From nobody Fri Apr 26 05:57:31 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673632553; cv=none; d=zohomail.com; s=zohoarc; b=RQhXVCHsBOquUU8wcC+HuINJaUNePtWyF55EyfwBVv+OoniA7fszj7FdMkvWArx/cpCo4ACAM+8M0MZPZWkuOa8IzDTgzbkrejNGr/5Dby32cbXh2rMOS5ycJPQapCTJTxS9HfqkXS/4AD83wT19AdAdxjDiA6Mmizvjm9thy3U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673632553; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DOI8/iNH0q6l/+yMdTICroh3zdczF3J2qooInPAT9oE=; b=m2x7qHha99jwizODZA8QBYQxWo60DzZd3pdXjGxX6C+Twor2R3RqtXK7DK/XSGbr0voVpYejYS5zllibTlr0lhXoFxtmFgc3bKQf7oXl/7DzSeC26/XT+HocG/ocQ4YT8RpceAkXQ+4cnAHcGvvLDxcemLn3REAA5bcB4OK5nRs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673632553055805.4230078790968; Fri, 13 Jan 2023 09:55:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pGOEa-0001DO-9X; Fri, 13 Jan 2023 12:52:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGOEN-00010G-TK for qemu-devel@nongnu.org; Fri, 13 Jan 2023 12:52:43 -0500 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGOEM-0001YT-2G for qemu-devel@nongnu.org; Fri, 13 Jan 2023 12:52:43 -0500 Received: by mail-oi1-x22c.google.com with SMTP id h185so18272439oif.5 for ; Fri, 13 Jan 2023 09:52:41 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id 2-20020aca0702000000b00363ea5be014sm9549276oih.3.2023.01.13.09.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:52:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DOI8/iNH0q6l/+yMdTICroh3zdczF3J2qooInPAT9oE=; b=RVBiQun9XRl8KInbmhhawpk6XxxloM0jX+ADLqXprtKLR0Ih7x0dkeRU2B9BRHmvXr wDrS8gBiLOBkbiXnXoqZoTeSeW+cPxchsT8LgaWwMte274DKv7NFBBadIB9IEyPK+2+j Zj3xi/3p20H/93sIhLBht7CiBNLG3u8+WIjPbPRsCg3ZVDHLB4oQnuVQiBYhRMLvTa9k oSm2tmMeGh4kOpAAQc48R/zo8lc0kBoqByqqhyicoP6StyxShiqAv4qtAF/otYtj9q86 ptSy2DzIOnPo2v25ZoOCB2EtN1AeUUFzrmaBlYSPkPQKFY3n0/4t1VNJDlhDyigLnKTv zg8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DOI8/iNH0q6l/+yMdTICroh3zdczF3J2qooInPAT9oE=; b=12MSEEZW9P29ws9uxVg3s+tX7jkLJRuLDYQUwJY/LL8SUNwsdaSSQ9buTGNzKG+pJu komXe23DGSz1jy5f7uX7NTvuGDm472gQASjY/EWCn4MAjkMfJ8fsSzk9oQDpFQa41D2n uv6e4xTneLFwx9FegjlVQIJc3RteqyvHoiLi7khswNghk6skZ5WqIeZ5z7+FWElXoKEA 5HrodbuB9ruxBYUJ2miZpE8hErz8JtI7I2cP4kTwJ0jX/2RtZ1LFYYw8E4WbROIy41bj CfWcTItHccSgCdCVZ2Y2DWg0XZG0QYTY5mGG33h6P7UfVVZJDeK4i4nIi2LBiqFpQeRe A8AQ== X-Gm-Message-State: AFqh2koubJ+FyXmDWPhQMbUnY1z0V5PnDlRvpvcaS7Vew+/y17PFKi3R NYgGwxJ4HK4jwn22hd9Zgc9HUNJiVlJ5Ksi9+GI= X-Google-Smtp-Source: AMrXdXs6o9QIBwQamHhUW5EiVMXRubpJdXKLlkWI2pkOP4cu61snHCusURQIa0jtCdPFh5aA3zFXcA== X-Received: by 2002:a05:6808:238f:b0:360:d951:28bf with SMTP id bp15-20020a056808238f00b00360d95128bfmr7025696oib.19.1673632359407; Fri, 13 Jan 2023 09:52:39 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng.cn@gmail.com, Daniel Henrique Barboza Subject: [PATCH v2 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() Date: Fri, 13 Jan 2023 14:52:29 -0300 Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113175230.473975-1-dbarboza@ventanamicro.com> References: <20230113175230.473975-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673632554190100001 Content-Type: text/plain; charset="utf-8" There is an informal contract between the cpu_init() functions and riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the default settings were loaded via register_cpu_props() and do validations to set env.misa_ext. If it's not zero, skip this whole process and assume that the board somehow did everything. At this moment, all SiFive CPUs are setting a non-zero misa_ext during their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This causes problems when the code being skipped in riscv_cpu_realize() contains fixes or assumptions that affects all CPUs, meaning that SiFive CPUs are missing out. To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attributes needs to be set during cpu_init() time. At this moment this is being done in register_cpu_props(). The SiFive boards are setting their own extensions during cpu_init() though, meaning that they don't want all the defaults from register_cpu_props(). Let's move the contract between *_cpu_init() and riscv_cpu_realize() to register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext was set and, if that's the case, set all relevant cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' =3D 0 case as is today, i.e. loading all the defaults from riscv_cpu_extensions[]. register_cpu_props() can then be called by all the cpu_init() functions, including the SiFive ones. This will make all CPUs behave more in line with what riscv_cpu_realize() expects. This will also make the cpu_init() functions even more alike, but at this moment we would need some design changes in how we're initializing extensions/attributes (e.g. some CPUs are setting cfg options after register_cpu_props(), so we can't simply add the function to a common post_init() hook) to make a common cpu_init() code across all CPUs. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 4 ++++ 2 files changed, 44 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a2e6238bd7..e682102c2a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -256,6 +256,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } =20 @@ -265,6 +266,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -299,6 +301,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } =20 @@ -308,6 +311,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -318,6 +322,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu =3D false; cpu->cfg.epmp =3D true; @@ -329,6 +334,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -1083,10 +1089,44 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +/* + * Register CPU props based on env.misa_ext. If a non-zero + * value was set, register only the required cpu->cfg.ext_* + * properties and leave. env.misa_ext =3D 0 means that we want + * all the default properties to be registered. + */ static void register_cpu_props(DeviceState *dev) { + RISCVCPU *cpu =3D RISCV_CPU(OBJECT(dev)); + uint32_t misa_ext =3D cpu->env.misa_ext; Property *prop; =20 + /* + * If misa_ext is not zero, set cfg properties now to + * allow them to be read during riscv_cpu_realize() + * later on. + */ + if (cpu->env.misa_ext !=3D 0) { + cpu->cfg.ext_i =3D misa_ext & RVI; + cpu->cfg.ext_e =3D misa_ext & RVE; + cpu->cfg.ext_m =3D misa_ext & RVM; + cpu->cfg.ext_a =3D misa_ext & RVA; + cpu->cfg.ext_f =3D misa_ext & RVF; + cpu->cfg.ext_d =3D misa_ext & RVD; + cpu->cfg.ext_v =3D misa_ext & RVV; + cpu->cfg.ext_c =3D misa_ext & RVC; + cpu->cfg.ext_s =3D misa_ext & RVS; + cpu->cfg.ext_u =3D misa_ext & RVU; + cpu->cfg.ext_h =3D misa_ext & RVH; + cpu->cfg.ext_j =3D misa_ext & RVJ; + + /* + * We don't want to set the default riscv_cpu_extensions + * in this case. + */ + return; + } + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 61a9a40958..bcf0826753 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -63,6 +63,10 @@ =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 +/* + * Consider updating register_cpu_props() when adding + * new MISA bits here. + */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') --=20 2.39.0 From nobody Fri Apr 26 05:57:31 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673632677; cv=none; d=zohomail.com; s=zohoarc; b=a0yZ2LO6b0eCCskd1pf4ika2WiEgv2lqLf8PpMtQfcyiLwQC5BUCwXB1PZyHrhA7tRGZMjHoegsUuHPC1GpQnVxnj6k3n3dmaQUy4q4Eoa8N5J6fLM3qHQI9i5E9/TPEKsA3vGC6pxNf2OZTftk4+YK9xg7uDqKyk6dywJUvShc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673632677; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+M3ohrTeofqSkxQ7pQ8d32nm7gQpOvTOJJgz+5YPODI=; b=lARvAmIDuMnTMwX42r67bW45ap139Ensvfnpc99tRK3pBw/zOoaJhmhgUji4goz0TDIQ1RUPgrIIsXje0nFFrIhmTcjPQJlrQEKnMyNxNJ0mPpXAaPsGmEIZyJ99HwW3hO4RhVwL5w7r2c5w/T3LmVsYXz4PS0oIbWJLxeT+Ow4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673632677861335.479387495113; Fri, 13 Jan 2023 09:57:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pGOEa-0001GD-V0; Fri, 13 Jan 2023 12:52:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGOER-000154-SW for qemu-devel@nongnu.org; Fri, 13 Jan 2023 12:52:51 -0500 Received: from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGOEP-0001ZD-Pv for qemu-devel@nongnu.org; Fri, 13 Jan 2023 12:52:47 -0500 Received: by mail-oi1-x235.google.com with SMTP id i5so35106oih.11 for ; Fri, 13 Jan 2023 09:52:44 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id 2-20020aca0702000000b00363ea5be014sm9549276oih.3.2023.01.13.09.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:52:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+M3ohrTeofqSkxQ7pQ8d32nm7gQpOvTOJJgz+5YPODI=; b=I3Bqn2WaKfFzvTGHB1XDo+/dS7wrPeIblMrVgn7Ot7asibUjWTd07osgrAAD9XDaWS H0fbwOOd8sXVAiBdZRAmboUXZ7UnKwNgoN6Ypi0+zSZ/NkfCLiSAd+SarTRljGdwDupD xlBSbyALyUaygBe5TmNYZg9rGH3r6K45Dmp9p8usDPwZxC9hA3qhllfUQOUKqh6dZkdM ocbwVIBDM43qxVYy3Q0B+2Oww9wXopQg5ncTjEzJFGR+UYeM4M1SXDcqE2rYH9bjM5Iq oH+EoBQkyDfP5Ev94qDa5MScn5KEmBPy85QwTy/LjzI1IxJT6590E+oEPBLdMT7ldgZS P7aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+M3ohrTeofqSkxQ7pQ8d32nm7gQpOvTOJJgz+5YPODI=; b=Rle3iX1RoaVtNXwLMcdlWV/Anb+epHT3NTCkleuDQO5u4Mz6P74gPvue8WoEcc14hi ioj7+qxUxR+KrEawbCntakhN/X2XEdVO3DFoGxwRB47hWID8c43ik0x9a+dEmv17PFvG /LgIMPBUGTlEQBRPpdYNNngIaSRI97XTMxnbsHtak3XTaGB4W8MkKee8GhjEtUFkmQkq M3fe2FezW9n/XLbdJ/LFxzRKY9Dw/7njhmi++ZDxu50eN3OsHfRNbkd7lvY6bBmVvbtq lIa0V2Og0bv16LQH6AQcnbjtj3kP8RyjzgwicF/AYePOYlJ73cyfey8j5KMDWrlpLe83 YGXw== X-Gm-Message-State: AFqh2kq4LnSjNFpL0oljz8lBRWv4ys3Jahqdx2bksqWfj8Ni2NOEYLp4 UlgQmTeYgzhVSP/abAVLOfITNPqBwBw2/osfuRg= X-Google-Smtp-Source: AMrXdXtKIeD/7iP4Pt8RPrlRQs3ONt642d3Zw3NxvfGwr+L25uqxIN3S4IzaiuV+x+x/hbmGEuYJgg== X-Received: by 2002:aca:ba08:0:b0:363:b22:6532 with SMTP id k8-20020acaba08000000b003630b226532mr33463790oif.7.1673632362225; Fri, 13 Jan 2023 09:52:42 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng.cn@gmail.com, Daniel Henrique Barboza Subject: [PATCH v2 2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Date: Fri, 13 Jan 2023 14:52:30 -0300 Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113175230.473975-1-dbarboza@ventanamicro.com> References: <20230113175230.473975-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673632679048100001 Content-Type: text/plain; charset="utf-8" All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, meaning that there's no reason to skip all the misa validation and setup if misa_ext was set beforehand - especially since we're setting an updated value in set_misa() in the end. Put this code chunk into a new riscv_cpu_validate_set_extensions() helper and always execute it regardless of what the board set in env->misa_ext. This will put more responsibility in how each board is going to init their attributes and extensions if they're not using the defaults. It'll also allow realize() to do its job looking only at the extensions enabled per se, not corner cases that some CPUs might have, and we won't have to change multiple code paths to fix or change how extensions work. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis [ Changes by AF: - Rebase ] Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 399 +++++++++++++++++++++++---------------------- 1 file changed, 205 insertions(+), 194 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e682102c2a..c192d96a94 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -625,6 +625,207 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) } } =20 +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly, doing a set_misa() in the end. + */ +static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + uint32_t ext =3D 0; + + /* Do some ISA extension error checking */ + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + cpu->cfg.ext_a && cpu->cfg.ext_f && + cpu->cfg.ext_d && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu->cfg.ext_i =3D true; + cpu->cfg.ext_m =3D true; + cpu->cfg.ext_a =3D true; + cpu->cfg.ext_f =3D true; + cpu->cfg.ext_d =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.ext_ifencei =3D true; + } + + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers= "); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { + error_setg(errp, "V extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + /* Set the ISA extensions, checks should have happened above */ + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx =3D true; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (cpu->cfg.ext_f) { + error_setg(errp, + "Zfinx cannot be supported together with F extension"); + return; + } + } + + if (cpu->cfg.ext_zk) { + cpu->cfg.ext_zkn =3D true; + cpu->cfg.ext_zkr =3D true; + cpu->cfg.ext_zkt =3D true; + } + + if (cpu->cfg.ext_zkn) { + cpu->cfg.ext_zbkb =3D true; + cpu->cfg.ext_zbkc =3D true; + cpu->cfg.ext_zbkx =3D true; + cpu->cfg.ext_zkne =3D true; + cpu->cfg.ext_zknd =3D true; + cpu->cfg.ext_zknh =3D true; + } + + if (cpu->cfg.ext_zks) { + cpu->cfg.ext_zbkb =3D true; + cpu->cfg.ext_zbkc =3D true; + cpu->cfg.ext_zbkx =3D true; + cpu->cfg.ext_zksed =3D true; + cpu->cfg.ext_zksh =3D true; + } + + if (cpu->cfg.ext_i) { + ext |=3D RVI; + } + if (cpu->cfg.ext_e) { + ext |=3D RVE; + } + if (cpu->cfg.ext_m) { + ext |=3D RVM; + } + if (cpu->cfg.ext_a) { + ext |=3D RVA; + } + if (cpu->cfg.ext_f) { + ext |=3D RVF; + } + if (cpu->cfg.ext_d) { + ext |=3D RVD; + } + if (cpu->cfg.ext_c) { + ext |=3D RVC; + } + if (cpu->cfg.ext_s) { + ext |=3D RVS; + } + if (cpu->cfg.ext_u) { + ext |=3D RVU; + } + if (cpu->cfg.ext_h) { + ext |=3D RVH; + } + if (cpu->cfg.ext_v) { + int vext_version =3D VEXT_VERSION_1_00_0; + ext |=3D RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { + vext_version =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); + } + if (cpu->cfg.ext_j) { + ext |=3D RVJ; + } + + set_misa(env, env->misa_mxl, ext); +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -720,200 +921,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } assert(env->misa_mxl_max =3D=3D env->misa_mxl); =20 - /* If only MISA_EXT is unset for misa, then set it from properties */ - if (env->misa_ext =3D=3D 0) { - uint32_t ext =3D 0; - - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)= ) { - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i =3D true; - cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; - cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; - cpu->cfg.ext_icsr =3D true; - cpu->cfg.ext_ifencei =3D true; - } - - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { - error_setg(errp, - "Setting S extension without U extension is illegal= "); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x regis= ters"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { - error_setg(errp, "D extension requires F extension"); - return; - } - - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { - error_setg(errp, "V extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_= f) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension= "); - return; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || - cpu->cfg.ext_zhinxmin) { - cpu->cfg.ext_zfinx =3D true; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (cpu->cfg.ext_f) { - error_setg(errp, - "Zfinx cannot be supported together with F extension"); - return; - } - } - - if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn =3D true; - cpu->cfg.ext_zkr =3D true; - cpu->cfg.ext_zkt =3D true; - } - - if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zknh =3D true; - } - - if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; - } - - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } - if (cpu->cfg.ext_v) { - int vext_version =3D VEXT_VERSION_1_00_0; - ext |=3D RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLE= N " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELE= N " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); - } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } - - set_misa(env, env->misa_mxl, ext); + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 #ifndef CONFIG_USER_ONLY --=20 2.39.0