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Iglesias" , qemu-trivial@nongnu.org, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/4] iothread: Remove unused IOThreadClass / IOTHREAD_CLASS Date: Fri, 13 Jan 2023 21:01:35 +0100 Message-Id: <20230113200138.52869-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113200138.52869-1-philmd@linaro.org> References: <20230113200138.52869-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673640175270100001 Since commit be8d853766 ("iothread: add I/O thread object") we never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(), remove these definitions. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Stefan Hajnoczi --- iothread.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/iothread.c b/iothread.c index 3862a64471..b41c305bd9 100644 --- a/iothread.c +++ b/iothread.c @@ -25,10 +25,6 @@ #include "qemu/rcu.h" #include "qemu/main-loop.h" =20 -typedef ObjectClass IOThreadClass; - -DECLARE_CLASS_CHECKERS(IOThreadClass, IOTHREAD, - TYPE_IOTHREAD) =20 #ifdef CONFIG_POSIX /* Benchmark results from 2016 on NVMe SSD drives show max polling times a= round --=20 2.38.1 From nobody Fri Apr 19 13:14:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673640227; cv=none; d=zohomail.com; s=zohoarc; b=aX8OLtONE0PffBJHvWlfDfs4G06sCwSR3fVRzw9j5y54GGmA0qJ38lbT2jT3cyM/XVgdDOMwa0YAOvq/3yDuUFbMNNTSPmXB+UFxhQHbG7ahi8xG1Dfnw+pirmFQ4+5MHvptwoYq2rop1R5OqdruMtj34JzeC9E6Qfdcz0iACfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673640227; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tt1mSx+5mpU6vHqq0Q13XSPghb0/iRRovVdL8d0eEs4=; b=TERdHNkBISDYpbhirjqlYLdJMMoyiVJJJOVv+pMjRzePCQuNA73jRkFnulT4dCQz9969dkFW+YjhwMsAGPcq0aAdqEykjtSnVE5gleRFvnbyQiU73m6uHIyde42Hu763hPD4Z6LUEbKa6pIdEqGouMBtyKKhBqvZ7Tf2B4htYXk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673640227636479.853161032481; Fri, 13 Jan 2023 12:03:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pGQFZ-0003dC-Gl; Fri, 13 Jan 2023 15:02:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGQFQ-0003YS-E3 for qemu-devel@nongnu.org; Fri, 13 Jan 2023 15:01:56 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGQFO-0006mc-4H for qemu-devel@nongnu.org; Fri, 13 Jan 2023 15:01:56 -0500 Received: by mail-wr1-x430.google.com with SMTP id b5so879197wrn.0 for ; Fri, 13 Jan 2023 12:01:53 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id i6-20020adfe486000000b002423dc3b1a9sm19290078wrm.52.2023.01.13.12.01.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Jan 2023 12:01:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tt1mSx+5mpU6vHqq0Q13XSPghb0/iRRovVdL8d0eEs4=; b=Cn2mKzV6ctZxmYKSeDpjr1h/46sokNPZxnhqsyq9C4ZKQJZgtxB03U5xSMilrwXxVX E40iS+jhZ/l4JE/VQMeeL2pJ0eRed0kMVJ4m3KUUG5bxiVp3Z4nejh7Fx4l1bvkQwYDM aM3tc4wSGT9EZcdVFCl8C+0bP10TKBNmpwpdgEbHDp1QaBeMIis9VOZ4Eq+A+UNsIMcq wSHz3kXSfzcClpRU2nPSTHkEIAX0dL3Ofxo2OtvhyPdJY+wCJY+sGlppNT97B0rmN7eB 3GMk4U3PmZXWy+YsBo6fbqTd3KOw0txTdYnMsZ7NzLH4+7sEReKvZbqNrF7JXOwZZZbW AbMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tt1mSx+5mpU6vHqq0Q13XSPghb0/iRRovVdL8d0eEs4=; b=yk7uvltuHCViiwLLtkj0BhFzVmECH8fA4pPSnXUnlQVBc0cCc/eL//uE2FHG1NQWv1 m/Ur68rJoOY1hnylYiuPpSOOukkSW/iU0djtm92+4FMW/WByWHPz+0km9+viLTuOnJEx wemwZIrcxH1bmsCs4WUw/305eXBwoc9S1O/EtJkN6WxYKPGzs1vU5stwxTlaiYbGL8V8 uSQi0udl4U/QcsqZSSYnC4b/aVhwkibW4C+7sao0ESP4xIJIQlUTq9BUfABjqD52y3/e PizQiZJjWQt7ca2z+mmvIM8X3p8RDj3WKFumOdEFuxv92gHt9wqHcuao2Rb2lEsPYkcc 15qA== X-Gm-Message-State: AFqh2kr7Kj/FS2s2w/zG+OeZInVBOe/srLQ03gQ4scHolYsBUVEubER3 g/aG0j/PjCWF7HeajGSkm2wN45kTqb3UKtd5 X-Google-Smtp-Source: AMrXdXtTL6D44qTH0r/JeMhSbTQWTT6SDAl+BPXmv3UqNUxOACPqZFSiiTntWD2qbP94eQCGMNHM0Q== X-Received: by 2002:adf:e181:0:b0:2b1:c393:cbe with SMTP id az1-20020adfe181000000b002b1c3930cbemr882252wrb.11.1673640112416; Fri, 13 Jan 2023 12:01:52 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , qemu-arm@nongnu.org, Peter Maydell , qemu-ppc@nongnu.org, "Edgar E. Iglesias" , qemu-trivial@nongnu.org, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/4] hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() Date: Fri, 13 Jan 2023 21:01:36 +0100 Message-Id: <20230113200138.52869-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113200138.52869-1-philmd@linaro.org> References: <20230113200138.52869-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673640229535100001 QOM *DECLARE* macros expect a typedef as first argument, not a structure. Replace 'struct IRQState' by 'IRQState' to avoid when modifying the macros: ../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a d= efinition DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, ^ Use OBJECT_DECLARE_SIMPLE_TYPE instead of DECLARE_INSTANCE_CHECKER. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Stefan Hajnoczi --- hw/core/irq.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/core/irq.c b/hw/core/irq.c index 3623f711fe..3f14e2dda7 100644 --- a/hw/core/irq.c +++ b/hw/core/irq.c @@ -26,8 +26,7 @@ #include "hw/irq.h" #include "qom/object.h" =20 -DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, - TYPE_IRQ) +OBJECT_DECLARE_SIMPLE_TYPE(IRQState, IRQ) =20 struct IRQState { Object parent_obj; @@ -68,7 +67,7 @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, vo= id *opaque, int n) =20 qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n) { - struct IRQState *irq; + IRQState *irq; =20 irq =3D IRQ(object_new(TYPE_IRQ)); irq->handler =3D handler; @@ -94,7 +93,7 @@ void qemu_free_irq(qemu_irq irq) =20 static void qemu_notirq(void *opaque, int line, int level) { - struct IRQState *irq =3D opaque; + IRQState *irq =3D opaque; =20 irq->handler(irq->opaque, irq->n, !level); } @@ -120,7 +119,7 @@ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_= handler handler, int n) static const TypeInfo irq_type_info =3D { .name =3D TYPE_IRQ, .parent =3D TYPE_OBJECT, - .instance_size =3D sizeof(struct IRQState), + .instance_size =3D sizeof(IRQState), }; =20 static void irq_register_types(void) --=20 2.38.1 From nobody Fri Apr 19 13:14:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673640234; cv=none; d=zohomail.com; s=zohoarc; b=etaehS+vo8PU/bJifVGyTd7Dj25uKwUSUg/g33S6Ovowl2N86mD9PFgl67LGk6f6Zg4+jF/jxrvMv4UKOC5tftVQMLEuQqa8g1cLAd9WPDTKin39xmQjDhaDdfCHf3Y8wj/OQx655b9CnC5NN1mxW+xDqfM7GkSex5/fDuboIjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Fri, 13 Jan 2023 12:01:58 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , qemu-arm@nongnu.org, Peter Maydell , qemu-ppc@nongnu.org, "Edgar E. Iglesias" , qemu-trivial@nongnu.org, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/4] hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() Date: Fri, 13 Jan 2023 21:01:37 +0100 Message-Id: <20230113200138.52869-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113200138.52869-1-philmd@linaro.org> References: <20230113200138.52869-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673640235383100001 Missed during automatic conversion from commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Stefan Hajnoczi --- include/hw/or-irq.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h index f2f0a27381..131abc2e0c 100644 --- a/include/hw/or-irq.h +++ b/include/hw/or-irq.h @@ -37,8 +37,7 @@ =20 typedef struct OrIRQState qemu_or_irq; =20 -DECLARE_INSTANCE_CHECKER(qemu_or_irq, OR_IRQ, - TYPE_OR_IRQ) +OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ) =20 struct OrIRQState { DeviceState parent_obj; --=20 2.38.1 From nobody Fri Apr 19 13:14:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673640207; cv=none; d=zohomail.com; s=zohoarc; b=m27bfvjs6wewn9SzDyLsW/rjs/w3GpaaoBpBMm/x09XB5zPhAFSPjUo4rPG5feloNo1fcUw5DLrEU0SEgAqA8xOVf/TOJdLHNhGz5qxvkamXNxS+h9Ozp+deYtT9aYnizUhixHnhhzgr8rf/tjiYlFxQ9C89IAFq668LmkrSdfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673640207; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EG3Qe0kxJp7FPfJDFX/WhPOIuV6nKtCj0QjnSu6ovew=; b=LxTmwohtaHq33h9urgRnPdWzDN6fH68ghDmL3EOeVMEqxi8Iyjche/pCybfJTFY6MmD0nTqb0QEtM0p+2/uUieUKieT4dBAKdkAEsDqW/cs04YUhpskk/p90LipfpP6H35Nvz0MyJ3zkGmB9HSAscsc8NVDRF23hbbGuqBH/GV0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167364020761533.0691847379876; Fri, 13 Jan 2023 12:03:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pGQFh-0003he-6f; Fri, 13 Jan 2023 15:02:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGQFb-0003eI-Hj for qemu-devel@nongnu.org; Fri, 13 Jan 2023 15:02:08 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGQFZ-0006py-Fr for qemu-devel@nongnu.org; Fri, 13 Jan 2023 15:02:07 -0500 Received: by mail-wr1-x435.google.com with SMTP id v2so11048386wrw.10 for ; Fri, 13 Jan 2023 12:02:05 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id bw28-20020a0560001f9c00b002421888a011sm19372771wrb.69.2023.01.13.12.02.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Jan 2023 12:02:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EG3Qe0kxJp7FPfJDFX/WhPOIuV6nKtCj0QjnSu6ovew=; b=bCW6+6Y7sYBQTrsIVsNZzG7nNoCZivP0Y218So9k3HSfikw4IhRMbZ4erkiwK8tjgV FaC7uoPr3pWL3IoIJo94A5u/up8mzujC0031+EAVmZrorB+alqw552two50hHpszt1Ma zfFrCCgxBULncmr0qfZOhrQUzlltXNKQgPV0sHcODz3B9JWNoUVeZHLiGzfxzakh506w GiKp49umAXyUMwRjIxX8L6MpKGj5xZMnxjR6to5OF7fZmINePNzcY0grvby670ucJxok 0WmHD5Ga7UPH5ghitjX3D2mi9MQz4WyJDgBnLJGRc2Ww3utsplQbaGL4ZHNtFmhekGJZ FhNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EG3Qe0kxJp7FPfJDFX/WhPOIuV6nKtCj0QjnSu6ovew=; b=NLWtrdRE1kvF4VO2jG4Jn3T9P7AnwfbtxUVCuJKgZGLIfq4Ov04oNvo0OzowGBH3nr DolYJ3HLidStdJoHtAMG3EGHax5TXzTsfmTc0o+DW4y9lm4JPzOrFYuQMAUNVjJoYjfI Au4BoUE0KtWtHW91ecoMTVf2W4117v3HPg3ePGaHA/FWSuquMf/E8PTpMRYmnQ5HN/OE 30RcrWcWDMXbQyYycPc6GuTuflSG8+PycpN7OmWkV5o7zVL9z+4DQBcHL0eCSJLYhPeX HQb4ez3jB08r2c/erk0Lz8LCReYI/x3vamjMOPw3H+1lJ+UhbHS/yYfXSqlfGdDJl70P gp8Q== X-Gm-Message-State: AFqh2kq4oluMhjsR1kC3Cor0ywJUhNaC9RFQ8Re7XJx1frDlWeErxoYW ZkHUlOkDd/oMdG2YvuryGDNCLyW2149FvQRc X-Google-Smtp-Source: AMrXdXtd+6xpJJTh/3n9ABsZZ+03v4N8UU3BnVoQOuW0ENnhTSZ002CPU6tbsld+tou48MsdpYuk2w== X-Received: by 2002:a5d:6385:0:b0:2bd:e217:e1d with SMTP id p5-20020a5d6385000000b002bde2170e1dmr2710419wru.52.1673640123892; Fri, 13 Jan 2023 12:02:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , qemu-arm@nongnu.org, Peter Maydell , qemu-ppc@nongnu.org, "Edgar E. Iglesias" , qemu-trivial@nongnu.org, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/4] hw: Replace qemu_or_irq typedef by OrIRQState Date: Fri, 13 Jan 2023 21:01:38 +0100 Message-Id: <20230113200138.52869-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113200138.52869-1-philmd@linaro.org> References: <20230113200138.52869-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673640209319100001 OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState declaration for free. Besides, the QOM code style is to use the structure name as typedef, and QEMU style is to use Camel Case, so rename qemu_or_irq as OrIRQState. Mechanical change using: $ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Stefan Hajnoczi --- hw/arm/exynos4210.c | 4 ++-- hw/arm/mps2-tz.c | 2 +- hw/core/or-irq.c | 18 +++++++++--------- hw/pci-host/raven.c | 2 +- include/hw/arm/armsse.h | 6 +++--- include/hw/arm/bcm2835_peripherals.h | 2 +- include/hw/arm/exynos4210.h | 4 ++-- include/hw/arm/stm32f205_soc.h | 2 +- include/hw/arm/stm32f405_soc.h | 2 +- include/hw/arm/xlnx-versal.h | 6 +++--- include/hw/arm/xlnx-zynqmp.h | 2 +- include/hw/or-irq.h | 2 -- 12 files changed, 25 insertions(+), 27 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 8dafa2215b..6f2dda13f6 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -507,7 +507,7 @@ static uint64_t exynos4210_calc_affinity(int cpu) return (0x9 << ARM_AFF1_SHIFT) | cpu; } =20 -static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, +static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate, qemu_irq irq, int nreq, int nevents, int = width) { SysBusDevice *busdev; @@ -806,7 +806,7 @@ static void exynos4210_init(Object *obj) =20 for (i =3D 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { char *name =3D g_strdup_printf("pl330-irq-orgate%d", i); - qemu_or_irq *orgate =3D &s->pl330_irq_orgate[i]; + OrIRQState *orgate =3D &s->pl330_irq_orgate[i]; =20 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); g_free(name); diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 284c09c91d..07aecd9497 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -152,7 +152,7 @@ struct MPS2TZMachineState { TZMSC msc[4]; CMSDKAPBUART uart[6]; SplitIRQ sec_resp_splitter; - qemu_or_irq uart_irq_orgate; + OrIRQState uart_irq_orgate; DeviceState *lan9118; SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c index d8f3754e96..1df4bc05a7 100644 --- a/hw/core/or-irq.c +++ b/hw/core/or-irq.c @@ -31,7 +31,7 @@ =20 static void or_irq_handler(void *opaque, int n, int level) { - qemu_or_irq *s =3D OR_IRQ(opaque); + OrIRQState *s =3D OR_IRQ(opaque); int or_level =3D 0; int i; =20 @@ -46,7 +46,7 @@ static void or_irq_handler(void *opaque, int n, int level) =20 static void or_irq_reset(DeviceState *dev) { - qemu_or_irq *s =3D OR_IRQ(dev); + OrIRQState *s =3D OR_IRQ(dev); int i; =20 for (i =3D 0; i < MAX_OR_LINES; i++) { @@ -56,7 +56,7 @@ static void or_irq_reset(DeviceState *dev) =20 static void or_irq_realize(DeviceState *dev, Error **errp) { - qemu_or_irq *s =3D OR_IRQ(dev); + OrIRQState *s =3D OR_IRQ(dev); =20 assert(s->num_lines <=3D MAX_OR_LINES); =20 @@ -65,7 +65,7 @@ static void or_irq_realize(DeviceState *dev, Error **errp) =20 static void or_irq_init(Object *obj) { - qemu_or_irq *s =3D OR_IRQ(obj); + OrIRQState *s =3D OR_IRQ(obj); =20 qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1); } @@ -84,7 +84,7 @@ static void or_irq_init(Object *obj) =20 static bool vmstate_extras_needed(void *opaque) { - qemu_or_irq *s =3D OR_IRQ(opaque); + OrIRQState *s =3D OR_IRQ(opaque); =20 return s->num_lines >=3D OLD_MAX_OR_LINES; } @@ -95,7 +95,7 @@ static const VMStateDescription vmstate_or_irq_extras =3D= { .minimum_version_id =3D 1, .needed =3D vmstate_extras_needed, .fields =3D (VMStateField[]) { - VMSTATE_VARRAY_UINT16_UNSAFE(levels, qemu_or_irq, num_lines, 0, + VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0, vmstate_info_bool, bool), VMSTATE_END_OF_LIST(), }, @@ -106,7 +106,7 @@ static const VMStateDescription vmstate_or_irq =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_BOOL_SUB_ARRAY(levels, qemu_or_irq, 0, OLD_MAX_OR_LINES), + VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES), VMSTATE_END_OF_LIST(), }, .subsections =3D (const VMStateDescription*[]) { @@ -116,7 +116,7 @@ static const VMStateDescription vmstate_or_irq =3D { }; =20 static Property or_irq_properties[] =3D { - DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1), + DEFINE_PROP_UINT16("num-lines", OrIRQState, num_lines, 1), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -136,7 +136,7 @@ static void or_irq_class_init(ObjectClass *klass, void = *data) static const TypeInfo or_irq_type_info =3D { .name =3D TYPE_OR_IRQ, .parent =3D TYPE_DEVICE, - .instance_size =3D sizeof(qemu_or_irq), + .instance_size =3D sizeof(OrIRQState), .instance_init =3D or_irq_init, .class_init =3D or_irq_class_init, }; diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index 2c96ddf8fe..5e0a5b9303 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -60,7 +60,7 @@ DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRI= DGE, struct PRePPCIState { PCIHostState parent_obj; =20 - qemu_or_irq *or_irq; + OrIRQState *or_irq; qemu_irq pci_irqs[PCI_NUM_PINS]; PCIBus pci_bus; AddressSpace pci_io_as; diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9648e7a419..cd0931d0a0 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -155,12 +155,12 @@ struct ARMSSE { TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; CMSDKAPBTimer timer[3]; - qemu_or_irq ppc_irq_orgate; + OrIRQState ppc_irq_orgate; SplitIRQ sec_resp_splitter; SplitIRQ ppc_irq_splitter[NUM_PPCS]; SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; - qemu_or_irq mpc_irq_orgate; - qemu_or_irq nmi_orgate; + OrIRQState mpc_irq_orgate; + OrIRQState nmi_orgate; =20 SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS]; =20 diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index c9d25d493e..d724a2fc28 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -56,7 +56,7 @@ struct BCM2835PeripheralState { BCM2835AuxState aux; BCM2835FBState fb; BCM2835DMAState dma; - qemu_or_irq orgated_dma_irq; + OrIRQState orgated_dma_irq; BCM2835ICState ic; BCM2835PropertyState property; BCM2835RngState rng; diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 97353f1c02..68db19f0cb 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -96,8 +96,8 @@ struct Exynos4210State { MemoryRegion boot_secondary; MemoryRegion bootreg_mem; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; - qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; - qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; + OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA]; + OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS]; A9MPPrivState a9mpcore; Exynos4210GicState ext_gic; Exynos4210CombinerState int_combiner; diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 849d3ed889..5a4f776264 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -63,7 +63,7 @@ struct STM32F205State { STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; =20 - qemu_or_irq *adc_irqs; + OrIRQState *adc_irqs; =20 MemoryRegion sram; MemoryRegion flash; diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 249ab5434e..c968ce3ab2 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -63,7 +63,7 @@ struct STM32F405State { STM32F4xxExtiState exti; STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; - qemu_or_irq adc_irqs; + OrIRQState adc_irqs; STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; =20 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index cbe8a19c10..b6786e9832 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -85,7 +85,7 @@ struct Versal { } rpu; =20 struct { - qemu_or_irq irq_orgate; + OrIRQState irq_orgate; XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; } xram; =20 @@ -103,7 +103,7 @@ struct Versal { XlnxCSUDMA dma_src; XlnxCSUDMA dma_dst; MemoryRegion linear_mr; - qemu_or_irq irq_orgate; + OrIRQState irq_orgate; } ospi; } iou; =20 @@ -113,7 +113,7 @@ struct Versal { XlnxVersalEFuseCtrl efuse_ctrl; XlnxVersalEFuseCache efuse_cache; =20 - qemu_or_irq apb_irq_orgate; + OrIRQState apb_irq_orgate; } pmc; =20 struct { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 20bdf894aa..687c75e3b0 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -130,7 +130,7 @@ struct XlnxZynqMPState { XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; XlnxCSUDMA qspi_dma; - qemu_or_irq qspi_irq_orgate; + OrIRQState qspi_irq_orgate; XlnxZynqMPAPUCtrl apu_ctrl; XlnxZynqMPCRF crf; CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h index 131abc2e0c..c0a42f3711 100644 --- a/include/hw/or-irq.h +++ b/include/hw/or-irq.h @@ -35,8 +35,6 @@ */ #define MAX_OR_LINES 48 =20 -typedef struct OrIRQState qemu_or_irq; - OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ) =20 struct OrIRQState { --=20 2.38.1