From nobody Tue May 13 04:33:55 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673656849335998.4959598404895; Fri, 13 Jan 2023 16:40:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pGUa2-0004hT-Rx; Fri, 13 Jan 2023 19:39:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGUa0-0004ge-3E for qemu-devel@nongnu.org; Fri, 13 Jan 2023 19:39:28 -0500 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGUZv-0005Md-Lr for qemu-devel@nongnu.org; Fri, 13 Jan 2023 19:39:27 -0500 Received: from i7.infradead.org ([2001:8b0:10b:1:21e:67ff:fecb:7a92]) by casper.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGUZy-006abu-BP; Sat, 14 Jan 2023 00:39:26 +0000 Received: from dwoodhou by i7.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGUZk-001C2F-SB; Sat, 14 Jan 2023 00:39:12 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description; bh=JqQCDIJ+1Gc1rVXAy99kDVBLCB7ZHbgitI9/ZFJtP1g=; b=Y1UNdwIB7FM8tDr/ayAYooH1IR JoIQwv5uYOoyqcwOcmk0zEYGgHnGMzXZbxqio07UxsXMmuUw1KadLli1QtoyDR06RCtrv4bjSvixT Tq7aQFfI9HZcjyWrWGCkBz3LEq/7xQZkwRF/1QneXOxq781wIvyX52n3m9xUZWjdaX7utQtgGX4/F jHPLNNLfydnOcZcPjjMb6LxN1uZMIchyeZFksjmp6PTag1AcNo52D9/a5M5Kculo4W7YhS/qVk8ON iW4o7Ue082vbrr5DIVTx78xGhQK1inVmIs0sbiqf1gNbOEXvAuN2MdwpCg7ZBh9h/oFmwl2SQvAWc jRoJ0Ksw==; From: David Woodhouse To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Paul Durrant , Joao Martins , Ankur Arora , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Juan Quintela , "Dr . David Alan Gilbert" , Claudio Fontana , Julien Grall , "Michael S. Tsirkin" , arcel Apfelbaum Subject: [RFC PATCH 2/5] hw/xen: Implement emulated PIRQ hypercall support Date: Sat, 14 Jan 2023 00:39:06 +0000 Message-Id: <20230114003909.284331-3-dwmw2@infradead.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230114003909.284331-1-dwmw2@infradead.org> References: <20230114003909.284331-1-dwmw2@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SRS-Rewrite: SMTP reverse-path rewritten from by casper.infradead.org. See http://www.infradead.org/rpr.html Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2001:8b0:10b:1236::1; envelope-from=BATV+cc7f48ec5f75d1861b59+7083+infradead.org+dwmw2@casper.srs.infradead.org; helo=casper.infradead.org X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1673656849684100001 From: David Woodhouse This wires up the basic infrastructure but the actual interrupts aren't there yet, so don't advertise it to the guest. Signed-off-by: David Woodhouse --- hw/i386/kvm/trace-events | 4 + hw/i386/kvm/trace.h | 1 + hw/i386/kvm/xen_evtchn.c | 265 +++++++++++++++++++++++++++++++++++++- hw/i386/kvm/xen_evtchn.h | 2 + meson.build | 1 + target/i386/kvm/xen-emu.c | 15 +++ 6 files changed, 283 insertions(+), 5 deletions(-) create mode 100644 hw/i386/kvm/trace-events create mode 100644 hw/i386/kvm/trace.h diff --git a/hw/i386/kvm/trace-events b/hw/i386/kvm/trace-events new file mode 100644 index 0000000000..04e60c5bb8 --- /dev/null +++ b/hw/i386/kvm/trace-events @@ -0,0 +1,4 @@ +kvm_xen_map_pirq(int pirq, int gsi) "pirq %d gsi %d" +kvm_xen_unmap_pirq(int pirq, int gsi) "pirq %d gsi %d" +kvm_xen_get_free_pirq(int pirq, int type) "pirq %d type %d" +kvm_xen_bind_pirq(int pirq, int port) "pirq %d port %d" diff --git a/hw/i386/kvm/trace.h b/hw/i386/kvm/trace.h new file mode 100644 index 0000000000..e55d0812fd --- /dev/null +++ b/hw/i386/kvm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_i386_kvm.h" diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c index fd83d052f7..82250daecb 100644 --- a/hw/i386/kvm/xen_evtchn.c +++ b/hw/i386/kvm/xen_evtchn.c @@ -23,6 +23,7 @@ #include "exec/target_page.h" #include "exec/address-spaces.h" #include "migration/vmstate.h" +#include "trace.h" =20 #include "hw/sysbus.h" #include "hw/xen/xen.h" @@ -105,6 +106,23 @@ struct xenevtchn_handle { #define PORT_INFO_TYPEVAL_REMOTE_QEMU 0x8000 #define PORT_INFO_TYPEVAL_REMOTE_PORT_MASK 0x7FFF =20 +#define MAX_XEN_PIRQ 0x1048 /* Empirically */ + +/* + * These 'emuirq' values are used by Xen in the LM stream... and yes, I am + * insane enough to think about guest-transparent live migration from actu= al + * Xen to QEMU, and ensuring that we can convert/consume the stream. + */ +#define IRQ_UNBOUND -1 +#define IRQ_PT -2 +#define IRQ_MSI_EMU -3 + + +struct pirq_info { + int gsi; + uint16_t port; +}; + struct XenEvtchnState { /*< private >*/ SysBusDevice busdev; @@ -120,6 +138,14 @@ struct XenEvtchnState { qemu_irq gsis[GSI_NUM_PINS]; =20 struct xenevtchn_handle *be_handles[EVTCHN_2L_NR_CHANNELS]; + + /* GSI =E2=86=92 PIRQ mapping (serialized) */ + uint16_t gsi_pirq[GSI_NUM_PINS]; + /* Bitmap of allocated PIRQs (serialized) */ + uint64_t pirq_inuse[DIV_ROUND_UP(MAX_XEN_PIRQ, 64)]; + + /* Per-PIRQ information (rebuilt on migration) */ + struct pirq_info pirq[MAX_XEN_PIRQ]; }; =20 struct XenEvtchnState *xen_evtchn_singleton; @@ -179,6 +205,9 @@ static const VMStateDescription xen_evtchn_vmstate =3D { VMSTATE_UINT32(nr_ports, XenEvtchnState), VMSTATE_STRUCT_VARRAY_UINT32(port_table, XenEvtchnState, nr_ports,= 1, xen_evtchn_port_vmstate, XenEvtchnPor= t), + VMSTATE_UINT16_ARRAY(gsi_pirq, XenEvtchnState, GSI_NUM_PINS), + VMSTATE_UINT64_ARRAY(pirq_inuse, XenEvtchnState, + DIV_ROUND_UP(MAX_XEN_PIRQ, 64)), VMSTATE_END_OF_LIST() } }; @@ -247,6 +276,21 @@ static void xen_evtchn_register_types(void) =20 type_init(xen_evtchn_register_types) =20 +static int pirq_bind_port(XenEvtchnState *s, int pirq, uint16_t port) +{ + assert(pirq < MAX_XEN_PIRQ); + + if (port && s->pirq[pirq].port) { + return -EBUSY; + } + + s->pirq[pirq].port =3D port; + trace_kvm_xen_bind_pirq(pirq, port); + + /* XX: We need to unmask MSI here, when we get to that */ + return 0; +} + static int set_callback_pci_intx(XenEvtchnState *s, uint64_t param) { PCMachineState *pcms =3D PC_MACHINE(qdev_get_machine()); @@ -881,6 +925,10 @@ static int close_port(XenEvtchnState *s, evtchn_port_t= port) case EVTCHNSTAT_closed: return -ENOENT; =20 + case EVTCHNSTAT_pirq: + pirq_bind_port(s, p->type_val, 0); + break; + case EVTCHNSTAT_virq: kvm_xen_set_vcpu_virq(virq_is_global(p->type_val) ? 0 : p->vcpu, p->type_val, 0); @@ -1075,6 +1123,35 @@ int xen_evtchn_bind_virq_op(struct evtchn_bind_virq = *virq) return ret; } =20 +int xen_evtchn_bind_pirq_op(struct evtchn_bind_pirq *pirq) +{ + XenEvtchnState *s =3D xen_evtchn_singleton; + int ret; + + if (!s) { + return -ENOTSUP; + } + + if (pirq->pirq >=3D MAX_XEN_PIRQ) { + return -EINVAL; + } + + QEMU_LOCK_GUARD(&s->port_lock); + + ret =3D allocate_port(s, 0, EVTCHNSTAT_pirq, pirq->pirq, + &pirq->port); + if (ret) { + return ret; + } + + ret =3D pirq_bind_port(s, pirq->pirq, pirq->port); + if (ret) { + free_port(s, pirq->port); + pirq->port =3D 0; + } + return ret; +} + int xen_evtchn_bind_ipi_op(struct evtchn_bind_ipi *ipi) { XenEvtchnState *s =3D xen_evtchn_singleton; @@ -1301,29 +1378,207 @@ int xen_evtchn_set_port(uint16_t port) return ret; } =20 +#define pirq_inuse_word(s, pirq) (s->pirq_inuse[((pirq) / 64)]) +#define pirq_inuse_bit(pirq) (1ULL << ((pirq) & 63)) + +#define pirq_inuse(s, pirq) (pirq_inuse_word(s, pirq) & pirq_inuse_bit(pir= q)) + +static int allocate_pirq(XenEvtchnState *s, int type, int gsi) +{ + uint16_t pirq; + + /* Preserve the allocation strategy that Xen has. It looks like + * we *never* give out PIRQ 0-15, we give out 16-nr_irqs_gsi only + * to GSIs (counting up from 16), and then we count backwards from + * the top for MSIs or when the GSI space is exhausted. */ + if (type =3D=3D MAP_PIRQ_TYPE_GSI) { + for (pirq =3D 16 ; pirq < GSI_NUM_PINS; pirq++) { + if (pirq_inuse(s, pirq)) { + continue; + } + + /* Found it */ + goto found; + } + } + for (pirq =3D MAX_XEN_PIRQ - 1; pirq >=3D GSI_NUM_PINS; pirq--) { + /* Skip whole words at a time when they're full */ + if (pirq_inuse_word(s, pirq) =3D=3D UINT64_MAX) { + pirq &=3D ~63ULL; + continue; + } + if (pirq_inuse(s, pirq)) { + continue; + } + + goto found; + } + return -ENOSPC; + + found: + pirq_inuse_word(s, pirq) |=3D pirq_inuse_bit(pirq); + if (gsi >=3D 0) { + assert(gsi <=3D GSI_NUM_PINS); + s->gsi_pirq[gsi] =3D pirq; + } + s->pirq[pirq].gsi =3D gsi; + return pirq; +} + int xen_physdev_map_pirq(struct physdev_map_pirq *map) { - return -ENOTSUP; + XenEvtchnState *s =3D xen_evtchn_singleton; + int pirq =3D map->pirq; + int gsi =3D map->index; + + if (!s) { + return -ENOTSUP; + } + + QEMU_LOCK_GUARD(&s->port_lock); + + if (map->domid !=3D DOMID_SELF && map->domid !=3D xen_domid) { + return -EPERM; + } + if (map->type !=3D MAP_PIRQ_TYPE_GSI) { + return -EINVAL; + } + if (gsi < 0 || gsi >=3D GSI_NUM_PINS) { + return -EINVAL; + } + + if (pirq < 0) { + pirq =3D allocate_pirq(s, map->type, gsi); + if (pirq < 0) { + return pirq; + } + map->pirq =3D pirq; + } else if (pirq > MAX_XEN_PIRQ) { + return -EINVAL; + } else { + /* User specified a valid-looking PIRQ#. Allow it if it is + * allocated and not yet bound, or if it is unallocated */ + if (pirq_inuse(s, pirq)) { + if (s->pirq[pirq].gsi !=3D IRQ_UNBOUND) { + return -EBUSY; + } + } else { + /* If it was unused, mark it used now. */ + pirq_inuse_word(s, pirq) |=3D pirq_inuse_bit(pirq); + } + /* Set the mapping in both directions. */ + s->pirq[pirq].gsi =3D gsi; + s->gsi_pirq[gsi] =3D pirq; + } + + trace_kvm_xen_map_pirq(pirq, gsi); + return 0; } =20 int xen_physdev_unmap_pirq(struct physdev_unmap_pirq *unmap) { - return -ENOTSUP; + XenEvtchnState *s =3D xen_evtchn_singleton; + int pirq =3D unmap->pirq; + int gsi; + + if (!s) { + return -ENOTSUP; + } + + if (unmap->domid !=3D DOMID_SELF && unmap->domid !=3D xen_domid) + return -EPERM; + if (pirq < 0 || pirq >=3D MAX_XEN_PIRQ) + return -EINVAL; + + QEMU_LOCK_GUARD(&s->port_lock); + + if (!pirq_inuse(s, pirq)) { + return -ENOENT; + } + + gsi =3D s->pirq[pirq].gsi; + + /* We can only unmap GSI PIRQs */ + if (gsi < 0) { + return -EINVAL; + } + + s->gsi_pirq[gsi] =3D 0; + s->pirq[pirq].gsi =3D IRQ_UNBOUND; /* Doesn't actually matter because:= */ + pirq_inuse_word(s, pirq) &=3D ~pirq_inuse_bit(pirq); + + trace_kvm_xen_unmap_pirq(pirq, gsi); + return 0; } =20 int xen_physdev_eoi_pirq(struct physdev_eoi *eoi) { - return -ENOTSUP; + XenEvtchnState *s =3D xen_evtchn_singleton; + int pirq =3D eoi->irq; + int gsi; + + if (!s) { + return -ENOTSUP; + } + + QEMU_LOCK_GUARD(&s->port_lock); + + if (!pirq_inuse(s, pirq)) { + return -ENOENT; + } + + gsi =3D s->pirq[pirq].gsi; + if (gsi < 0) { + return -EINVAL; + } + + // XX: Reassert a level IRQ if needed */ + return 0; } =20 int xen_physdev_query_pirq(struct physdev_irq_status_query *query) { - return -ENOTSUP; + XenEvtchnState *s =3D xen_evtchn_singleton; + int pirq =3D query->irq; + + if (!s) { + return -ENOTSUP; + } + + QEMU_LOCK_GUARD(&s->port_lock); + + if (!pirq_inuse(s, pirq)) { + return -ENOENT; + } + + if (s->pirq[pirq].gsi >=3D 0) { + query->flags =3D XENIRQSTAT_needs_eoi; + } else { + query->flags =3D 0; + } + + return 0; } =20 int xen_physdev_get_free_pirq(struct physdev_get_free_pirq *get) { - return -ENOTSUP; + XenEvtchnState *s =3D xen_evtchn_singleton; + int pirq; + + if (!s) { + return -ENOTSUP; + } + + QEMU_LOCK_GUARD(&s->port_lock); + + pirq =3D allocate_pirq(s, get->type, IRQ_UNBOUND); + if (pirq < 0) { + return pirq; + } + + get->pirq =3D pirq; + trace_kvm_xen_get_free_pirq(pirq, get->type); + return 0; } =20 struct xenevtchn_handle *xen_be_evtchn_open(void) diff --git a/hw/i386/kvm/xen_evtchn.h b/hw/i386/kvm/xen_evtchn.h index ccf58aa796..2c12506cc2 100644 --- a/hw/i386/kvm/xen_evtchn.h +++ b/hw/i386/kvm/xen_evtchn.h @@ -48,6 +48,7 @@ struct evtchn_status; struct evtchn_close; struct evtchn_unmask; struct evtchn_bind_virq; +struct evtchn_bind_pirq; struct evtchn_bind_ipi; struct evtchn_send; struct evtchn_alloc_unbound; @@ -58,6 +59,7 @@ int xen_evtchn_status_op(struct evtchn_status *status); int xen_evtchn_close_op(struct evtchn_close *close); int xen_evtchn_unmask_op(struct evtchn_unmask *unmask); int xen_evtchn_bind_virq_op(struct evtchn_bind_virq *virq); +int xen_evtchn_bind_pirq_op(struct evtchn_bind_pirq *pirq); int xen_evtchn_bind_ipi_op(struct evtchn_bind_ipi *ipi); int xen_evtchn_send_op(struct evtchn_send *send); int xen_evtchn_alloc_unbound_op(struct evtchn_alloc_unbound *alloc); diff --git a/meson.build b/meson.build index 72eec9c68a..8a58c381eb 100644 --- a/meson.build +++ b/meson.build @@ -2943,6 +2943,7 @@ if have_system 'hw/i2c', 'hw/i386', 'hw/i386/xen', + 'hw/i386/kvm', 'hw/ide', 'hw/input', 'hw/intc', diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c index 3fa58e33bd..c956390e2c 100644 --- a/target/i386/kvm/xen-emu.c +++ b/target/i386/kvm/xen-emu.c @@ -1215,6 +1215,21 @@ static bool kvm_xen_hcall_evtchn_op(struct kvm_xen_e= xit *exit, X86CPU *cpu, } break; } + case EVTCHNOP_bind_pirq: { + struct evtchn_bind_pirq pirq; + + qemu_build_assert(sizeof(pirq) =3D=3D 12); + if (kvm_copy_from_gva(cs, arg, &pirq, sizeof(pirq))) { + err =3D -EFAULT; + break; + } + + err =3D xen_evtchn_bind_pirq_op(&pirq); + if (!err && kvm_copy_to_gva(cs, arg, &pirq, sizeof(pirq))) { + err =3D -EFAULT; + } + break; + } case EVTCHNOP_bind_ipi: { struct evtchn_bind_ipi ipi; =20 --=20 2.35.3