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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1031; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673668874932100003 igb implementation first starts off by copying e1000e code. Correct the code style before that. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/e1000.c | 41 ++++++++-------- hw/net/e1000e.c | 72 ++++++++++++++-------------- hw/net/e1000e_core.c | 103 ++++++++++++++++++++++------------------- hw/net/e1000e_core.h | 66 +++++++++++++------------- hw/net/e1000x_common.h | 44 +++++++++--------- 5 files changed, 168 insertions(+), 158 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 7efb8a4c52..8ee30aa37c 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -808,10 +808,11 @@ receive_filter(E1000State *s, const uint8_t *buf, int= size) if (e1000x_is_vlan_packet(buf, le16_to_cpu(s->mac_reg[VET])) && e1000x_vlan_rx_filter_enabled(s->mac_reg)) { uint16_t vid =3D lduw_be_p(buf + 14); - uint32_t vfta =3D ldl_le_p((uint32_t*)(s->mac_reg + VFTA) + + uint32_t vfta =3D ldl_le_p((uint32_t *)(s->mac_reg + VFTA) + ((vid >> 5) & 0x7f)); - if ((vfta & (1 << (vid & 0x1f))) =3D=3D 0) + if ((vfta & (1 << (vid & 0x1f))) =3D=3D 0) { return 0; + } } =20 if (!isbcast && !ismcast && (rctl & E1000_RCTL_UPE)) { /* promiscuous = ucast */ @@ -1220,16 +1221,16 @@ static const readops macreg_readops[] =3D { [TDFPC] =3D mac_low13_read, [AIT] =3D mac_low16_read, =20 - [CRCERRS ... MPC] =3D &mac_readreg, - [IP6AT ... IP6AT+3] =3D &mac_readreg, [IP4AT ... IP4AT+6] =3D &mac_= readreg, - [FFLT ... FFLT+6] =3D &mac_low11_read, - [RA ... RA+31] =3D &mac_readreg, - [WUPM ... WUPM+31] =3D &mac_readreg, - [MTA ... MTA+127] =3D &mac_readreg, - [VFTA ... VFTA+127] =3D &mac_readreg, - [FFMT ... FFMT+254] =3D &mac_low4_read, - [FFVT ... FFVT+254] =3D &mac_readreg, - [PBM ... PBM+16383] =3D &mac_readreg, + [CRCERRS ... MPC] =3D &mac_readreg, + [IP6AT ... IP6AT + 3] =3D &mac_readreg, [IP4AT ... IP4AT + 6] =3D &= mac_readreg, + [FFLT ... FFLT + 6] =3D &mac_low11_read, + [RA ... RA + 31] =3D &mac_readreg, + [WUPM ... WUPM + 31] =3D &mac_readreg, + [MTA ... MTA + 127] =3D &mac_readreg, + [VFTA ... VFTA + 127] =3D &mac_readreg, + [FFMT ... FFMT + 254] =3D &mac_low4_read, + [FFVT ... FFVT + 254] =3D &mac_readreg, + [PBM ... PBM + 16383] =3D &mac_readreg, }; enum { NREADOPS =3D ARRAY_SIZE(macreg_readops) }; =20 @@ -1252,14 +1253,14 @@ static const writeops macreg_writeops[] =3D { [RDTR] =3D set_16bit, [RADV] =3D set_16bit, [TADV] =3D set_1= 6bit, [ITR] =3D set_16bit, =20 - [IP6AT ... IP6AT+3] =3D &mac_writereg, [IP4AT ... IP4AT+6] =3D &mac_wr= itereg, - [FFLT ... FFLT+6] =3D &mac_writereg, - [RA ... RA+31] =3D &mac_writereg, - [WUPM ... WUPM+31] =3D &mac_writereg, - [MTA ... MTA+127] =3D &mac_writereg, - [VFTA ... VFTA+127] =3D &mac_writereg, - [FFMT ... FFMT+254] =3D &mac_writereg, [FFVT ... FFVT+254] =3D &mac_wr= itereg, - [PBM ... PBM+16383] =3D &mac_writereg, + [IP6AT ... IP6AT + 3] =3D &mac_writereg, [IP4AT ... IP4AT + 6] =3D &ma= c_writereg, + [FFLT ... FFLT + 6] =3D &mac_writereg, + [RA ... RA + 31] =3D &mac_writereg, + [WUPM ... WUPM + 31] =3D &mac_writereg, + [MTA ... MTA + 127] =3D &mac_writereg, + [VFTA ... VFTA + 127] =3D &mac_writereg, + [FFMT ... FFMT + 254] =3D &mac_writereg, [FFVT ... FFVT + 254] =3D &ma= c_writereg, + [PBM ... PBM + 16383] =3D &mac_writereg, }; =20 enum { NWRITEOPS =3D ARRAY_SIZE(macreg_writeops) }; diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 7523e9f5d2..8635ca16c6 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -1,37 +1,37 @@ /* -* QEMU INTEL 82574 GbE NIC emulation -* -* Software developer's manuals: -* http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-dat= asheet.pdf -* -* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) -* Developed by Daynix Computing LTD (http://www.daynix.com) -* -* Authors: -* Dmitry Fleytman -* Leonid Bloch -* Yan Vugenfirer -* -* Based on work done by: -* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. -* Copyright (c) 2008 Qumranet -* Based on work done by: -* Copyright (c) 2007 Dan Aloni -* Copyright (c) 2004 Antony T Curtis -* -* This library is free software; you can redistribute it and/or -* modify it under the terms of the GNU Lesser General Public -* License as published by the Free Software Foundation; either -* version 2.1 of the License, or (at your option) any later version. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -* Lesser General Public License for more details. -* -* You should have received a copy of the GNU Lesser General Public -* License along with this library; if not, see . -*/ + * QEMU INTEL 82574 GbE NIC emulation + * + * Software developer's manuals: + * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-da= tasheet.pdf + * + * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) + * Developed by Daynix Computing LTD (http://www.daynix.com) + * + * Authors: + * Dmitry Fleytman + * Leonid Bloch + * Yan Vugenfirer + * + * Based on work done by: + * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. + * Copyright (c) 2008 Qumranet + * Based on work done by: + * Copyright (c) 2007 Dan Aloni + * Copyright (c) 2004 Antony T Curtis + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ =20 #include "qemu/osdep.h" #include "qemu/units.h" @@ -239,9 +239,9 @@ static NetClientInfo net_e1000e_info =3D { }; =20 /* -* EEPROM (NVM) contents documented in Table 36, section 6.1 -* and generally 6.1.2 Software accessed words. -*/ + * EEPROM (NVM) contents documented in Table 36, section 6.1 + * and generally 6.1.2 Software accessed words. + */ static const uint16_t e1000e_eeprom_template[64] =3D { /* Address | Compat. | ImVer | Compat. */ 0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff, diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index fc9cdb4528..c4be782558 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -1,37 +1,37 @@ /* -* Core code for QEMU e1000e emulation -* -* Software developer's manuals: -* http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-dat= asheet.pdf -* -* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) -* Developed by Daynix Computing LTD (http://www.daynix.com) -* -* Authors: -* Dmitry Fleytman -* Leonid Bloch -* Yan Vugenfirer -* -* Based on work done by: -* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. -* Copyright (c) 2008 Qumranet -* Based on work done by: -* Copyright (c) 2007 Dan Aloni -* Copyright (c) 2004 Antony T Curtis -* -* This library is free software; you can redistribute it and/or -* modify it under the terms of the GNU Lesser General Public -* License as published by the Free Software Foundation; either -* version 2.1 of the License, or (at your option) any later version. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -* Lesser General Public License for more details. -* -* You should have received a copy of the GNU Lesser General Public -* License along with this library; if not, see . -*/ + * Core code for QEMU e1000e emulation + * + * Software developer's manuals: + * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-da= tasheet.pdf + * + * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) + * Developed by Daynix Computing LTD (http://www.daynix.com) + * + * Authors: + * Dmitry Fleytman + * Leonid Bloch + * Yan Vugenfirer + * + * Based on work done by: + * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. + * Copyright (c) 2008 Qumranet + * Based on work done by: + * Copyright (c) 2007 Dan Aloni + * Copyright (c) 2004 Antony T Curtis + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ =20 #include "qemu/osdep.h" #include "qemu/log.h" @@ -49,8 +49,9 @@ =20 #include "trace.h" =20 -#define E1000E_MIN_XITR (500) /* No more then 7813 interrupts per - second according to spec 10.2.4.2 */ +/* No more then 7813 interrupts per second according to spec 10.2.4.2 */ +#define E1000E_MIN_XITR (500) + #define E1000E_MAX_TX_FRAGS (64) =20 static inline void @@ -282,14 +283,18 @@ e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint= 32_t *causes) core->delayed_causes |=3D *causes & delayable_causes; *causes &=3D ~delayable_causes; =20 - /* Check if delayed RX interrupts disabled by client - or if there are causes that cannot be delayed */ + /* + * Check if delayed RX interrupts disabled by client + * or if there are causes that cannot be delayed + */ if ((rdtr =3D=3D 0) || (*causes !=3D 0)) { return false; } =20 - /* Check if delayed RX ACK interrupts disabled by client - and there is an ACK packet received */ + /* + * Check if delayed RX ACK interrupts disabled by client + * and there is an ACK packet received + */ if ((raid =3D=3D 0) && (core->delayed_causes & E1000_ICR_ACK)) { return false; } @@ -2515,7 +2520,8 @@ e1000e_set_icr(E1000ECore *core, int index, uint32_t = val) } =20 icr =3D core->mac[ICR] & ~val; - /* Windows driver expects that the "receive overrun" bit and other + /* + * Windows driver expects that the "receive overrun" bit and other * ones to be cleared when the "Other" bit (#24) is cleared. */ icr =3D (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : ic= r; @@ -3269,10 +3275,12 @@ enum { E1000E_NWRITEOPS =3D ARRAY_SIZE(e1000e_macre= g_writeops) }; =20 enum { MAC_ACCESS_PARTIAL =3D 1 }; =20 -/* The array below combines alias offsets of the index values for the +/* + * The array below combines alias offsets of the index values for the * MAC registers that have aliases, with the indication of not fully * implemented registers (lowest bit). This combination is possible - * because all of the offsets are even. */ + * because all of the offsets are even. + */ static const uint16_t mac_reg_access[E1000E_MAC_SIZE] =3D { /* Alias index offsets */ [FCRTL_A] =3D 0x07fe, [FCRTH_A] =3D 0x0802, @@ -3536,10 +3544,10 @@ void e1000e_core_pre_save(E1000ECore *core) NetClientState *nc =3D qemu_get_queue(core->owner_nic); =20 /* - * If link is down and auto-negotiation is supported and ongoing, - * complete auto-negotiation immediately. This allows us to look - * at MII_SR_AUTONEG_COMPLETE to infer link status on load. - */ + * If link is down and auto-negotiation is supported and ongoing, + * complete auto-negotiation immediately. This allows us to look + * at MII_SR_AUTONEG_COMPLETE to infer link status on load. + */ if (nc->link_down && e1000e_have_autoneg(core)) { core->phy[0][PHY_STATUS] |=3D MII_SR_AUTONEG_COMPLETE; e1000e_update_flowctl_status(core); @@ -3557,7 +3565,8 @@ e1000e_core_post_load(E1000ECore *core) { NetClientState *nc =3D qemu_get_queue(core->owner_nic); =20 - /* nc.link_down can't be migrated, so infer link_down according + /* + * nc.link_down can't be migrated, so infer link_down according * to link status bit in core.mac[STATUS]. */ nc->link_down =3D (core->mac[STATUS] & E1000_STATUS_LU) =3D=3D 0; diff --git a/hw/net/e1000e_core.h b/hw/net/e1000e_core.h index 4ddb4d2c39..b8f38c47a0 100644 --- a/hw/net/e1000e_core.h +++ b/hw/net/e1000e_core.h @@ -1,37 +1,37 @@ /* -* Core code for QEMU e1000e emulation -* -* Software developer's manuals: -* http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-dat= asheet.pdf -* -* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) -* Developed by Daynix Computing LTD (http://www.daynix.com) -* -* Authors: -* Dmitry Fleytman -* Leonid Bloch -* Yan Vugenfirer -* -* Based on work done by: -* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. -* Copyright (c) 2008 Qumranet -* Based on work done by: -* Copyright (c) 2007 Dan Aloni -* Copyright (c) 2004 Antony T Curtis -* -* This library is free software; you can redistribute it and/or -* modify it under the terms of the GNU Lesser General Public -* License as published by the Free Software Foundation; either -* version 2.1 of the License, or (at your option) any later version. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -* Lesser General Public License for more details. -* -* You should have received a copy of the GNU Lesser General Public -* License along with this library; if not, see . -*/ + * Core code for QEMU e1000e emulation + * + * Software developer's manuals: + * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-da= tasheet.pdf + * + * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) + * Developed by Daynix Computing LTD (http://www.daynix.com) + * + * Authors: + * Dmitry Fleytman + * Leonid Bloch + * Yan Vugenfirer + * + * Based on work done by: + * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. + * Copyright (c) 2008 Qumranet + * Based on work done by: + * Copyright (c) 2007 Dan Aloni + * Copyright (c) 2004 Antony T Curtis + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ =20 #ifndef HW_NET_E1000E_CORE_H #define HW_NET_E1000E_CORE_H diff --git a/hw/net/e1000x_common.h b/hw/net/e1000x_common.h index b7742775c4..bc1ee75b04 100644 --- a/hw/net/e1000x_common.h +++ b/hw/net/e1000x_common.h @@ -1,26 +1,26 @@ /* -* QEMU e1000(e) emulation - shared code -* -* Copyright (c) 2008 Qumranet -* -* Based on work done by: -* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. -* Copyright (c) 2007 Dan Aloni -* Copyright (c) 2004 Antony T Curtis -* -* This library is free software; you can redistribute it and/or -* modify it under the terms of the GNU Lesser General Public -* License as published by the Free Software Foundation; either -* version 2.1 of the License, or (at your option) any later version. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -* Lesser General Public License for more details. -* -* You should have received a copy of the GNU Lesser General Public -* License along with this library; if not, see . -*/ + * QEMU e1000(e) emulation - shared code + * + * Copyright (c) 2008 Qumranet + * + * Based on work done by: + * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. + * Copyright (c) 2007 Dan Aloni + * Copyright (c) 2004 Antony T Curtis + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ =20 #ifndef HW_NET_E1000X_COMMON_H #define HW_NET_E1000X_COMMON_H --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673668872; cv=none; d=zohomail.com; s=zohoarc; b=bFZqXRfQWCbHfvoe/7ZFmMTk21LFdBD0yjU4IicJBk4RVUR4eXDsu/65LSX2o95DVBRG+aM/BwjT0UXLDHCXOKkMmteDFRhnnWcXj3K6fkY6sCMjFFRoE8l7z6RkKl93JjW3fj7y6jxKqdzjj1/rqng9DJ2mOcO8ztK2IGwhLHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673668872; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::631; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673668874787100001 Content-Type: text/plain; charset="utf-8" The definitions will be used by igb. Signed-off-by: Akihiko Odaki --- include/hw/net/mii.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h index 4ae4dcce7e..c6a767a49a 100644 --- a/include/hw/net/mii.h +++ b/include/hw/net/mii.h @@ -81,20 +81,31 @@ #define MII_ANLPAR_ACK (1 << 14) #define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */ #define MII_ANLPAR_PAUSE (1 << 10) /* can pause */ +#define MII_ANLPAR_T4 (1 << 9) #define MII_ANLPAR_TXFD (1 << 8) #define MII_ANLPAR_TX (1 << 7) #define MII_ANLPAR_10FD (1 << 6) #define MII_ANLPAR_10 (1 << 5) #define MII_ANLPAR_CSMACD (1 << 0) =20 -#define MII_ANER_NWAY (1 << 0) /* Can do N-way auto-nego */ +#define MII_ANER_NP (1 << 2) /* Next Page Able */ +#define MII_ANER_NWAY (1 << 0) /* Can do N-way auto-nego */ =20 +#define MII_ANNP_MP (1 << 13) /* Message Page */ + +#define MII_CTRL1000_MASTER (1 << 11) /* MASTER-SLAVE Manual Configuration= Value */ +#define MII_CTRL1000_PORT (1 << 10) /* T2_Repeater/DTE bit */ #define MII_CTRL1000_FULL (1 << 9) /* 1000BASE-T full duplex */ #define MII_CTRL1000_HALF (1 << 8) /* 1000BASE-T half duplex */ =20 +#define MII_STAT1000_LOK (1 << 13) /* Local Receiver Status */ +#define MII_STAT1000_ROK (1 << 12) /* Remote Receiver Status */ #define MII_STAT1000_FULL (1 << 11) /* 1000BASE-T full duplex */ #define MII_STAT1000_HALF (1 << 10) /* 1000BASE-T half duplex */ =20 +#define MII_EXTSTAT_1000T_FD (1 << 13) /* 1000BASE-T Full Duplex */ +#define MII_EXTSTAT_1000T_HD (1 << 12) /* 1000BASE-T Half Duplex */ + /* List of vendor identifiers */ /* RealTek 8201 */ #define RTL8201CP_PHYID1 0x0000 --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 13 Jan 2023 19:59:59 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 03/19] fsl_etsec: Use hw/net/mii.h Date: Sat, 14 Jan 2023 12:59:03 +0900 Message-Id: <20230114035919.35251-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1032; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669029361100001 hw/net/mii.h provides common definitions for MII. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/fsl_etsec/etsec.c | 11 ++++++----- hw/net/fsl_etsec/etsec.h | 17 ----------------- hw/net/fsl_etsec/miim.c | 5 +++-- include/hw/net/mii.h | 1 + 4 files changed, 10 insertions(+), 24 deletions(-) diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index b75d8e3dce..b008dbb274 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -29,6 +29,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/irq.h" +#include "hw/net/mii.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" #include "etsec.h" @@ -339,11 +340,11 @@ static void etsec_reset(DeviceState *d) etsec->rx_buffer_len =3D 0; =20 etsec->phy_status =3D - MII_SR_EXTENDED_CAPS | MII_SR_LINK_STATUS | MII_SR_AUTONEG_CA= PS | - MII_SR_AUTONEG_COMPLETE | MII_SR_PREAMBLE_SUPPRESS | - MII_SR_EXTENDED_STATUS | MII_SR_100T2_HD_CAPS | MII_SR_100T2_FD_C= APS | - MII_SR_10T_HD_CAPS | MII_SR_10T_FD_CAPS | MII_SR_100X_HD_CA= PS | - MII_SR_100X_FD_CAPS | MII_SR_100T4_CAPS; + MII_BMSR_EXTCAP | MII_BMSR_LINK_ST | MII_BMSR_AUTONEG | + MII_BMSR_AN_COMP | MII_BMSR_MFPS | MII_BMSR_EXTSTAT | + MII_BMSR_100T2_HD | MII_BMSR_100T2_FD | + MII_BMSR_10T_HD | MII_BMSR_10T_FD | + MII_BMSR_100TX_HD | MII_BMSR_100TX_FD | MII_BMSR_100T4; =20 etsec_update_irq(etsec); } diff --git a/hw/net/fsl_etsec/etsec.h b/hw/net/fsl_etsec/etsec.h index 3c625c955c..3860864a3f 100644 --- a/hw/net/fsl_etsec/etsec.h +++ b/hw/net/fsl_etsec/etsec.h @@ -76,23 +76,6 @@ typedef struct eTSEC_rxtx_bd { #define FCB_TX_CTU (1 << 1) #define FCB_TX_NPH (1 << 0) =20 -/* PHY Status Register */ -#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabiliti= es */ -#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ -#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 =3D link */ -#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ -#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ -#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ -#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ -#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F= */ -#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ -#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ -#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ -#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ -#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ -#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ -#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ - /* eTSEC */ =20 /* Number of register in the device */ diff --git a/hw/net/fsl_etsec/miim.c b/hw/net/fsl_etsec/miim.c index 6bba01c82a..b48d2cb57b 100644 --- a/hw/net/fsl_etsec/miim.c +++ b/hw/net/fsl_etsec/miim.c @@ -23,6 +23,7 @@ */ =20 #include "qemu/osdep.h" +#include "hw/net/mii.h" #include "etsec.h" #include "registers.h" =20 @@ -140,8 +141,8 @@ void etsec_miim_link_status(eTSEC *etsec, NetClientStat= e *nc) { /* Set link status */ if (nc->link_down) { - etsec->phy_status &=3D ~MII_SR_LINK_STATUS; + etsec->phy_status &=3D ~MII_BMSR_LINK_ST; } else { - etsec->phy_status |=3D MII_SR_LINK_STATUS; + etsec->phy_status |=3D MII_BMSR_LINK_ST; } } diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h index c6a767a49a..ed1bb52b0f 100644 --- a/include/hw/net/mii.h +++ b/include/hw/net/mii.h @@ -55,6 +55,7 @@ #define MII_BMCR_CTST (1 << 7) /* Collision test */ #define MII_BMCR_SPEED1000 (1 << 6) /* MSB of Speed (1000) */ =20 +#define MII_BMSR_100T4 (1 << 15) /* Can do 100mbps T4 */ #define MII_BMSR_100TX_FD (1 << 14) /* Can do 100mbps, full-duplex */ #define MII_BMSR_100TX_HD (1 << 13) /* Can do 100mbps, half-duplex */ #define MII_BMSR_10T_FD (1 << 12) /* Can do 10mbps, full-duplex */ --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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Fri, 13 Jan 2023 20:00:01 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 04/19] e1000: Use hw/net/mii.h Date: Sat, 14 Jan 2023 12:59:04 +0900 Message-Id: <20230114035919.35251-5-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::632; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669139906100001 hw/net/mii.h provides common definitions for MII. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/e1000.c | 86 ++++++++++++++++++------------------ hw/net/e1000_regs.h | 46 -------------------- hw/net/e1000e.c | 1 + hw/net/e1000e_core.c | 99 +++++++++++++++++++++--------------------- hw/net/e1000x_common.c | 5 ++- hw/net/e1000x_common.h | 8 ++-- 6 files changed, 101 insertions(+), 144 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 8ee30aa37c..9619a2e481 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -26,6 +26,7 @@ =20 =20 #include "qemu/osdep.h" +#include "hw/net/mii.h" #include "hw/pci/pci_device.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -181,67 +182,67 @@ e1000_autoneg_done(E1000State *s) static bool have_autoneg(E1000State *s) { - return chkflag(AUTONEG) && (s->phy_reg[PHY_CTRL] & MII_CR_AUTO_NEG_EN); + return chkflag(AUTONEG) && (s->phy_reg[MII_BMCR] & MII_BMCR_AUTOEN); } =20 static void set_phy_ctrl(E1000State *s, int index, uint16_t val) { - /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearin= g */ - s->phy_reg[PHY_CTRL] =3D val & ~(0x3f | - MII_CR_RESET | - MII_CR_RESTART_AUTO_NEG); + /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ + s->phy_reg[MII_BMCR] =3D val & ~(0x3f | + MII_BMCR_RESET | + MII_BMCR_ANRESTART); =20 /* * QEMU 1.3 does not support link auto-negotiation emulation, so if we * migrate during auto negotiation, after migration the link will be * down. */ - if (have_autoneg(s) && (val & MII_CR_RESTART_AUTO_NEG)) { + if (have_autoneg(s) && (val & MII_BMCR_ANRESTART)) { e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer); } } =20 static void (*phyreg_writeops[])(E1000State *, int, uint16_t) =3D { - [PHY_CTRL] =3D set_phy_ctrl, + [MII_BMCR] =3D set_phy_ctrl, }; =20 enum { NPHYWRITEOPS =3D ARRAY_SIZE(phyreg_writeops) }; =20 enum { PHY_R =3D 1, PHY_W =3D 2, PHY_RW =3D PHY_R | PHY_W }; static const char phy_regcap[0x20] =3D { - [PHY_STATUS] =3D PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] =3D PHY_= RW, - [PHY_ID1] =3D PHY_R, [M88E1000_PHY_SPEC_CTRL] =3D PHY_= RW, - [PHY_CTRL] =3D PHY_RW, [PHY_1000T_CTRL] =3D PHY_= RW, - [PHY_LP_ABILITY] =3D PHY_R, [PHY_1000T_STATUS] =3D PHY_= R, - [PHY_AUTONEG_ADV] =3D PHY_RW, [M88E1000_RX_ERR_CNTR] =3D PHY_= R, - [PHY_ID2] =3D PHY_R, [M88E1000_PHY_SPEC_STATUS] =3D PHY_= R, - [PHY_AUTONEG_EXP] =3D PHY_R, + [MII_BMSR] =3D PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] =3D PHY_RW, + [MII_PHYID1] =3D PHY_R, [M88E1000_PHY_SPEC_CTRL] =3D PHY_RW, + [MII_BMCR] =3D PHY_RW, [MII_CTRL1000] =3D PHY_RW, + [MII_ANLPAR] =3D PHY_R, [MII_STAT1000] =3D PHY_R, + [MII_ANAR] =3D PHY_RW, [M88E1000_RX_ERR_CNTR] =3D PHY_R, + [MII_PHYID2] =3D PHY_R, [M88E1000_PHY_SPEC_STATUS] =3D PHY_R, + [MII_ANER] =3D PHY_R, }; =20 -/* PHY_ID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */ +/* MII_PHYID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */ static const uint16_t phy_reg_init[] =3D { - [PHY_CTRL] =3D MII_CR_SPEED_SELECT_MSB | - MII_CR_FULL_DUPLEX | - MII_CR_AUTO_NEG_EN, - - [PHY_STATUS] =3D MII_SR_EXTENDED_CAPS | - MII_SR_LINK_STATUS | /* link initially up */ - MII_SR_AUTONEG_CAPS | - /* MII_SR_AUTONEG_COMPLETE: initially NOT completed */ - MII_SR_PREAMBLE_SUPPRESS | - MII_SR_EXTENDED_STATUS | - MII_SR_10T_HD_CAPS | - MII_SR_10T_FD_CAPS | - MII_SR_100X_HD_CAPS | - MII_SR_100X_FD_CAPS, - - [PHY_ID1] =3D 0x141, - /* [PHY_ID2] configured per DevId, from e1000_reset() */ - [PHY_AUTONEG_ADV] =3D 0xde1, - [PHY_LP_ABILITY] =3D 0x1e0, - [PHY_1000T_CTRL] =3D 0x0e00, - [PHY_1000T_STATUS] =3D 0x3c00, + [MII_BMCR] =3D MII_BMCR_SPEED1000 | + MII_BMCR_FD | + MII_BMCR_AUTOEN, + + [MII_BMSR] =3D MII_BMSR_EXTCAP | + MII_BMSR_LINK_ST | /* link initially up */ + MII_BMSR_AUTONEG | + /* MII_BMSR_AN_COMP: initially NOT completed */ + MII_BMSR_MFPS | + MII_BMSR_EXTSTAT | + MII_BMSR_10T_HD | + MII_BMSR_10T_FD | + MII_BMSR_100TX_HD | + MII_BMSR_100TX_FD, + + [MII_PHYID1] =3D 0x141, + /* [MII_PHYID2] configured per DevId, from e1000_reset() */ + [MII_ANAR] =3D 0xde1, + [MII_ANLPAR] =3D 0x1e0, + [MII_CTRL1000] =3D 0x0e00, + [MII_STAT1000] =3D 0x3c00, [M88E1000_PHY_SPEC_CTRL] =3D 0x360, [M88E1000_PHY_SPEC_STATUS] =3D 0xac00, [M88E1000_EXT_PHY_SPEC_CTRL] =3D 0x0d60, @@ -387,7 +388,7 @@ static void e1000_reset(void *opaque) d->mit_ide =3D 0; memset(d->phy_reg, 0, sizeof d->phy_reg); memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init); - d->phy_reg[PHY_ID2] =3D edc->phy_id2; + d->phy_reg[MII_PHYID2] =3D edc->phy_id2; memset(d->mac_reg, 0, sizeof d->mac_reg); memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init); d->rxbuf_min_shift =3D 1; @@ -561,7 +562,7 @@ e1000_send_packet(E1000State *s, const uint8_t *buf, in= t size) PTC1023, PTC1522 }; =20 NetClientState *nc =3D qemu_get_queue(s->nic); - if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) { + if (s->phy_reg[MII_BMCR] & MII_BMCR_LOOPBACK) { qemu_receive_packet(nc, buf, size); } else { qemu_send_packet(nc, buf, size); @@ -842,7 +843,7 @@ e1000_set_link_status(NetClientState *nc) e1000x_update_regs_on_link_down(s->mac_reg, s->phy_reg); } else { if (have_autoneg(s) && - !(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { + !(s->phy_reg[MII_BMSR] & MII_BMSR_AN_COMP)) { e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_time= r); } else { e1000_link_up(s); @@ -1416,10 +1417,10 @@ static int e1000_pre_save(void *opaque) /* * If link is down and auto-negotiation is supported and ongoing, * complete auto-negotiation immediately. This allows us to look - * at MII_SR_AUTONEG_COMPLETE to infer link status on load. + * at MII_BMSR_AN_COMP to infer link status on load. */ if (nc->link_down && have_autoneg(s)) { - s->phy_reg[PHY_STATUS] |=3D MII_SR_AUTONEG_COMPLETE; + s->phy_reg[MII_BMSR] |=3D MII_BMSR_AN_COMP; } =20 /* Decide which set of props to migrate in the main structure */ @@ -1458,8 +1459,7 @@ static int e1000_post_load(void *opaque, int version_= id) * Alternatively, restart link negotiation if it was in progress. */ nc->link_down =3D (s->mac_reg[STATUS] & E1000_STATUS_LU) =3D=3D 0; =20 - if (have_autoneg(s) && - !(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { + if (have_autoneg(s) && !(s->phy_reg[MII_BMSR] & MII_BMSR_AN_COMP)) { nc->link_down =3D false; timer_mod(s->autoneg_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h index 59e050742b..59d6eb3189 100644 --- a/hw/net/e1000_regs.h +++ b/hw/net/e1000_regs.h @@ -474,20 +474,6 @@ #define E1000_TARC_ENABLE BIT(10) =20 /* PHY 1000 MII Register/Bit Definitions */ -/* PHY Registers defined by IEEE */ -#define PHY_CTRL 0x00 /* Control Register */ -#define PHY_STATUS 0x01 /* Status Regiser */ -#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ -#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ -#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ -#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ -#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ -#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ -#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ -#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ -#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ -#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ - /* 82574-specific registers */ #define PHY_COPPER_CTRL1 0x10 /* Copper Specific Control Register 1 */ #define PHY_COPPER_STAT1 0x11 /* Copper Specific Status Register 1 */ @@ -539,38 +525,6 @@ #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ =20 -/* PHY Control Register */ -#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=3D1000, 01=3D100, = 00=3D10 */ -#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ -#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =3D1, half duplex =3D0 */ -#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ -#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ -#define MII_CR_POWER_DOWN 0x0800 /* Power down */ -#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ -#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=3D1000, 01=3D100, = 00=3D10 */ -#define MII_CR_LOOPBACK 0x4000 /* 0 =3D normal, 1 =3D loopback */ -#define MII_CR_RESET 0x8000 /* 0 =3D normal, 1 =3D PHY reset */ - -/* PHY Status Register */ -#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabiliti= es */ -#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ -#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 =3D link */ -#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ -#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ -#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ -#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ -#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F= */ -#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ -#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ -#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ -#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ -#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ -#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ -#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ - -/* PHY Link Partner Ability Register */ -#define MII_LPAR_LPACK 0x4000 /* Acked by link partner */ - /* Interrupt Cause Read */ #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 8635ca16c6..d591d01c07 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -42,6 +42,7 @@ #include "qemu/range.h" #include "sysemu/sysemu.h" #include "hw/hw.h" +#include "hw/net/mii.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/qdev-properties.h" diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index c4be782558..181c1e0c2a 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -37,6 +37,7 @@ #include "qemu/log.h" #include "net/net.h" #include "net/tap.h" +#include "hw/net/mii.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "sysemu/runstate.h" @@ -659,7 +660,7 @@ e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *= tx, int queue_index) =20 net_tx_pkt_dump(tx->tx_pkt); =20 - if ((core->phy[0][PHY_CTRL] & MII_CR_LOOPBACK) || + if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) =3D=3D E1000_RCTL_LBM_MAC)= ) { return net_tx_pkt_send_loopback(tx->tx_pkt, queue); } else { @@ -1797,13 +1798,13 @@ e1000e_receive_iov(E1000ECore *core, const struct i= ovec *iov, int iovcnt) static inline bool e1000e_have_autoneg(E1000ECore *core) { - return core->phy[0][PHY_CTRL] & MII_CR_AUTO_NEG_EN; + return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; } =20 static void e1000e_update_flowctl_status(E1000ECore *core) { if (e1000e_have_autoneg(core) && - core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE) { + core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { trace_e1000e_link_autoneg_flowctl(true); core->mac[CTRL] |=3D E1000_CTRL_TFCE | E1000_CTRL_RFCE; } else { @@ -1821,12 +1822,12 @@ e1000e_link_down(E1000ECore *core) static inline void e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) { - /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearin= g */ - core->phy[0][PHY_CTRL] =3D val & ~(0x3f | - MII_CR_RESET | - MII_CR_RESTART_AUTO_NEG); + /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ + core->phy[0][MII_BMCR] =3D val & ~(0x3f | + MII_BMCR_RESET | + MII_BMCR_ANRESTART); =20 - if ((val & MII_CR_RESTART_AUTO_NEG) && + if ((val & MII_BMCR_ANRESTART) && e1000e_have_autoneg(core)) { e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_time= r); } @@ -1860,7 +1861,7 @@ e1000e_core_set_link_status(E1000ECore *core) e1000x_update_regs_on_link_down(core->mac, core->phy[0]); } else { if (e1000e_have_autoneg(core) && - !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { + !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); } else { @@ -2002,7 +2003,7 @@ static void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) (E1000ECore *, int, uint16_t) =3D { [0] =3D { - [PHY_CTRL] =3D e1000e_set_phy_ctrl, + [MII_BMCR] =3D e1000e_set_phy_ctrl, [PHY_PAGE] =3D e1000e_set_phy_page, [PHY_OEM_BITS] =3D e1000e_set_phy_oem_bits } @@ -2274,19 +2275,19 @@ e1000e_get_reg_index_with_offset(const uint16_t *ma= c_reg_access, hwaddr addr) =20 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] =3D { [0] =3D { - [PHY_CTRL] =3D PHY_ANYPAGE | PHY_RW, - [PHY_STATUS] =3D PHY_ANYPAGE | PHY_R, - [PHY_ID1] =3D PHY_ANYPAGE | PHY_R, - [PHY_ID2] =3D PHY_ANYPAGE | PHY_R, - [PHY_AUTONEG_ADV] =3D PHY_ANYPAGE | PHY_RW, - [PHY_LP_ABILITY] =3D PHY_ANYPAGE | PHY_R, - [PHY_AUTONEG_EXP] =3D PHY_ANYPAGE | PHY_R, - [PHY_NEXT_PAGE_TX] =3D PHY_ANYPAGE | PHY_RW, - [PHY_LP_NEXT_PAGE] =3D PHY_ANYPAGE | PHY_R, - [PHY_1000T_CTRL] =3D PHY_ANYPAGE | PHY_RW, - [PHY_1000T_STATUS] =3D PHY_ANYPAGE | PHY_R, - [PHY_EXT_STATUS] =3D PHY_ANYPAGE | PHY_R, - [PHY_PAGE] =3D PHY_ANYPAGE | PHY_RW, + [MII_BMCR] =3D PHY_ANYPAGE | PHY_RW, + [MII_BMSR] =3D PHY_ANYPAGE | PHY_R, + [MII_PHYID1] =3D PHY_ANYPAGE | PHY_R, + [MII_PHYID2] =3D PHY_ANYPAGE | PHY_R, + [MII_ANAR] =3D PHY_ANYPAGE | PHY_RW, + [MII_ANLPAR] =3D PHY_ANYPAGE | PHY_R, + [MII_ANER] =3D PHY_ANYPAGE | PHY_R, + [MII_ANNP] =3D PHY_ANYPAGE | PHY_RW, + [MII_ANLPRNP] =3D PHY_ANYPAGE | PHY_R, + [MII_CTRL1000] =3D PHY_ANYPAGE | PHY_RW, + [MII_STAT1000] =3D PHY_ANYPAGE | PHY_R, + [MII_EXTSTAT] =3D PHY_ANYPAGE | PHY_R, + [PHY_PAGE] =3D PHY_ANYPAGE | PHY_RW, =20 [PHY_COPPER_CTRL1] =3D PHY_RW, [PHY_COPPER_STAT1] =3D PHY_R, @@ -3355,7 +3356,7 @@ static void e1000e_autoneg_resume(E1000ECore *core) { if (e1000e_have_autoneg(core) && - !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { + !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { qemu_get_queue(core->owner_nic)->link_down =3D false; timer_mod(core->autoneg_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); @@ -3430,29 +3431,29 @@ e1000e_core_pci_uninit(E1000ECore *core) static const uint16_t e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] =3D { [0] =3D { - [PHY_CTRL] =3D MII_CR_SPEED_SELECT_MSB | - MII_CR_FULL_DUPLEX | - MII_CR_AUTO_NEG_EN, - - [PHY_STATUS] =3D MII_SR_EXTENDED_CAPS | - MII_SR_LINK_STATUS | - MII_SR_AUTONEG_CAPS | - MII_SR_PREAMBLE_SUPPRESS | - MII_SR_EXTENDED_STATUS | - MII_SR_10T_HD_CAPS | - MII_SR_10T_FD_CAPS | - MII_SR_100X_HD_CAPS | - MII_SR_100X_FD_CAPS, - - [PHY_ID1] =3D 0x141, - [PHY_ID2] =3D E1000_PHY_ID2_82574x, - [PHY_AUTONEG_ADV] =3D 0xde1, - [PHY_LP_ABILITY] =3D 0x7e0, - [PHY_AUTONEG_EXP] =3D BIT(2), - [PHY_NEXT_PAGE_TX] =3D BIT(0) | BIT(13), - [PHY_1000T_CTRL] =3D BIT(8) | BIT(9) | BIT(10) | BIT(11), - [PHY_1000T_STATUS] =3D 0x3c00, - [PHY_EXT_STATUS] =3D BIT(12) | BIT(13), + [MII_BMCR] =3D MII_BMCR_SPEED1000 | + MII_BMCR_FD | + MII_BMCR_AUTOEN, + + [MII_BMSR] =3D MII_BMSR_EXTCAP | + MII_BMSR_LINK_ST | + MII_BMSR_AUTONEG | + MII_BMSR_MFPS | + MII_BMSR_EXTSTAT | + MII_BMSR_10T_HD | + MII_BMSR_10T_FD | + MII_BMSR_100TX_HD | + MII_BMSR_100TX_FD, + + [MII_PHYID1] =3D 0x141, + [MII_PHYID2] =3D E1000_PHY_ID2_82574x, + [MII_ANAR] =3D 0xde1, + [MII_ANLPAR] =3D 0x7e0, + [MII_ANER] =3D BIT(2), + [MII_ANNP] =3D BIT(0) | BIT(13), + [MII_CTRL1000] =3D BIT(8) | BIT(9) | BIT(10) | BIT(11), + [MII_STAT1000] =3D 0x3c00, + [MII_EXTSTAT] =3D BIT(12) | BIT(13), =20 [PHY_COPPER_CTRL1] =3D BIT(5) | BIT(6) | BIT(8) | BIT(9) | BIT(12) | BIT(13), @@ -3546,10 +3547,10 @@ void e1000e_core_pre_save(E1000ECore *core) /* * If link is down and auto-negotiation is supported and ongoing, * complete auto-negotiation immediately. This allows us to look - * at MII_SR_AUTONEG_COMPLETE to infer link status on load. + * at MII_BMSR_AN_COMP to infer link status on load. */ if (nc->link_down && e1000e_have_autoneg(core)) { - core->phy[0][PHY_STATUS] |=3D MII_SR_AUTONEG_COMPLETE; + core->phy[0][MII_BMSR] |=3D MII_BMSR_AN_COMP; e1000e_update_flowctl_status(core); } =20 diff --git a/hw/net/e1000x_common.c b/hw/net/e1000x_common.c index 2f43e8cd13..e79d4c79bd 100644 --- a/hw/net/e1000x_common.c +++ b/hw/net/e1000x_common.c @@ -24,6 +24,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "hw/net/mii.h" #include "hw/pci/pci_device.h" #include "net/net.h" =20 @@ -152,8 +153,8 @@ void e1000x_reset_mac_addr(NICState *nic, uint32_t *mac= _regs, void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy) { e1000x_update_regs_on_link_up(mac, phy); - phy[PHY_LP_ABILITY] |=3D MII_LPAR_LPACK; - phy[PHY_STATUS] |=3D MII_SR_AUTONEG_COMPLETE; + phy[MII_ANLPAR] |=3D MII_ANLPAR_ACK; + phy[MII_BMSR] |=3D MII_BMSR_AN_COMP; trace_e1000x_link_negotiation_done(); } =20 diff --git a/hw/net/e1000x_common.h b/hw/net/e1000x_common.h index bc1ee75b04..3501e4855a 100644 --- a/hw/net/e1000x_common.h +++ b/hw/net/e1000x_common.h @@ -152,16 +152,16 @@ static inline void e1000x_update_regs_on_link_down(uint32_t *mac, uint16_t *phy) { mac[STATUS] &=3D ~E1000_STATUS_LU; - phy[PHY_STATUS] &=3D ~MII_SR_LINK_STATUS; - phy[PHY_STATUS] &=3D ~MII_SR_AUTONEG_COMPLETE; - phy[PHY_LP_ABILITY] &=3D ~MII_LPAR_LPACK; + phy[MII_BMSR] &=3D ~MII_BMSR_LINK_ST; + phy[MII_BMSR] &=3D ~MII_BMSR_AN_COMP; + phy[MII_ANLPAR] &=3D ~MII_ANLPAR_ACK; } =20 static inline void e1000x_update_regs_on_link_up(uint32_t *mac, uint16_t *phy) { mac[STATUS] |=3D E1000_STATUS_LU; - phy[PHY_STATUS] |=3D MII_SR_LINK_STATUS; + phy[MII_BMSR] |=3D MII_BMSR_LINK_ST; } =20 void e1000x_update_rx_total_stats(uint32_t *mac, --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 13 Jan 2023 20:00:03 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki Subject: [PATCH 05/19] e1000: Mask registers when writing Date: Sat, 14 Jan 2023 12:59:05 +0900 Message-Id: <20230114035919.35251-6-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1035; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669595070100001 Content-Type: text/plain; charset="utf-8" When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000.c | 84 +++++++++++++++++++------------------------------- 1 file changed, 31 insertions(+), 53 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 9619a2e481..0925a99511 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -1062,30 +1062,6 @@ mac_readreg(E1000State *s, int index) return s->mac_reg[index]; } =20 -static uint32_t -mac_low4_read(E1000State *s, int index) -{ - return s->mac_reg[index] & 0xf; -} - -static uint32_t -mac_low11_read(E1000State *s, int index) -{ - return s->mac_reg[index] & 0x7ff; -} - -static uint32_t -mac_low13_read(E1000State *s, int index) -{ - return s->mac_reg[index] & 0x1fff; -} - -static uint32_t -mac_low16_read(E1000State *s, int index) -{ - return s->mac_reg[index] & 0xffff; -} - static uint32_t mac_icr_read(E1000State *s, int index) { @@ -1138,11 +1114,17 @@ set_rdt(E1000State *s, int index, uint32_t val) } } =20 -static void -set_16bit(E1000State *s, int index, uint32_t val) -{ - s->mac_reg[index] =3D val & 0xffff; -} +#define LOW_BITS_SET_FUNC(num) \ + static void \ + set_##num##bit(E1000State *s, int index, uint32_t val) \ + { \ + s->mac_reg[index] =3D val & (BIT(num) - 1); \ + } + +LOW_BITS_SET_FUNC(4) +LOW_BITS_SET_FUNC(11) +LOW_BITS_SET_FUNC(13) +LOW_BITS_SET_FUNC(16) =20 static void set_dlen(E1000State *s, int index, uint32_t val) @@ -1196,7 +1178,9 @@ static const readops macreg_readops[] =3D { getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC), getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC), getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), getreg(GORCL), - getreg(GOTCL), + getreg(GOTCL), getreg(RDFH), getreg(RDFT), getreg(RDFHS), + getreg(RDFTS), getreg(RDFPC), getreg(TDFH), getreg(TDFT), + getreg(TDFHS), getreg(TDFTS), getreg(TDFPC), getreg(AIT), =20 [TOTH] =3D mac_read_clr8, [TORH] =3D mac_read_clr8, [GOTCH] =3D mac_read_clr8, [GORCH] =3D mac_read_clr8, @@ -1214,22 +1198,15 @@ static const readops macreg_readops[] =3D { [MPTC] =3D mac_read_clr4, [ICR] =3D mac_icr_read, [EECD] =3D get_eecd, [EERD] =3D flash_eerd_read, - [RDFH] =3D mac_low13_read, [RDFT] =3D mac_low13_read, - [RDFHS] =3D mac_low13_read, [RDFTS] =3D mac_low13_read, - [RDFPC] =3D mac_low13_read, - [TDFH] =3D mac_low11_read, [TDFT] =3D mac_low11_read, - [TDFHS] =3D mac_low13_read, [TDFTS] =3D mac_low13_read, - [TDFPC] =3D mac_low13_read, - [AIT] =3D mac_low16_read, =20 [CRCERRS ... MPC] =3D &mac_readreg, [IP6AT ... IP6AT + 3] =3D &mac_readreg, [IP4AT ... IP4AT + 6] =3D &= mac_readreg, - [FFLT ... FFLT + 6] =3D &mac_low11_read, + [FFLT ... FFLT + 6] =3D &mac_readreg, [RA ... RA + 31] =3D &mac_readreg, [WUPM ... WUPM + 31] =3D &mac_readreg, [MTA ... MTA + 127] =3D &mac_readreg, [VFTA ... VFTA + 127] =3D &mac_readreg, - [FFMT ... FFMT + 254] =3D &mac_low4_read, + [FFMT ... FFMT + 254] =3D &mac_readreg, [FFVT ... FFVT + 254] =3D &mac_readreg, [PBM ... PBM + 16383] =3D &mac_readreg, }; @@ -1241,26 +1218,27 @@ static const writeops macreg_writeops[] =3D { putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC), - putreg(TDFH), putreg(TDFT), putreg(TDFHS), putreg(TDFTS), - putreg(TDFPC), putreg(RDFH), putreg(RDFT), putreg(RDFHS), - putreg(RDFTS), putreg(RDFPC), putreg(IPAV), putreg(WUC), - putreg(WUS), putreg(AIT), - - [TDLEN] =3D set_dlen, [RDLEN] =3D set_dlen, [TCTL] =3D set_t= ctl, - [TDT] =3D set_tctl, [MDIC] =3D set_mdic, [ICS] =3D set_i= cs, - [TDH] =3D set_16bit, [RDH] =3D set_16bit, [RDT] =3D set_r= dt, - [IMC] =3D set_imc, [IMS] =3D set_ims, [ICR] =3D set_i= cr, - [EECD] =3D set_eecd, [RCTL] =3D set_rx_control, [CTRL] =3D set_c= trl, - [RDTR] =3D set_16bit, [RADV] =3D set_16bit, [TADV] =3D set_1= 6bit, - [ITR] =3D set_16bit, + putreg(IPAV), putreg(WUC), + putreg(WUS), + + [TDLEN] =3D set_dlen, [RDLEN] =3D set_dlen, [TCTL] =3D set_= tctl, + [TDT] =3D set_tctl, [MDIC] =3D set_mdic, [ICS] =3D set_= ics, + [TDH] =3D set_16bit, [RDH] =3D set_16bit, [RDT] =3D set_= rdt, + [IMC] =3D set_imc, [IMS] =3D set_ims, [ICR] =3D set_= icr, + [EECD] =3D set_eecd, [RCTL] =3D set_rx_control, [CTRL] =3D set_= ctrl, + [RDTR] =3D set_16bit, [RADV] =3D set_16bit, [TADV] =3D set_= 16bit, + [ITR] =3D set_16bit, [TDFH] =3D set_11bit, [TDFT] =3D set_= 11bit, + [TDFHS] =3D set_13bit, [TDFTS] =3D set_13bit, [TDFPC] =3D set_= 13bit, + [RDFH] =3D set_13bit, [RDFT] =3D set_13bit, [RDFHS] =3D set_= 13bit, + [RDFTS] =3D set_13bit, [RDFPC] =3D set_13bit, [AIT] =3D set_= 16bit, =20 [IP6AT ... IP6AT + 3] =3D &mac_writereg, [IP4AT ... IP4AT + 6] =3D &ma= c_writereg, - [FFLT ... FFLT + 6] =3D &mac_writereg, + [FFLT ... FFLT + 6] =3D &set_11bit, [RA ... RA + 31] =3D &mac_writereg, [WUPM ... WUPM + 31] =3D &mac_writereg, [MTA ... MTA + 127] =3D &mac_writereg, [VFTA ... VFTA + 127] =3D &mac_writereg, - [FFMT ... FFMT + 254] =3D &mac_writereg, [FFVT ... FFVT + 254] =3D &ma= c_writereg, + [FFMT ... FFMT + 254] =3D &set_4bit, [FFVT ... FFVT + 254] =3D &ma= c_writereg, [PBM ... PBM + 16383] =3D &mac_writereg, }; =20 --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673669199; cv=none; d=zohomail.com; s=zohoarc; b=hjz4/cnP8xO7oBAPzHx1eunuCe2CT0rMXL4B99uwC8mkG4EF4hwRW8S+y+pxXFBzKOopVPbIMR+jfkqSqSjtCxOSmAJueixv6dn3BtKP0pmx58O31UKgHY3i1YTJdidQNI5p5vYTyvpYtAC8+CcwrT9ci2c070nyfR6xJmYxFrs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673669199; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=qQAThEFT+OOf4M3xlMKLI4kuAC9hcUfjxpclwetq4QM=; b=VZalabn//43vkvfiyQh/wq6YuRQco3/EaJcEyrIDo8LsUIqFoGgQmED9tzDZBCIJ/6lbOeMefn+JG644mNxrA0c0//i5tgP0i5gHpcR6CvT98zZhEXXHQnAuWq4y/wc3IrgzdK+EeAra38P86p1gIo5Wb8GOtW055aCIiI2h0Ww= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1036; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669200270100001 Content-Type: text/plain; charset="utf-8" When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 94 +++++++++++++++++++------------------------- 1 file changed, 40 insertions(+), 54 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 181c1e0c2a..e6fc85ea51 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -2440,17 +2440,19 @@ e1000e_set_fcrtl(E1000ECore *core, int index, uint3= 2_t val) core->mac[FCRTL] =3D val & 0x8000FFF8; } =20 -static inline void -e1000e_set_16bit(E1000ECore *core, int index, uint32_t val) -{ - core->mac[index] =3D val & 0xffff; -} +#define E1000E_LOW_BITS_SET_FUNC(num) \ + static void \ + e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ + { \ + core->mac[index] =3D val & (BIT(num) - 1); \ + } =20 -static void -e1000e_set_12bit(E1000ECore *core, int index, uint32_t val) -{ - core->mac[index] =3D val & 0xfff; -} +E1000E_LOW_BITS_SET_FUNC(4) +E1000E_LOW_BITS_SET_FUNC(6) +E1000E_LOW_BITS_SET_FUNC(11) +E1000E_LOW_BITS_SET_FUNC(12) +E1000E_LOW_BITS_SET_FUNC(13) +E1000E_LOW_BITS_SET_FUNC(16) =20 static void e1000e_set_vet(E1000ECore *core, int index, uint32_t val) @@ -2621,22 +2623,6 @@ e1000e_mac_ims_read(E1000ECore *core, int index) return core->mac[IMS]; } =20 -#define E1000E_LOW_BITS_READ_FUNC(num) \ - static uint32_t \ - e1000e_mac_low##num##_read(E1000ECore *core, int index) \ - { \ - return core->mac[index] & (BIT(num) - 1); \ - } \ - -#define E1000E_LOW_BITS_READ(num) \ - e1000e_mac_low##num##_read - -E1000E_LOW_BITS_READ_FUNC(4); -E1000E_LOW_BITS_READ_FUNC(6); -E1000E_LOW_BITS_READ_FUNC(11); -E1000E_LOW_BITS_READ_FUNC(13); -E1000E_LOW_BITS_READ_FUNC(16); - static uint32_t e1000e_mac_swsm_read(E1000ECore *core, int index) { @@ -2930,7 +2916,19 @@ static const readops e1000e_macreg_readops[] =3D { e1000e_getreg(LATECOL), e1000e_getreg(SEQEC), e1000e_getreg(XONTXC), + e1000e_getreg(AIT), + e1000e_getreg(TDFH), + e1000e_getreg(TDFT), + e1000e_getreg(TDFHS), + e1000e_getreg(TDFTS), + e1000e_getreg(TDFPC), e1000e_getreg(WUS), + e1000e_getreg(PBS), + e1000e_getreg(RDFH), + e1000e_getreg(RDFT), + e1000e_getreg(RDFHS), + e1000e_getreg(RDFTS), + e1000e_getreg(RDFPC), e1000e_getreg(GORCL), e1000e_getreg(MGTPRC), e1000e_getreg(EERD), @@ -3066,16 +3064,9 @@ static const readops e1000e_macreg_readops[] =3D { [MPTC] =3D e1000e_mac_read_clr4, [IAC] =3D e1000e_mac_read_clr4, [ICR] =3D e1000e_mac_icr_read, - [RDFH] =3D E1000E_LOW_BITS_READ(13), - [RDFHS] =3D E1000E_LOW_BITS_READ(13), - [RDFPC] =3D E1000E_LOW_BITS_READ(13), - [TDFH] =3D E1000E_LOW_BITS_READ(13), - [TDFHS] =3D E1000E_LOW_BITS_READ(13), [STATUS] =3D e1000e_get_status, [TARC0] =3D e1000e_get_tarc, - [PBS] =3D E1000E_LOW_BITS_READ(6), [ICS] =3D e1000e_mac_ics_read, - [AIT] =3D E1000E_LOW_BITS_READ(16), [TORH] =3D e1000e_mac_read_clr8, [GORCH] =3D e1000e_mac_read_clr8, [PRC127] =3D e1000e_mac_read_clr4, @@ -3091,11 +3082,6 @@ static const readops e1000e_macreg_readops[] =3D { [BPTC] =3D e1000e_mac_read_clr4, [TSCTC] =3D e1000e_mac_read_clr4, [ITR] =3D e1000e_mac_itr_read, - [RDFT] =3D E1000E_LOW_BITS_READ(13), - [RDFTS] =3D E1000E_LOW_BITS_READ(13), - [TDFPC] =3D E1000E_LOW_BITS_READ(13), - [TDFT] =3D E1000E_LOW_BITS_READ(13), - [TDFTS] =3D E1000E_LOW_BITS_READ(13), [CTRL] =3D e1000e_get_ctrl, [TARC1] =3D e1000e_get_tarc, [SWSM] =3D e1000e_mac_swsm_read, @@ -3108,10 +3094,10 @@ static const readops e1000e_macreg_readops[] =3D { [WUPM ... WUPM + 31] =3D e1000e_mac_readreg, [MTA ... MTA + 127] =3D e1000e_mac_readreg, [VFTA ... VFTA + 127] =3D e1000e_mac_readreg, - [FFMT ... FFMT + 254] =3D E1000E_LOW_BITS_READ(4), + [FFMT ... FFMT + 254] =3D e1000e_mac_readreg, [FFVT ... FFVT + 254] =3D e1000e_mac_readreg, [MDEF ... MDEF + 7] =3D e1000e_mac_readreg, - [FFLT ... FFLT + 10] =3D E1000E_LOW_BITS_READ(11), + [FFLT ... FFLT + 10] =3D e1000e_mac_readreg, [FTFT ... FTFT + 254] =3D e1000e_mac_readreg, [PBM ... PBM + 10239] =3D e1000e_mac_readreg, [RETA ... RETA + 31] =3D e1000e_mac_readreg, @@ -3134,19 +3120,8 @@ static const writeops e1000e_macreg_writeops[] =3D { e1000e_putreg(LEDCTL), e1000e_putreg(FCAL), e1000e_putreg(FCRUC), - e1000e_putreg(AIT), - e1000e_putreg(TDFH), - e1000e_putreg(TDFT), - e1000e_putreg(TDFHS), - e1000e_putreg(TDFTS), - e1000e_putreg(TDFPC), e1000e_putreg(WUC), e1000e_putreg(WUS), - e1000e_putreg(RDFH), - e1000e_putreg(RDFT), - e1000e_putreg(RDFHS), - e1000e_putreg(RDFTS), - e1000e_putreg(RDFPC), e1000e_putreg(IPAV), e1000e_putreg(TDBAH1), e1000e_putreg(TIMINCA), @@ -3157,7 +3132,6 @@ static const writeops e1000e_macreg_writeops[] =3D { e1000e_putreg(TARC1), e1000e_putreg(FLSWDATA), e1000e_putreg(POEMB), - e1000e_putreg(PBS), e1000e_putreg(MFUTP01), e1000e_putreg(MFUTP23), e1000e_putreg(MANC), @@ -3222,6 +3196,18 @@ static const writeops e1000e_macreg_writeops[] =3D { [TADV] =3D e1000e_set_16bit, [ITR] =3D e1000e_set_itr, [EERD] =3D e1000e_set_eerd, + [AIT] =3D e1000e_set_16bit, + [TDFH] =3D e1000e_set_13bit, + [TDFT] =3D e1000e_set_13bit, + [TDFHS] =3D e1000e_set_13bit, + [TDFTS] =3D e1000e_set_13bit, + [TDFPC] =3D e1000e_set_13bit, + [RDFH] =3D e1000e_set_13bit, + [RDFHS] =3D e1000e_set_13bit, + [RDFT] =3D e1000e_set_13bit, + [RDFTS] =3D e1000e_set_13bit, + [RDFPC] =3D e1000e_set_13bit, + [PBS] =3D e1000e_set_6bit, [GCR] =3D e1000e_set_gcr, [PSRCTL] =3D e1000e_set_psrctl, [RXCSUM] =3D e1000e_set_rxcsum, @@ -3261,11 +3247,11 @@ static const writeops e1000e_macreg_writeops[] =3D { [WUPM ... WUPM + 31] =3D e1000e_mac_writereg, [MTA ... MTA + 127] =3D e1000e_mac_writereg, [VFTA ... VFTA + 127] =3D e1000e_mac_writereg, - [FFMT ... FFMT + 254] =3D e1000e_mac_writereg, + [FFMT ... FFMT + 254] =3D e1000e_set_4bit, [FFVT ... FFVT + 254] =3D e1000e_mac_writereg, [PBM ... PBM + 10239] =3D e1000e_mac_writereg, [MDEF ... MDEF + 7] =3D e1000e_mac_writereg, - [FFLT ... FFLT + 10] =3D e1000e_mac_writereg, + [FFLT ... FFLT + 10] =3D e1000e_set_11bit, [FTFT ... FTFT + 254] =3D e1000e_mac_writereg, [RETA ... RETA + 31] =3D e1000e_mac_writereg, [RSSRK ... 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102d; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673670938814100001 The definitions for E1000_VFTA_ENTRY_SHIFT, E1000_VFTA_ENTRY_MASK, and E1000_VFTA_ENTRY_BIT_SHIFT_MASK were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drive= rs/net/ethernet/intel/e1000/e1000_hw.h?h=3Dv6.0.9#n306 The definitions for E1000_NUM_UNICAST, E1000_MC_TBL_SIZE, and E1000_VLAN_FILTER_TBL_SIZE were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drive= rs/net/ethernet/intel/e1000/e1000_hw.h?h=3Dv6.0.9#n707 Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/e1000.c | 50 +++++++++++++++++++++++------------------- hw/net/e1000_regs.h | 9 ++++++++ hw/net/e1000x_common.c | 5 +++-- hw/net/e1000x_common.h | 2 +- 4 files changed, 41 insertions(+), 25 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 0925a99511..d9d048f665 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -43,8 +43,6 @@ #include "trace.h" #include "qom/object.h" =20 -static const uint8_t bcast[] =3D {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - /* #define E1000_DEBUG */ =20 #ifdef E1000_DEBUG @@ -67,9 +65,8 @@ static int debugflags =3D DBGBIT(TXERR) | DBGBIT(GENERAL); =20 #define IOPORT_SIZE 0x40 #define PNPMMIO_SIZE 0x20000 -#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS = */ =20 -#define MAXIMUM_ETHERNET_HDR_LEN (14+4) +#define MAXIMUM_ETHERNET_HDR_LEN (ETH_HLEN + 4) =20 /* * HW models: @@ -239,10 +236,16 @@ static const uint16_t phy_reg_init[] =3D { =20 [MII_PHYID1] =3D 0x141, /* [MII_PHYID2] configured per DevId, from e1000_reset() */ - [MII_ANAR] =3D 0xde1, - [MII_ANLPAR] =3D 0x1e0, - [MII_CTRL1000] =3D 0x0e00, - [MII_STAT1000] =3D 0x3c00, + [MII_ANAR] =3D MII_ANAR_CSMACD | MII_ANAR_10 | + MII_ANAR_10FD | MII_ANAR_TX | + MII_ANAR_TXFD | MII_ANAR_PAUSE | + MII_ANAR_PAUSE_ASYM, + [MII_ANLPAR] =3D MII_ANLPAR_10 | MII_ANLPAR_10FD | + MII_ANLPAR_TX | MII_ANLPAR_TXFD, + [MII_CTRL1000] =3D MII_CTRL1000_FULL | MII_CTRL1000_PORT | + MII_CTRL1000_MASTER, + [MII_STAT1000] =3D MII_STAT1000_HALF | MII_STAT1000_FULL | + MII_STAT1000_ROK | MII_STAT1000_LOK, [M88E1000_PHY_SPEC_CTRL] =3D 0x360, [M88E1000_PHY_SPEC_STATUS] =3D 0xac00, [M88E1000_EXT_PHY_SPEC_CTRL] =3D 0x0d60, @@ -548,9 +551,9 @@ putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32= _t css, uint32_t cse) static inline void inc_tx_bcast_or_mcast_count(E1000State *s, const unsigned char *arr) { - if (!memcmp(arr, bcast, sizeof bcast)) { + if (is_broadcast_ether_addr(arr)) { e1000x_inc_reg_if_not_full(s->mac_reg, BPTC); - } else if (arr[0] & 1) { + } else if (is_multicast_ether_addr(arr)) { e1000x_inc_reg_if_not_full(s->mac_reg, MPTC); } } @@ -804,14 +807,16 @@ static int receive_filter(E1000State *s, const uint8_t *buf, int size) { uint32_t rctl =3D s->mac_reg[RCTL]; - int isbcast =3D !memcmp(buf, bcast, sizeof bcast), ismcast =3D (buf[0]= & 1); + int isbcast =3D is_broadcast_ether_addr(buf); + int ismcast =3D is_multicast_ether_addr(buf); =20 if (e1000x_is_vlan_packet(buf, le16_to_cpu(s->mac_reg[VET])) && e1000x_vlan_rx_filter_enabled(s->mac_reg)) { - uint16_t vid =3D lduw_be_p(buf + 14); - uint32_t vfta =3D ldl_le_p((uint32_t *)(s->mac_reg + VFTA) + - ((vid >> 5) & 0x7f)); - if ((vfta & (1 << (vid & 0x1f))) =3D=3D 0) { + uint16_t vid =3D lduw_be_p(&PKT_GET_VLAN_HDR(buf)->h_tci); + uint32_t vfta =3D + ldl_le_p((uint32_t *)(s->mac_reg + VFTA) + + ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_M= ASK)); + if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) =3D=3D= 0) { return 0; } } @@ -909,7 +914,7 @@ e1000_receive_iov(NetClientState *nc, const struct iove= c *iov, int iovcnt) uint32_t rdh_start; uint16_t vlan_special =3D 0; uint8_t vlan_status =3D 0; - uint8_t min_buf[MIN_BUF_SIZE]; + uint8_t min_buf[ETH_ZLEN]; struct iovec min_iov; uint8_t *filter_buf =3D iov->iov_base; size_t size =3D iov_size(iov, iovcnt); @@ -1204,8 +1209,8 @@ static const readops macreg_readops[] =3D { [FFLT ... FFLT + 6] =3D &mac_readreg, [RA ... RA + 31] =3D &mac_readreg, [WUPM ... WUPM + 31] =3D &mac_readreg, - [MTA ... MTA + 127] =3D &mac_readreg, - [VFTA ... VFTA + 127] =3D &mac_readreg, + [MTA ... MTA + E1000_MC_TBL_SIZE - 1] =3D &mac_readreg, + [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] =3D &mac_readreg, [FFMT ... FFMT + 254] =3D &mac_readreg, [FFVT ... FFVT + 254] =3D &mac_readreg, [PBM ... PBM + 16383] =3D &mac_readreg, @@ -1236,8 +1241,8 @@ static const writeops macreg_writeops[] =3D { [FFLT ... FFLT + 6] =3D &set_11bit, [RA ... RA + 31] =3D &mac_writereg, [WUPM ... WUPM + 31] =3D &mac_writereg, - [MTA ... MTA + 127] =3D &mac_writereg, - [VFTA ... VFTA + 127] =3D &mac_writereg, + [MTA ... MTA + E1000_MC_TBL_SIZE - 1] =3D &mac_writereg, + [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] =3D &mac_writereg, [FFMT ... FFMT + 254] =3D &set_4bit, [FFVT ... FFVT + 254] =3D &ma= c_writereg, [PBM ... PBM + 16383] =3D &mac_writereg, }; @@ -1603,8 +1608,9 @@ static const VMStateDescription vmstate_e1000 =3D { VMSTATE_UINT32(mac_reg[WUFC], E1000State), VMSTATE_UINT32(mac_reg[VET], E1000State), VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32), - VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128), - VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128), + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, E1000_MC_TBL_SI= ZE), + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, + E1000_VLAN_FILTER_TBL_SIZE), VMSTATE_END_OF_LIST() }, .subsections =3D (const VMStateDescription*[]) { diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h index 59d6eb3189..3f6b5d0c52 100644 --- a/hw/net/e1000_regs.h +++ b/hw/net/e1000_regs.h @@ -1154,6 +1154,11 @@ struct e1000_data_desc { } upper; }; =20 +/* Filters */ +#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ +#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bit= s) */ +#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ + /* Management Control */ #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ @@ -1202,4 +1207,8 @@ struct e1000_data_desc { #define E1000_IOADDR 0x00 #define E1000_IODATA 0x04 =20 +#define E1000_VFTA_ENTRY_SHIFT 5 +#define E1000_VFTA_ENTRY_MASK 0x7F +#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F + #endif /* HW_E1000_REGS_H */ diff --git a/hw/net/e1000x_common.c b/hw/net/e1000x_common.c index e79d4c79bd..b3bbf31582 100644 --- a/hw/net/e1000x_common.c +++ b/hw/net/e1000x_common.c @@ -26,6 +26,7 @@ #include "qemu/units.h" #include "hw/net/mii.h" #include "hw/pci/pci_device.h" +#include "net/eth.h" #include "net/net.h" =20 #include "e1000x_common.h" @@ -48,7 +49,7 @@ bool e1000x_rx_ready(PCIDevice *d, uint32_t *mac) =20 bool e1000x_is_vlan_packet(const uint8_t *buf, uint16_t vet) { - uint16_t eth_proto =3D lduw_be_p(buf + 12); + uint16_t eth_proto =3D lduw_be_p(&PKT_GET_ETH_HDR(buf)->h_proto); bool res =3D (eth_proto =3D=3D vet); =20 trace_e1000x_vlan_is_vlan_pkt(res, eth_proto, vet); @@ -67,7 +68,7 @@ bool e1000x_rx_group_filter(uint32_t *mac, const uint8_t = *buf) } ra[0] =3D cpu_to_le32(rp[0]); ra[1] =3D cpu_to_le32(rp[1]); - if (!memcmp(buf, (uint8_t *)ra, 6)) { + if (!memcmp(buf, (uint8_t *)ra, ETH_ALEN)) { trace_e1000x_rx_flt_ucast_match((int)(rp - mac - RA) / 2, MAC_ARG(buf)); return true; diff --git a/hw/net/e1000x_common.h b/hw/net/e1000x_common.h index 3501e4855a..b991d814b1 100644 --- a/hw/net/e1000x_common.h +++ b/hw/net/e1000x_common.h @@ -102,7 +102,7 @@ enum { static inline void e1000x_inc_reg_if_not_full(uint32_t *mac, int index) { - if (mac[index] !=3D 0xffffffff) { + if (mac[index] !=3D UINT32_MAX) { mac[index]++; } } --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 13 Jan 2023 20:00:10 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki Subject: [PATCH 08/19] e1000e: Use more constant definitions Date: Sat, 14 Jan 2023 12:59:08 +0900 Message-Id: <20230114035919.35251-9-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1034; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673670984841100001 Content-Type: text/plain; charset="utf-8" The definitions of SW Semaphore Register were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drive= rs/net/ethernet/intel/e1000e/defines.h?h=3Dv6.0.9#n374 Signed-off-by: Akihiko Odaki --- hw/net/e1000_regs.h | 7 +++++++ hw/net/e1000e_core.c | 49 ++++++++++++++++++++++++-------------------- 2 files changed, 34 insertions(+), 22 deletions(-) diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h index 3f6b5d0c52..6a36573802 100644 --- a/hw/net/e1000_regs.h +++ b/hw/net/e1000_regs.h @@ -525,6 +525,13 @@ #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ =20 +/* SW Semaphore Register */ +#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ +#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ + +#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore b= it */ + /* Interrupt Cause Read */ #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index e6fc85ea51..6a4da72bd3 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -1022,10 +1022,11 @@ e1000e_receive_filter(E1000ECore *core, const uint8= _t *buf, int size) =20 if (e1000x_is_vlan_packet(buf, core->mac[VET]) && e1000x_vlan_rx_filter_enabled(core->mac)) { - uint16_t vid =3D lduw_be_p(buf + 14); - uint32_t vfta =3D ldl_le_p((uint32_t *)(core->mac + VFTA) + - ((vid >> 5) & 0x7f)); - if ((vfta & (1 << (vid & 0x1f))) =3D=3D 0) { + uint16_t vid =3D lduw_be_p(&PKT_GET_VLAN_HDR(buf)->h_tci); + uint32_t vfta =3D + ldl_le_p((uint32_t *)(core->mac + VFTA) + + ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_M= ASK)); + if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) =3D=3D= 0) { trace_e1000e_rx_flt_vlan_mismatch(vid); return false; } else { @@ -1679,16 +1680,13 @@ e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetR= xPkt *pkt) } } =20 -/* Min. octets in an ethernet frame sans FCS */ -#define MIN_BUF_SIZE 60 - ssize_t e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) { - static const int maximum_ethernet_hdr_len =3D (14 + 4); + static const int maximum_ethernet_hdr_len =3D (ETH_HLEN + 4); =20 uint32_t n =3D 0; - uint8_t min_buf[MIN_BUF_SIZE]; + uint8_t min_buf[ETH_ZLEN]; struct iovec min_iov; uint8_t *filter_buf; size_t size, orig_size; @@ -2627,7 +2625,7 @@ static uint32_t e1000e_mac_swsm_read(E1000ECore *core, int index) { uint32_t val =3D core->mac[SWSM]; - core->mac[SWSM] =3D val | 1; + core->mac[SWSM] =3D val | E1000_SWSM_SMBI; return val; } =20 @@ -3092,8 +3090,8 @@ static const readops e1000e_macreg_readops[] =3D { [IP4AT ... IP4AT + 6] =3D e1000e_mac_readreg, [RA ... RA + 31] =3D e1000e_mac_readreg, [WUPM ... WUPM + 31] =3D e1000e_mac_readreg, - [MTA ... MTA + 127] =3D e1000e_mac_readreg, - [VFTA ... VFTA + 127] =3D e1000e_mac_readreg, + [MTA ... MTA + E1000_MC_TBL_SIZE - 1] =3D e1000e_mac_readreg, + [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] =3D e1000e_mac_readr= eg, [FFMT ... FFMT + 254] =3D e1000e_mac_readreg, [FFVT ... FFVT + 254] =3D e1000e_mac_readreg, [MDEF ... MDEF + 7] =3D e1000e_mac_readreg, @@ -3245,8 +3243,8 @@ static const writeops e1000e_macreg_writeops[] =3D { [IP4AT ... IP4AT + 6] =3D e1000e_mac_writereg, [RA + 2 ... RA + 31] =3D e1000e_mac_writereg, [WUPM ... WUPM + 31] =3D e1000e_mac_writereg, - [MTA ... MTA + 127] =3D e1000e_mac_writereg, - [VFTA ... VFTA + 127] =3D e1000e_mac_writereg, + [MTA ... MTA + E1000_MC_TBL_SIZE - 1] =3D e1000e_mac_writereg, + [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] =3D e1000e_mac_wri= tereg, [FFMT ... FFMT + 254] =3D e1000e_set_4bit, [FFVT ... FFVT + 254] =3D e1000e_mac_writereg, [PBM ... PBM + 10239] =3D e1000e_mac_writereg, @@ -3276,7 +3274,7 @@ static const uint16_t mac_reg_access[E1000E_MAC_SIZE]= =3D { [TDH_A] =3D 0x0cf8, [TDT_A] =3D 0x0cf8, [TIDV_A] =3D 0x0cf8, [TDFH_A] =3D 0xed00, [TDFT_A] =3D 0xed00, [RA_A ... RA_A + 31] =3D 0x14f0, - [VFTA_A ... VFTA_A + 127] =3D 0x1400, + [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] =3D 0x1400, [RDBAL0_A ... RDLEN0_A] =3D 0x09bc, [TDBAL_A ... TDLEN_A] =3D 0x0cf8, /* Access options */ @@ -3433,13 +3431,20 @@ e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PA= GE_SIZE] =3D { =20 [MII_PHYID1] =3D 0x141, [MII_PHYID2] =3D E1000_PHY_ID2_82574x, - [MII_ANAR] =3D 0xde1, - [MII_ANLPAR] =3D 0x7e0, - [MII_ANER] =3D BIT(2), - [MII_ANNP] =3D BIT(0) | BIT(13), - [MII_CTRL1000] =3D BIT(8) | BIT(9) | BIT(10) | BIT(11), - [MII_STAT1000] =3D 0x3c00, - [MII_EXTSTAT] =3D BIT(12) | BIT(13), + [MII_ANAR] =3D MII_ANAR_CSMACD | MII_ANAR_10 | + MII_ANAR_10FD | MII_ANAR_TX | + MII_ANAR_TXFD | MII_ANAR_PAUSE | + MII_ANAR_PAUSE_ASYM, + [MII_ANLPAR] =3D MII_ANLPAR_10 | MII_ANLPAR_10FD | + MII_ANLPAR_TX | MII_ANLPAR_TXFD | + MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, + [MII_ANER] =3D MII_ANER_NP, + [MII_ANNP] =3D 1 | MII_ANNP_MP, + [MII_CTRL1000] =3D MII_CTRL1000_HALF | MII_CTRL1000_FULL | + MII_CTRL1000_PORT | MII_CTRL1000_MASTER, + [MII_STAT1000] =3D MII_STAT1000_HALF | MII_STAT1000_FULL | + MII_STAT1000_ROK | MII_STAT1000_LOK, + [MII_EXTSTAT] =3D MII_EXTSTAT_1000T_HD | MII_EXTSTAT_100= 0T_FD, =20 [PHY_COPPER_CTRL1] =3D BIT(5) | BIT(6) | BIT(8) | BIT(9) | BIT(12) | BIT(13), --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 13 Jan 2023 20:00:13 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki Subject: [PATCH 09/19] e1000: Use memcpy to intialize registers Date: Sat, 14 Jan 2023 12:59:09 +0900 Message-Id: <20230114035919.35251-10-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1032; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669928764100001 Content-Type: text/plain; charset="utf-8" Use memcpy instead of memmove to initialize registers. The initial register templates and register table instances will never overlap. Signed-off-by: Akihiko Odaki --- hw/net/e1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index d9d048f665..3353a3752c 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -390,10 +390,10 @@ static void e1000_reset(void *opaque) d->mit_irq_level =3D 0; d->mit_ide =3D 0; memset(d->phy_reg, 0, sizeof d->phy_reg); - memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init); + memcpy(d->phy_reg, phy_reg_init, sizeof phy_reg_init); d->phy_reg[MII_PHYID2] =3D edc->phy_id2; memset(d->mac_reg, 0, sizeof d->mac_reg); - memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init); + memcpy(d->mac_reg, mac_reg_init, sizeof mac_reg_init); d->rxbuf_min_shift =3D 1; memset(&d->tx, 0, sizeof d->tx); =20 --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 13 Jan 2023 20:00:15 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki Subject: [PATCH 10/19] e1000e: Use memcpy to intialize registers Date: Sat, 14 Jan 2023 12:59:10 +0900 Message-Id: <20230114035919.35251-11-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1035; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669157942100001 Content-Type: text/plain; charset="utf-8" Use memcpy instead of memmove to initialize registers. The initial register templates and register table instances will never overlap. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 6a4da72bd3..87f964cdc1 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -3511,9 +3511,9 @@ e1000e_core_reset(E1000ECore *core) e1000e_intrmgr_reset(core); =20 memset(core->phy, 0, sizeof core->phy); - memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); + memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); memset(core->mac, 0, sizeof core->mac); - memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init); + memcpy(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init); =20 core->rxbuf_min_shift =3D 1 + E1000_RING_DESC_LEN_SHIFT; =20 --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 13 Jan 2023 20:00:18 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki Subject: [PATCH 11/19] e1000e: Remove pending interrupt flags Date: Sat, 14 Jan 2023 12:59:11 +0900 Message-Id: <20230114035919.35251-12-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1035; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669274523100001 Content-Type: text/plain; charset="utf-8" They are duplicate of running throttling timer flags and incomplete as the flags are not cleared when the interrupts are fired or the device is reset. Signed-off-by: Akihiko Odaki --- hw/net/e1000e.c | 5 ++--- hw/net/e1000e_core.c | 19 +++---------------- hw/net/e1000e_core.h | 2 -- hw/net/trace-events | 2 -- 4 files changed, 5 insertions(+), 23 deletions(-) diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index d591d01c07..0bc222d354 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -631,12 +631,11 @@ static const VMStateDescription e1000e_vmstate =3D { VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState), =20 VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState), - VMSTATE_BOOL(core.itr_intr_pending, E1000EState), + VMSTATE_UNUSED(1), =20 VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState, E1000E_MSIX_VEC_NUM), - VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState, - E1000E_MSIX_VEC_NUM), + VMSTATE_UNUSED(E1000E_MSIX_VEC_NUM), =20 VMSTATE_UINT32(core.itr_guest_value, E1000EState), VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState, diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 87f964cdc1..37aec6a970 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -154,11 +154,6 @@ e1000e_intrmgr_on_throttling_timer(void *opaque) =20 timer->running =3D false; =20 - if (!timer->core->itr_intr_pending) { - trace_e1000e_irq_throttling_no_pending_interrupts(); - return; - } - if (msi_enabled(timer->core->owner)) { trace_e1000e_irq_msi_notify_postponed(); /* Clear msi_causes_pending to fire MSI eventually */ @@ -180,11 +175,6 @@ e1000e_intrmgr_on_msix_throttling_timer(void *opaque) =20 timer->running =3D false; =20 - if (!timer->core->eitr_intr_pending[idx]) { - trace_e1000e_irq_throttling_no_pending_vec(idx); - return; - } - trace_e1000e_irq_msix_notify_postponed_vec(idx); msix_notify(timer->core->owner, idx); } @@ -2015,13 +2005,11 @@ e1000e_clear_ims_bits(E1000ECore *core, uint32_t bi= ts) } =20 static inline bool -e1000e_postpone_interrupt(bool *interrupt_pending, - E1000IntrDelayTimer *timer) +e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) { if (timer->running) { trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); =20 - *interrupt_pending =3D true; return true; } =20 @@ -2035,14 +2023,13 @@ e1000e_postpone_interrupt(bool *interrupt_pending, static inline bool e1000e_itr_should_postpone(E1000ECore *core) { - return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr); + return e1000e_postpone_interrupt(&core->itr); } =20 static inline bool e1000e_eitr_should_postpone(E1000ECore *core, int idx) { - return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx], - &core->eitr[idx]); + return e1000e_postpone_interrupt(&core->eitr[idx]); } =20 static void diff --git a/hw/net/e1000e_core.h b/hw/net/e1000e_core.h index b8f38c47a0..d0a14b4523 100644 --- a/hw/net/e1000e_core.h +++ b/hw/net/e1000e_core.h @@ -95,10 +95,8 @@ struct E1000Core { E1000IntrDelayTimer tidv; =20 E1000IntrDelayTimer itr; - bool itr_intr_pending; =20 E1000IntrDelayTimer eitr[E1000E_MSIX_VEC_NUM]; - bool eitr_intr_pending[E1000E_MSIX_VEC_NUM]; =20 VMChangeStateEntry *vmstate; =20 diff --git a/hw/net/trace-events b/hw/net/trace-events index 4c0ec3fda1..8fa4299704 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -201,10 +201,8 @@ e1000e_rx_metadata_ipv6_filtering_disabled(void) "IPv6= RX filtering disabled by e1000e_vlan_vet(uint16_t vet) "Setting VLAN ethernet type 0x%X" =20 e1000e_irq_msi_notify(uint32_t cause) "MSI notify 0x%x" -e1000e_irq_throttling_no_pending_interrupts(void) "No pending interrupts t= o notify" e1000e_irq_msi_notify_postponed(void) "Sending MSI postponed by ITR" e1000e_irq_legacy_notify_postponed(void) "Raising legacy IRQ postponed by = ITR" -e1000e_irq_throttling_no_pending_vec(int idx) "No pending interrupts for v= ector %d" e1000e_irq_msix_notify_postponed_vec(int idx) "Sending MSI-X postponed by = EITR[%d]" e1000e_irq_legacy_notify(bool level) "IRQ line state: %d" e1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X notify vector 0x%x" --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 13 Jan 2023 20:00:20 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki Subject: [PATCH 12/19] e1000e: Improve software reset Date: Sat, 14 Jan 2023 12:59:12 +0900 Message-Id: <20230114035919.35251-13-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::62e; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673670028921100001 Content-Type: text/plain; charset="utf-8" This change makes e1000e reset more things when software reset was triggered. Some registers are exempted from software reset in the datasheet and this change also implements the behavior accordingly. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 37aec6a970..b8670662c8 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -58,6 +58,8 @@ static inline void e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); =20 +static void e1000e_reset(E1000ECore *core, bool sw); + static inline void e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) { @@ -1882,7 +1884,7 @@ e1000e_set_ctrl(E1000ECore *core, int index, uint32_t= val) =20 if (val & E1000_CTRL_RST) { trace_e1000e_core_ctrl_sw_reset(); - e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_= mac); + e1000e_reset(core, true); } =20 if (val & E1000_CTRL_PHY_RST) { @@ -3488,8 +3490,7 @@ static const uint32_t e1000e_mac_reg_init[] =3D { [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] =3D E1000E_MIN_XITR, }; =20 -void -e1000e_core_reset(E1000ECore *core) +static void e1000e_reset(E1000ECore *core, bool sw) { int i; =20 @@ -3499,8 +3500,15 @@ e1000e_core_reset(E1000ECore *core) =20 memset(core->phy, 0, sizeof core->phy); memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); - memset(core->mac, 0, sizeof core->mac); - memcpy(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init); + + for (i =3D 0; i < E1000E_MAC_SIZE; i++) { + if (sw && (i =3D=3D PBA || i =3D=3D PBS || i =3D=3D FLA)) { + continue; + } + + core->mac[i] =3D i < ARRAY_SIZE(e1000e_mac_reg_init) ? + e1000e_mac_reg_init[i] : 0; + } =20 core->rxbuf_min_shift =3D 1 + E1000_RING_DESC_LEN_SHIFT; =20 @@ -3517,6 +3525,12 @@ e1000e_core_reset(E1000ECore *core) } } =20 +void +e1000e_core_reset(E1000ECore *core) +{ + e1000e_reset(core, false); +} + void e1000e_core_pre_save(E1000ECore *core) { int i; --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 13 Jan 2023 20:00:23 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 13/19] e1000: Configure ResettableClass Date: Sat, 14 Jan 2023 12:59:13 +0900 Message-Id: <20230114035919.35251-14-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102c; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673670629254100001 This is part of recent efforts of refactoring e1000 and e1000e. DeviceClass's reset member is deprecated so migrate to ResettableClass. There is no behavioral difference. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/e1000.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 3353a3752c..c81d914a02 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -377,9 +377,9 @@ static bool e1000_vet_init_need(void *opaque) return chkflag(VET); } =20 -static void e1000_reset(void *opaque) +static void e1000_reset_hold(Object *obj) { - E1000State *d =3D opaque; + E1000State *d =3D E1000(obj); E1000BaseClass *edc =3D E1000_GET_CLASS(d); uint8_t *macaddr =3D d->conf.macaddr.a; =20 @@ -1731,12 +1731,6 @@ static void pci_e1000_realize(PCIDevice *pci_dev, Er= ror **errp) e1000_flush_queue_timer, d); } =20 -static void qdev_e1000_reset(DeviceState *dev) -{ - E1000State *d =3D E1000(dev); - e1000_reset(d); -} - static Property e1000_properties[] =3D { DEFINE_NIC_PROPERTIES(E1000State, conf), DEFINE_PROP_BIT("autonegotiation", E1000State, @@ -1762,6 +1756,7 @@ typedef struct E1000Info { static void e1000_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); E1000BaseClass *e =3D E1000_CLASS(klass); const E1000Info *info =3D data; @@ -1774,9 +1769,9 @@ static void e1000_class_init(ObjectClass *klass, void= *data) k->revision =3D info->revision; e->phy_id2 =3D info->phy_id2; k->class_id =3D PCI_CLASS_NETWORK_ETHERNET; + rc->phases.hold =3D e1000_reset_hold; set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->desc =3D "Intel Gigabit Ethernet"; - dc->reset =3D qdev_e1000_reset; dc->vmsd =3D &vmstate_e1000; device_class_set_props(dc, e1000_properties); } --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673671290; cv=none; d=zohomail.com; s=zohoarc; b=RCauNw9EbPdGrrZ+CWLIW8BWIiU2V2+X4WzuA8TVvd1KgpIuECQUGP51vi2MHNEsz/VXfUlwWAkhnFtvXcdRNIUGc1UukYozApoC9jGjhDlKKI3AFcHwoe7zbc0QxcXqxES3HaZZwGbQRmPDJ/NqAMNvT6BOuIPntnMmatQZDm8= ARC-Message-Signature: i=1; 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Fri, 13 Jan 2023 20:00:25 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 14/19] e1000e: Configure ResettableClass Date: Sat, 14 Jan 2023 12:59:14 +0900 Message-Id: <20230114035919.35251-15-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102b; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673671292351100001 This is part of recent efforts of refactoring e1000 and e1000e. DeviceClass's reset member is deprecated so migrate to ResettableClass. There is no behavioral difference. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/e1000e.c | 10 ++++++---- hw/net/trace-events | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 0bc222d354..ec274319c4 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -513,11 +513,11 @@ static void e1000e_pci_uninit(PCIDevice *pci_dev) msi_uninit(pci_dev); } =20 -static void e1000e_qdev_reset(DeviceState *dev) +static void e1000e_qdev_reset_hold(Object *obj) { - E1000EState *s =3D E1000E(dev); + E1000EState *s =3D E1000E(obj); =20 - trace_e1000e_cb_qdev_reset(); + trace_e1000e_cb_qdev_reset_hold(); =20 e1000e_core_reset(&s->core); =20 @@ -669,6 +669,7 @@ static Property e1000e_properties[] =3D { static void e1000e_class_init(ObjectClass *class, void *data) { DeviceClass *dc =3D DEVICE_CLASS(class); + ResettableClass *rc =3D RESETTABLE_CLASS(class); PCIDeviceClass *c =3D PCI_DEVICE_CLASS(class); =20 c->realize =3D e1000e_pci_realize; @@ -679,8 +680,9 @@ static void e1000e_class_init(ObjectClass *class, void = *data) c->romfile =3D "efi-e1000e.rom"; c->class_id =3D PCI_CLASS_NETWORK_ETHERNET; =20 + rc->phases.hold =3D e1000e_qdev_reset_hold; + dc->desc =3D "Intel 82574L GbE Controller"; - dc->reset =3D e1000e_qdev_reset; dc->vmsd =3D &e1000e_vmstate; =20 e1000e_prop_disable_vnet =3D qdev_prop_uint8; diff --git a/hw/net/trace-events b/hw/net/trace-events index 8fa4299704..c98ad12537 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -251,7 +251,7 @@ e1000e_vm_state_stopped(void) "VM state is stopped" # e1000e.c e1000e_cb_pci_realize(void) "E1000E PCI realize entry" e1000e_cb_pci_uninit(void) "E1000E PCI unit entry" -e1000e_cb_qdev_reset(void) "E1000E qdev reset entry" +e1000e_cb_qdev_reset_hold(void) "E1000E qdev reset hold" e1000e_cb_pre_save(void) "E1000E pre save entry" e1000e_cb_post_load(void) "E1000E post load entry" =20 --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 13 Jan 2023 20:00:27 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki Subject: [PATCH 15/19] e1000e: Introduce e1000_rx_desc_union Date: Sat, 14 Jan 2023 12:59:15 +0900 Message-Id: <20230114035919.35251-16-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102d; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669942610100001 Content-Type: text/plain; charset="utf-8" Before this change, e1000e_write_packet_to_guest() allocated the receive descriptor buffer as an array of uint8_t. This does not ensure the buffer is sufficiently aligned. Introduce e1000_rx_desc_union type, a union type of all receive descriptor types to correct this. Signed-off-by: Akihiko Odaki --- hw/net/e1000_regs.h | 1 - hw/net/e1000e_core.c | 115 +++++++++++++++++++++---------------------- 2 files changed, 57 insertions(+), 59 deletions(-) diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h index 6a36573802..4545fe25a6 100644 --- a/hw/net/e1000_regs.h +++ b/hw/net/e1000_regs.h @@ -1061,7 +1061,6 @@ union e1000_rx_desc_packet_split { #define E1000_RING_DESC_LEN_SHIFT (4) =20 #define E1000_MIN_RX_DESC_LEN E1000_RING_DESC_LEN -#define E1000_MAX_RX_DESC_LEN (sizeof(union e1000_rx_desc_packet_split)) =20 /* Receive Descriptor bit definitions */ #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index b8670662c8..d8c17baf8f 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -55,6 +55,12 @@ =20 #define E1000E_MAX_TX_FRAGS (64) =20 +union e1000_rx_desc_union { + struct e1000_rx_desc legacy; + union e1000_rx_desc_extended extended; + union e1000_rx_desc_packet_split packet_split; +}; + static inline void e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); =20 @@ -1053,29 +1059,28 @@ e1000e_receive_filter(E1000ECore *core, const uint8= _t *buf, int size) } =20 static inline void -e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_ad= dr) +e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, + hwaddr *buff_addr) { - struct e1000_rx_desc *d =3D (struct e1000_rx_desc *) desc; - *buff_addr =3D le64_to_cpu(d->buffer_addr); + *buff_addr =3D le64_to_cpu(desc->buffer_addr); } =20 static inline void -e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_add= r) +e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *d= esc, + hwaddr *buff_addr) { - union e1000_rx_desc_extended *d =3D (union e1000_rx_desc_extended *) d= esc; - *buff_addr =3D le64_to_cpu(d->read.buffer_addr); + *buff_addr =3D le64_to_cpu(desc->read.buffer_addr); } =20 static inline void -e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc, +e1000e_read_ps_rx_descr(E1000ECore *core, + union e1000_rx_desc_packet_split *desc, hwaddr (*buff_addr)[MAX_PS_BUFFERS]) { int i; - union e1000_rx_desc_packet_split *d =3D - (union e1000_rx_desc_packet_split *) desc; =20 for (i =3D 0; i < MAX_PS_BUFFERS; i++) { - (*buff_addr)[i] =3D le64_to_cpu(d->read.buffer_addr[i]); + (*buff_addr)[i] =3D le64_to_cpu(desc->read.buffer_addr[i]); } =20 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1], @@ -1083,17 +1088,17 @@ e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *= desc, } =20 static inline void -e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc, +e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, hwaddr (*buff_addr)[MAX_PS_BUFFERS]) { if (e1000e_rx_use_legacy_descriptor(core)) { - e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]); + e1000e_read_lgcy_rx_descr(core, &desc->legacy, &(*buff_addr)[0]); (*buff_addr)[1] =3D (*buff_addr)[2] =3D (*buff_addr)[3] =3D 0; } else { if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { - e1000e_read_ps_rx_descr(core, desc, buff_addr); + e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); } else { - e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]); + e1000e_read_ext_rx_descr(core, &desc->extended, &(*buff_addr)[= 0]); (*buff_addr)[1] =3D (*buff_addr)[2] =3D (*buff_addr)[3] =3D 0; } } @@ -1264,7 +1269,7 @@ func_exit: } =20 static inline void -e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, +e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length) @@ -1272,71 +1277,66 @@ e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_= t *desc, uint32_t status_flags, rss, mrq; uint16_t ip_id; =20 - struct e1000_rx_desc *d =3D (struct e1000_rx_desc *) desc; - assert(!rss_info->enabled); =20 - d->length =3D cpu_to_le16(length); - d->csum =3D 0; + desc->length =3D cpu_to_le16(length); + desc->csum =3D 0; =20 e1000e_build_rx_metadata(core, pkt, pkt !=3D NULL, rss_info, &rss, &mrq, &status_flags, &ip_id, - &d->special); - d->errors =3D (uint8_t) (le32_to_cpu(status_flags) >> 24); - d->status =3D (uint8_t) le32_to_cpu(status_flags); + &desc->special); + desc->errors =3D (uint8_t) (le32_to_cpu(status_flags) >> 24); + desc->status =3D (uint8_t) le32_to_cpu(status_flags); } =20 static inline void -e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc, +e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *= desc, struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length) { - union e1000_rx_desc_extended *d =3D (union e1000_rx_desc_extended *) d= esc; - - memset(&d->wb, 0, sizeof(d->wb)); + memset(&desc->wb, 0, sizeof(desc->wb)); =20 - d->wb.upper.length =3D cpu_to_le16(length); + desc->wb.upper.length =3D cpu_to_le16(length); =20 e1000e_build_rx_metadata(core, pkt, pkt !=3D NULL, rss_info, - &d->wb.lower.hi_dword.rss, - &d->wb.lower.mrq, - &d->wb.upper.status_error, - &d->wb.lower.hi_dword.csum_ip.ip_id, - &d->wb.upper.vlan); + &desc->wb.lower.hi_dword.rss, + &desc->wb.lower.mrq, + &desc->wb.upper.status_error, + &desc->wb.lower.hi_dword.csum_ip.ip_id, + &desc->wb.upper.vlan); } =20 static inline void -e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc, +e1000e_write_ps_rx_descr(E1000ECore *core, + union e1000_rx_desc_packet_split *desc, struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) { int i; - union e1000_rx_desc_packet_split *d =3D - (union e1000_rx_desc_packet_split *) desc; =20 - memset(&d->wb, 0, sizeof(d->wb)); + memset(&desc->wb, 0, sizeof(desc->wb)); =20 - d->wb.middle.length0 =3D cpu_to_le16((*written)[0]); + desc->wb.middle.length0 =3D cpu_to_le16((*written)[0]); =20 for (i =3D 0; i < PS_PAGE_BUFFERS; i++) { - d->wb.upper.length[i] =3D cpu_to_le16((*written)[i + 1]); + desc->wb.upper.length[i] =3D cpu_to_le16((*written)[i + 1]); } =20 e1000e_build_rx_metadata(core, pkt, pkt !=3D NULL, rss_info, - &d->wb.lower.hi_dword.rss, - &d->wb.lower.mrq, - &d->wb.middle.status_error, - &d->wb.lower.hi_dword.csum_ip.ip_id, - &d->wb.middle.vlan); + &desc->wb.lower.hi_dword.rss, + &desc->wb.lower.mrq, + &desc->wb.middle.status_error, + &desc->wb.lower.hi_dword.csum_ip.ip_id, + &desc->wb.middle.vlan); =20 - d->wb.upper.header_status =3D + desc->wb.upper.header_status =3D cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP := 0)); =20 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], @@ -1344,20 +1344,21 @@ e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t = *desc, } =20 static inline void -e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc, +e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) { if (e1000e_rx_use_legacy_descriptor(core)) { assert(ps_hdr_len =3D=3D 0); - e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0= ]); + e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, + (*written)[0]); } else { if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { - e1000e_write_ps_rx_descr(core, desc, pkt, rss_info, + e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_i= nfo, ps_hdr_len, written); } else { assert(ps_hdr_len =3D=3D 0); - e1000e_write_ext_rx_descr(core, desc, pkt, rss_info, + e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, (*written)[0]); } } @@ -1365,12 +1366,12 @@ struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_inf= o, =20 static inline void e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, - uint8_t *desc, dma_addr_t len) + union e1000_rx_desc_union *desc, dma_addr_t l= en) { PCIDevice *dev =3D core->owner; =20 if (e1000e_rx_use_legacy_descriptor(core)) { - struct e1000_rx_desc *d =3D (struct e1000_rx_desc *) desc; + struct e1000_rx_desc *d =3D &desc->legacy; size_t offset =3D offsetof(struct e1000_rx_desc, status); uint8_t status =3D d->status; =20 @@ -1383,8 +1384,7 @@ e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_ad= dr_t addr, } } else { if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { - union e1000_rx_desc_packet_split *d =3D - (union e1000_rx_desc_packet_split *) desc; + union e1000_rx_desc_packet_split *d =3D &desc->packet_split; size_t offset =3D offsetof(union e1000_rx_desc_packet_split, wb.middle.status_error); uint32_t status =3D d->wb.middle.status_error; @@ -1397,8 +1397,7 @@ e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_ad= dr_t addr, pci_dma_write(dev, addr + offset, &status, sizeof(status)); } } else { - union e1000_rx_desc_extended *d =3D - (union e1000_rx_desc_extended *) desc; + union e1000_rx_desc_extended *d =3D &desc->extended; size_t offset =3D offsetof(union e1000_rx_desc_extended, wb.upper.status_error); uint32_t status =3D d->wb.upper.status_error; @@ -1542,7 +1541,7 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct= NetRxPkt *pkt, { PCIDevice *d =3D core->owner; dma_addr_t base; - uint8_t desc[E1000_MAX_RX_DESC_LEN]; + union e1000_rx_desc_union desc; size_t desc_size; size_t desc_offset =3D 0; size_t iov_ofs =3D 0; @@ -1578,7 +1577,7 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct= NetRxPkt *pkt, =20 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); =20 - e1000e_read_rx_descr(core, desc, &ba); + e1000e_read_rx_descr(core, &desc, &ba); =20 if (ba[0]) { if (desc_offset < size) { @@ -1648,9 +1647,9 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct= NetRxPkt *pkt, is_last =3D true; } =20 - e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL, + e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, rss_info, do_ps ? ps_hdr_len : 0, &bastate.writ= ten); - e1000e_pci_dma_write_rx_desc(core, base, desc, core->rx_desc_len); + e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); =20 e1000e_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN); --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673669278; cv=none; d=zohomail.com; s=zohoarc; b=LAImszYcNKIITzusrMyOuN49zpJA/xtFEuaZU3Aq7BqGSBuWd77/oEh+41fVdqqSOAphu/K99a6jXTK1Zq6QMGMXmooUUIhvPDxBWTuR21iXDY6zegY5uXYryO9YOG8Chccr3Mq3xhGNOm6EAXXg/OmSHpsdKhQXz7ybFJvzk7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673669278; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1031; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669278645100001 This keeps Windows driver 12.18.9.23 from generating an event with ID 30. The description of the event is as follows: > Intel(R) 82574L Gigabit Network Connection > PROBLEM: The network adapter is configured for auto-negotiation but > the link partner is not. This may result in a duplex mismatch. > ACTION: Configure the link partner for auto-negotiation. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/e1000e_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index d8c17baf8f..736708407c 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -3426,7 +3426,7 @@ e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE= _SIZE] =3D { [MII_ANLPAR] =3D MII_ANLPAR_10 | MII_ANLPAR_10FD | MII_ANLPAR_TX | MII_ANLPAR_TXFD | MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, - [MII_ANER] =3D MII_ANER_NP, + [MII_ANER] =3D MII_ANER_NP | MII_ANER_NWAY, [MII_ANNP] =3D 1 | MII_ANNP_MP, [MII_CTRL1000] =3D MII_CTRL1000_HALF | MII_CTRL1000_FULL | MII_CTRL1000_PORT | MII_CTRL1000_MASTER, --=20 2.39.0 From nobody Sat May 4 20:21:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 13 Jan 2023 20:00:32 -0800 (PST) From: Akihiko Odaki To: Cc: Jason Wang , Dmitry Fleytman , Thomas Huth , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki Subject: [PATCH 17/19] e1000e: Remove extra pointer indirection Date: Sat, 14 Jan 2023 12:59:17 +0900 Message-Id: <20230114035919.35251-18-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230114035919.35251-1-akihiko.odaki@daynix.com> References: <20230114035919.35251-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1032; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673670494606100001 Content-Type: text/plain; charset="utf-8" e1000e_write_packet_to_guest() passes the reference of variable ba as a pointer to an array, and that pointer indirection is just unnecessary; all functions which uses the passed reference performs no pointer operation on the pointer and they simply dereference the passed pointer. Remove the extra pointer indirection. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/e1000e_core.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 736708407c..d143f2ae6f 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -1075,31 +1075,31 @@ e1000e_read_ext_rx_descr(E1000ECore *core, union e1= 000_rx_desc_extended *desc, static inline void e1000e_read_ps_rx_descr(E1000ECore *core, union e1000_rx_desc_packet_split *desc, - hwaddr (*buff_addr)[MAX_PS_BUFFERS]) + hwaddr buff_addr[MAX_PS_BUFFERS]) { int i; =20 for (i =3D 0; i < MAX_PS_BUFFERS; i++) { - (*buff_addr)[i] =3D le64_to_cpu(desc->read.buffer_addr[i]); + buff_addr[i] =3D le64_to_cpu(desc->read.buffer_addr[i]); } =20 - trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1], - (*buff_addr)[2], (*buff_addr)[3]); + trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], + buff_addr[2], buff_addr[3]); } =20 static inline void e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, - hwaddr (*buff_addr)[MAX_PS_BUFFERS]) + hwaddr buff_addr[MAX_PS_BUFFERS]) { if (e1000e_rx_use_legacy_descriptor(core)) { - e1000e_read_lgcy_rx_descr(core, &desc->legacy, &(*buff_addr)[0]); - (*buff_addr)[1] =3D (*buff_addr)[2] =3D (*buff_addr)[3] =3D 0; + e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); + buff_addr[1] =3D buff_addr[2] =3D buff_addr[3] =3D 0; } else { if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); } else { - e1000e_read_ext_rx_descr(core, &desc->extended, &(*buff_addr)[= 0]); - (*buff_addr)[1] =3D (*buff_addr)[2] =3D (*buff_addr)[3] =3D 0; + e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); + buff_addr[1] =3D buff_addr[2] =3D buff_addr[3] =3D 0; } } } @@ -1420,14 +1420,14 @@ typedef struct e1000e_ba_state_st { =20 static inline void e1000e_write_hdr_to_rx_buffers(E1000ECore *core, - hwaddr (*ba)[MAX_PS_BUFFERS], + hwaddr ba[MAX_PS_BUFFERS], e1000e_ba_state *bastate, const char *data, dma_addr_t data_len) { assert(data_len <=3D core->rxbuf_sizes[0] - bastate->written[0]); =20 - pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_= len); + pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len= ); bastate->written[0] +=3D data_len; =20 bastate->cur_idx =3D 1; @@ -1435,7 +1435,7 @@ e1000e_write_hdr_to_rx_buffers(E1000ECore *core, =20 static void e1000e_write_to_rx_buffers(E1000ECore *core, - hwaddr (*ba)[MAX_PS_BUFFERS], + hwaddr ba[MAX_PS_BUFFERS], e1000e_ba_state *bastate, const char *data, dma_addr_t data_len) @@ -1447,13 +1447,13 @@ e1000e_write_to_rx_buffers(E1000ECore *core, uint32_t bytes_to_write =3D MIN(data_len, cur_buf_bytes_left); =20 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, - (*ba)[bastate->cur_idx], + ba[bastate->cur_idx], bastate->written[bastate->cur_idx], data, bytes_to_write); =20 pci_dma_write(core->owner, - (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx], + ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], data, bytes_to_write); =20 bastate->written[bastate->cur_idx] +=3D bytes_to_write; @@ -1577,7 +1577,7 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct= NetRxPkt *pkt, =20 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); =20 - e1000e_read_rx_descr(core, &desc, &ba); + e1000e_read_rx_descr(core, &desc, ba); =20 if (ba[0]) { if (desc_offset < size) { @@ -1596,7 +1596,7 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct= NetRxPkt *pkt, iov_copy =3D MIN(ps_hdr_len - ps_hdr_copied, iov->iov_len - iov_ofs); =20 - e1000e_write_hdr_to_rx_buffers(core, &ba, &bas= tate, + e1000e_write_hdr_to_rx_buffers(core, ba, &bast= ate, iov->iov_base, iov_c= opy); =20 copy_size -=3D iov_copy; @@ -1613,7 +1613,7 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct= NetRxPkt *pkt, } else { /* Leave buffer 0 of each descriptor except first = */ /* empty as per spec 7.1.5.1 = */ - e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate, + e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, NULL, 0); } } @@ -1622,7 +1622,7 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct= NetRxPkt *pkt, while (copy_size) { iov_copy =3D MIN(copy_size, iov->iov_len - iov_ofs); =20 - e1000e_write_to_rx_buffers(core, &ba, &bastate, + e1000e_write_to_rx_buffers(core, ba, &bastate, iov->iov_base + iov_ofs, iov_c= opy); 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Correct the code style before that. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tests/qtest/e1000e-test.c | 2 +- tests/qtest/libqos/e1000e.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c index 3fc92046be..b63a4d3c91 100644 --- a/tests/qtest/e1000e-test.c +++ b/tests/qtest/e1000e-test.c @@ -1,4 +1,4 @@ - /* +/* * QTest testcase for e1000e NIC * * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c index 37c794b130..b90eb2d5e0 100644 --- a/tests/qtest/libqos/e1000e.c +++ b/tests/qtest/libqos/e1000e.c @@ -222,8 +222,10 @@ static void e1000e_register_nodes(void) .device_id =3D E1000_DEV_ID_82574L, }; =20 - /* FIXME: every test using this node needs to setup a -netdev socket,i= d=3Dhs0 - * otherwise QEMU is not going to start */ + /* + * FIXME: every test using this node needs to setup a -netdev socket,i= d=3Dhs0 + * otherwise QEMU is not going to start + */ QOSGraphEdgeOptions opts =3D { .extra_device_opts =3D "netdev=3Dhs0", }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102d; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673669109770100001 The register definitions in tests/qtest/libqos/e1000e.h had names different from hw/net/e1000_regs.h, which made it hard to understand what test codes corresponds to the implementation. Use hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove these duplications. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tests/qtest/libqos/e1000e.c | 20 ++++++++++---------- tests/qtest/libqos/e1000e.h | 5 ----- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c index b90eb2d5e0..28fb3052aa 100644 --- a/tests/qtest/libqos/e1000e.c +++ b/tests/qtest/libqos/e1000e.c @@ -51,13 +51,13 @@ static uint32_t e1000e_macreg_read(QE1000E *d, uint32_t= reg) void e1000e_tx_ring_push(QE1000E *d, void *descr) { QE1000E_PCI *d_pci =3D container_of(d, QE1000E_PCI, e1000e); - uint32_t tail =3D e1000e_macreg_read(d, E1000E_TDT); - uint32_t len =3D e1000e_macreg_read(d, E1000E_TDLEN) / E1000_RING_DESC= _LEN; + uint32_t tail =3D e1000e_macreg_read(d, E1000_TDT); + uint32_t len =3D e1000e_macreg_read(d, E1000_TDLEN) / E1000_RING_DESC_= LEN; =20 qtest_memwrite(d_pci->pci_dev.bus->qts, d->tx_ring + tail * E1000_RING_DESC_LEN, descr, E1000_RING_DESC_LEN); - e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len); + e1000e_macreg_write(d, E1000_TDT, (tail + 1) % len); =20 /* Read WB data for the packet transmitted */ qtest_memread(d_pci->pci_dev.bus->qts, @@ -68,13 +68,13 @@ void e1000e_tx_ring_push(QE1000E *d, void *descr) void e1000e_rx_ring_push(QE1000E *d, void *descr) { QE1000E_PCI *d_pci =3D container_of(d, QE1000E_PCI, e1000e); - uint32_t tail =3D e1000e_macreg_read(d, E1000E_RDT); - uint32_t len =3D e1000e_macreg_read(d, E1000E_RDLEN) / E1000_RING_DESC= _LEN; + uint32_t tail =3D e1000e_macreg_read(d, E1000_RDT); + uint32_t len =3D e1000e_macreg_read(d, E1000_RDLEN) / E1000_RING_DESC_= LEN; =20 qtest_memwrite(d_pci->pci_dev.bus->qts, d->rx_ring + tail * E1000_RING_DESC_LEN, descr, E1000_RING_DESC_LEN); - e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len); + e1000e_macreg_write(d, E1000_RDT, (tail + 1) % len); =20 /* Read WB data for the packet received */ qtest_memread(d_pci->pci_dev.bus->qts, @@ -145,8 +145,8 @@ static void e1000e_pci_start_hw(QOSGraphObject *obj) (uint32_t) d->e1000e.tx_ring); e1000e_macreg_write(&d->e1000e, E1000_TDBAH, (uint32_t) (d->e1000e.tx_ring >> 32)); - e1000e_macreg_write(&d->e1000e, E1000E_TDLEN, E1000E_RING_LEN); - e1000e_macreg_write(&d->e1000e, E1000E_TDT, 0); + e1000e_macreg_write(&d->e1000e, E1000_TDLEN, E1000E_RING_LEN); + e1000e_macreg_write(&d->e1000e, E1000_TDT, 0); e1000e_macreg_write(&d->e1000e, E1000_TDH, 0); =20 /* Enable transmit */ @@ -156,8 +156,8 @@ static void e1000e_pci_start_hw(QOSGraphObject *obj) (uint32_t)d->e1000e.rx_ring); e1000e_macreg_write(&d->e1000e, E1000_RDBAH, (uint32_t)(d->e1000e.rx_ring >> 32)); - e1000e_macreg_write(&d->e1000e, E1000E_RDLEN, E1000E_RING_LEN); - e1000e_macreg_write(&d->e1000e, E1000E_RDT, 0); + e1000e_macreg_write(&d->e1000e, E1000_RDLEN, E1000E_RING_LEN); + e1000e_macreg_write(&d->e1000e, E1000_RDT, 0); e1000e_macreg_write(&d->e1000e, E1000_RDH, 0); =20 /* Enable receive */ diff --git a/tests/qtest/libqos/e1000e.h b/tests/qtest/libqos/e1000e.h index 3bf285af42..091ce139da 100644 --- a/tests/qtest/libqos/e1000e.h +++ b/tests/qtest/libqos/e1000e.h @@ -25,11 +25,6 @@ #define E1000E_RX0_MSG_ID (0) #define E1000E_TX0_MSG_ID (1) =20 -#define E1000E_TDLEN (0x3808) -#define E1000E_TDT (0x3818) -#define E1000E_RDLEN (0x2808) -#define E1000E_RDT (0x2818) - typedef struct QE1000E QE1000E; typedef struct QE1000E_PCI QE1000E_PCI; =20 --=20 2.39.0