[PATCH v2] include/hw/riscv/opentitan: update opentitan IRQs

Wilfred Mallawa posted 1 patch 2 weeks, 2 days ago
hw/riscv/opentitan.c         | 80 ++++++++++++++++++------------------
include/hw/riscv/opentitan.h | 14 +++----
2 files changed, 47 insertions(+), 47 deletions(-)
[PATCH v2] include/hw/riscv/opentitan: update opentitan IRQs
Posted by Wilfred Mallawa 2 weeks, 2 days ago
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.

OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47

Memory layout as per [1]

[1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
Changes in v2:
	- Updated the MMIO register layout/size
	- Bumped the supported commit sha
	- Added link to OT register layout for reference in the commit
	  msg

 hw/riscv/opentitan.c         | 80 ++++++++++++++++++------------------
 include/hw/riscv/opentitan.h | 14 +++----
 2 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 64d5d435b9..353f030d80 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -31,47 +31,47 @@
 /*
  * This version of the OpenTitan machine currently supports
  * OpenTitan RTL version:
- * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
+ * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
  *
  * MMIO mapping as per (specified commit):
  * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
  */
 static const MemMapEntry ibex_memmap[] = {
-    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000 },
-    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
-    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
-    [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
-    [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
-    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
-    [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
-    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
-    [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
-    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
-    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
-    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x1000  },
-    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
-    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
-    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000  },
-    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
-    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
-    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
-    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
-    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x1000  },
-    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
-    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
-    [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
-    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
-    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
-    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
-    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
-    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
-    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
-    [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
-    [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
-    [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
-    [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
-    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000 },
-    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
+    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000      },
+    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000     },
+    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000    },
+    [IBEX_DEV_UART] =           {  0x40000000,  0x40        },
+    [IBEX_DEV_GPIO] =           {  0x40040000,  0x40        },
+    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x2000      },
+    [IBEX_DEV_I2C] =            {  0x40080000,  0x80        },
+    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x40        },
+    [IBEX_DEV_TIMER] =          {  0x40100000,  0x200       },
+    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x2000      },
+    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x100       },
+    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x800       },
+    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x40        },
+    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x40        },
+    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000      },
+    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x80        },
+    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x80        },
+    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x80        },
+    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000      },
+    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x40        },
+    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x40        },
+    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x200       },
+    [IBEX_DEV_AES] =            {  0x41100000,  0x100       },
+    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000      },
+    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000      },
+    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000     },
+    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x100       },
+    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x80        },
+    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x100       },
+    [IBEX_DEV_EDNO] =           {  0x41170000,  0x80        },
+    [IBEX_DEV_EDN1] =           {  0x41180000,  0x80        },
+    [IBEX_DEV_SRAM_CTRL] =      {  0x411c0000,  0x20        },
+    [IBEX_DEV_IBEX_CFG] =       {  0x411f0000,  0x100       },
+    [IBEX_DEV_PLIC] =           {  0x48000000,  0x8000000   },
+    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000     },
 };
 
 static void opentitan_board_init(MachineState *machine)
@@ -294,12 +294,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
         memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
     create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
         memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
-    create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
-        memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
+    create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
+        memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
     create_unimplemented_device("riscv.lowrisc.ibex.otbn",
         memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
-    create_unimplemented_device("riscv.lowrisc.ibex.peri",
-        memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
+    create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
+        memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
 }
 
 static Property lowrisc_ibex_soc_props[] = {
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 7659d1bc5b..c40b05052a 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -94,9 +94,9 @@ enum {
     IBEX_DEV_EDNO,
     IBEX_DEV_EDN1,
     IBEX_DEV_ALERT_HANDLER,
-    IBEX_DEV_NMI_GEN,
+    IBEX_DEV_SRAM_CTRL,
     IBEX_DEV_OTBN,
-    IBEX_DEV_PERI,
+    IBEX_DEV_IBEX_CFG,
 };
 
 enum {
@@ -108,11 +108,11 @@ enum {
     IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
     IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
     IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
-    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
-    IBEX_SPI_HOST0_ERR_IRQ        = 134,
-    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
-    IBEX_SPI_HOST1_ERR_IRQ        = 136,
-    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
+    IBEX_TIMER_TIMEREXPIRED0_0    = 124,
+    IBEX_SPI_HOST0_ERR_IRQ        = 131,
+    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 132,
+    IBEX_SPI_HOST1_ERR_IRQ        = 133,
+    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 134,
 };
 
 #endif
-- 
2.39.1
Re: [PATCH v2] include/hw/riscv/opentitan: update opentitan IRQs
Posted by Alistair Francis 2 weeks, 2 days ago
On Mon, Jan 23, 2023 at 4:40 PM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> Updates the opentitan IRQs to match the latest supported commit of
> Opentitan from TockOS.
>
> OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
>
> Memory layout as per [1]
>
> [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
> Changes in v2:
>         - Updated the MMIO register layout/size
>         - Bumped the supported commit sha
>         - Added link to OT register layout for reference in the commit
>           msg
>
>  hw/riscv/opentitan.c         | 80 ++++++++++++++++++------------------
>  include/hw/riscv/opentitan.h | 14 +++----
>  2 files changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 64d5d435b9..353f030d80 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -31,47 +31,47 @@
>  /*
>   * This version of the OpenTitan machine currently supports
>   * OpenTitan RTL version:
> - * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
> + * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
>   *
>   * MMIO mapping as per (specified commit):
>   * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
>   */
>  static const MemMapEntry ibex_memmap[] = {
> -    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000 },
> -    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
> -    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
> -    [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
> -    [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
> -    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
> -    [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
> -    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
> -    [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
> -    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
> -    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
> -    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x1000  },
> -    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
> -    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
> -    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000  },
> -    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
> -    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
> -    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
> -    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
> -    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x1000  },
> -    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
> -    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
> -    [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
> -    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
> -    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
> -    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
> -    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
> -    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
> -    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
> -    [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
> -    [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
> -    [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
> -    [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
> -    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000 },
> -    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
> +    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000      },
> +    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000     },
> +    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000    },
> +    [IBEX_DEV_UART] =           {  0x40000000,  0x40        },
> +    [IBEX_DEV_GPIO] =           {  0x40040000,  0x40        },
> +    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x2000      },
> +    [IBEX_DEV_I2C] =            {  0x40080000,  0x80        },
> +    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x40        },
> +    [IBEX_DEV_TIMER] =          {  0x40100000,  0x200       },
> +    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x2000      },
> +    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x100       },
> +    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x800       },
> +    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x40        },
> +    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x40        },
> +    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000      },
> +    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x80        },
> +    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x80        },
> +    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x80        },
> +    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000      },
> +    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x40        },
> +    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x40        },
> +    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x200       },
> +    [IBEX_DEV_AES] =            {  0x41100000,  0x100       },
> +    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000      },
> +    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000      },
> +    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000     },
> +    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x100       },
> +    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x80        },
> +    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x100       },
> +    [IBEX_DEV_EDNO] =           {  0x41170000,  0x80        },
> +    [IBEX_DEV_EDN1] =           {  0x41180000,  0x80        },
> +    [IBEX_DEV_SRAM_CTRL] =      {  0x411c0000,  0x20        },
> +    [IBEX_DEV_IBEX_CFG] =       {  0x411f0000,  0x100       },
> +    [IBEX_DEV_PLIC] =           {  0x48000000,  0x8000000   },
> +    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000     },
>  };
>
>  static void opentitan_board_init(MachineState *machine)
> @@ -294,12 +294,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>          memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
>          memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
> -    create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
> -        memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
> +    create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
> +        memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.otbn",
>          memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
> -    create_unimplemented_device("riscv.lowrisc.ibex.peri",
> -        memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
> +    create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
> +        memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
>  }
>
>  static Property lowrisc_ibex_soc_props[] = {
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 7659d1bc5b..c40b05052a 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -94,9 +94,9 @@ enum {
>      IBEX_DEV_EDNO,
>      IBEX_DEV_EDN1,
>      IBEX_DEV_ALERT_HANDLER,
> -    IBEX_DEV_NMI_GEN,
> +    IBEX_DEV_SRAM_CTRL,
>      IBEX_DEV_OTBN,
> -    IBEX_DEV_PERI,
> +    IBEX_DEV_IBEX_CFG,
>  };
>
>  enum {
> @@ -108,11 +108,11 @@ enum {
>      IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
>      IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
>      IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
> -    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
> -    IBEX_SPI_HOST0_ERR_IRQ        = 134,
> -    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
> -    IBEX_SPI_HOST1_ERR_IRQ        = 136,
> -    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
> +    IBEX_TIMER_TIMEREXPIRED0_0    = 124,
> +    IBEX_SPI_HOST0_ERR_IRQ        = 131,
> +    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 132,
> +    IBEX_SPI_HOST1_ERR_IRQ        = 133,
> +    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 134,
>  };
>
>  #endif
> --
> 2.39.1
>
>
Re: [PATCH v2] include/hw/riscv/opentitan: update opentitan IRQs
Posted by Alistair Francis 2 weeks, 2 days ago
On Mon, Jan 23, 2023 at 4:40 PM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> Updates the opentitan IRQs to match the latest supported commit of
> Opentitan from TockOS.
>
> OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
>
> Memory layout as per [1]
>
> [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
> Changes in v2:
>         - Updated the MMIO register layout/size
>         - Bumped the supported commit sha
>         - Added link to OT register layout for reference in the commit
>           msg
>
>  hw/riscv/opentitan.c         | 80 ++++++++++++++++++------------------
>  include/hw/riscv/opentitan.h | 14 +++----
>  2 files changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 64d5d435b9..353f030d80 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -31,47 +31,47 @@
>  /*
>   * This version of the OpenTitan machine currently supports
>   * OpenTitan RTL version:
> - * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
> + * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
>   *
>   * MMIO mapping as per (specified commit):
>   * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
>   */
>  static const MemMapEntry ibex_memmap[] = {
> -    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000 },
> -    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
> -    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
> -    [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
> -    [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
> -    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
> -    [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
> -    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
> -    [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
> -    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
> -    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
> -    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x1000  },
> -    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
> -    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
> -    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000  },
> -    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
> -    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
> -    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
> -    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
> -    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x1000  },
> -    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
> -    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
> -    [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
> -    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
> -    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
> -    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
> -    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
> -    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
> -    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
> -    [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
> -    [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
> -    [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
> -    [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
> -    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000 },
> -    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
> +    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000      },
> +    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000     },
> +    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000    },
> +    [IBEX_DEV_UART] =           {  0x40000000,  0x40        },
> +    [IBEX_DEV_GPIO] =           {  0x40040000,  0x40        },
> +    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x2000      },
> +    [IBEX_DEV_I2C] =            {  0x40080000,  0x80        },
> +    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x40        },
> +    [IBEX_DEV_TIMER] =          {  0x40100000,  0x200       },
> +    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x2000      },
> +    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x100       },
> +    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x800       },
> +    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x40        },
> +    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x40        },
> +    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000      },
> +    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x80        },
> +    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x80        },
> +    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x80        },
> +    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000      },
> +    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x40        },
> +    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x40        },
> +    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x200       },
> +    [IBEX_DEV_AES] =            {  0x41100000,  0x100       },
> +    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000      },
> +    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000      },
> +    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000     },
> +    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x100       },
> +    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x80        },
> +    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x100       },
> +    [IBEX_DEV_EDNO] =           {  0x41170000,  0x80        },
> +    [IBEX_DEV_EDN1] =           {  0x41180000,  0x80        },
> +    [IBEX_DEV_SRAM_CTRL] =      {  0x411c0000,  0x20        },
> +    [IBEX_DEV_IBEX_CFG] =       {  0x411f0000,  0x100       },
> +    [IBEX_DEV_PLIC] =           {  0x48000000,  0x8000000   },
> +    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000     },
>  };
>
>  static void opentitan_board_init(MachineState *machine)
> @@ -294,12 +294,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>          memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
>          memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
> -    create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
> -        memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
> +    create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
> +        memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.otbn",
>          memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
> -    create_unimplemented_device("riscv.lowrisc.ibex.peri",
> -        memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
> +    create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
> +        memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
>  }
>
>  static Property lowrisc_ibex_soc_props[] = {
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 7659d1bc5b..c40b05052a 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -94,9 +94,9 @@ enum {
>      IBEX_DEV_EDNO,
>      IBEX_DEV_EDN1,
>      IBEX_DEV_ALERT_HANDLER,
> -    IBEX_DEV_NMI_GEN,
> +    IBEX_DEV_SRAM_CTRL,
>      IBEX_DEV_OTBN,
> -    IBEX_DEV_PERI,
> +    IBEX_DEV_IBEX_CFG,
>  };
>
>  enum {
> @@ -108,11 +108,11 @@ enum {
>      IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
>      IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
>      IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
> -    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
> -    IBEX_SPI_HOST0_ERR_IRQ        = 134,
> -    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
> -    IBEX_SPI_HOST1_ERR_IRQ        = 136,
> -    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
> +    IBEX_TIMER_TIMEREXPIRED0_0    = 124,
> +    IBEX_SPI_HOST0_ERR_IRQ        = 131,
> +    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 132,
> +    IBEX_SPI_HOST1_ERR_IRQ        = 133,
> +    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 134,
>  };
>
>  #endif
> --
> 2.39.1
>
>