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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HLC1b+miMYKSFpzmpb6sjN/lCOjEj7YzmRL1GMfHWWQ=; b=va0D7Jo3HJRLKp7iICozOQigBIOgZRTIFMFFeG9lisAzsWlinksVjz7mmXIMXvlc8R aplebvAWzoNq5Soc4bU0qn3Jyi0Xcx1NOoE4E9E4Hb5V4jbv0RfE0uA9uc2BTraAC/4n ROJbbDFHY8W0gYYnqcqd6RaFPZxHg+qbsAAK7rwQHzOUb/g9zP4a80ZQ71S53C3/vxf3 S2CTTgWLyLAB8RoCBTTDgkH8STKWX/8FyHnIXugw2WgWEtbPPxLFG3Vwc1IFR9G7HIex ZyNSwNaR6Khi9mMZOusAHbwJLKtwF01K/LZZjJKyW5kTFFHdZ+MTi8Xohc3jd6MXWwoC 8MsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HLC1b+miMYKSFpzmpb6sjN/lCOjEj7YzmRL1GMfHWWQ=; b=C1OGrOBC6bZfu9gOtR4ggJOKkzOQR7x2xC9NLyrQEKMkqGSPWUECkMMDcrhXfq4ks0 T84klhYwLjhwbS1pYhzSkofXDxUZV5ipNyuH7NTbggzk81Qs7HqoPbNP5S/+jBO6YBWs rxI6TjjWWi2WYQwpo1+KC+BDqCUmZgNaFmDnsMxFIxOIhevUmHEXmZxHmmvr1Vqu2/9/ D7apAyOgbxdEoEQ8/Rj1wWLh3vKL9vdqifjeE1MWybViq5dL0wiAZ0Dql43EZZzqvzVy DTzwICqI4AK/2BMaxSp22iq7LOljZBmcAOK1FJvX9DYilMn13qWLrxO8IMzkjfolL46a yoMQ== X-Gm-Message-State: AFqh2kr3UtnooqB+K5UZijEQVk1ZP0KLP3gfzTEFjZ8SA7Pd1jNTUB4q j3c2nQ2Wx5lxZYAH9CdCY95auRoiRGfbPDxP X-Google-Smtp-Source: AMrXdXtJ2spXVYATb077xOO9IFKJerxx+cWgK8zeAjvi3Nzfd0gtmgfF7+gT9UrjYQAFA8Ji5XZ9CQ== X-Received: by 2002:a05:6a00:438d:b0:589:8fac:cfe5 with SMTP id bt13-20020a056a00438d00b005898faccfe5mr26236608pfb.13.1674518474227; Mon, 23 Jan 2023 16:01:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 16/22] target/arm: Move s1_is_El0 into S1Translate Date: Mon, 23 Jan 2023 14:00:21 -1000 Message-Id: <20230124000027.3565716-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518546070100007 Content-Type: text/plain; charset="utf-8" Instead of passing this to get_phys_addr_lpae, stash it in the S1Translate structure. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 37f5ff220c..eaa47f6b62 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -22,6 +22,7 @@ typedef struct S1Translate { ARMSecuritySpace in_space; bool in_secure; bool in_debug; + bool in_s1_is_el0; bool out_secure; bool out_rw; bool out_be; @@ -33,7 +34,7 @@ typedef struct S1Translate { =20 static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 @@ -1257,17 +1258,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_= aa64, uint64_t tcr, * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH - * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2 - * (so this is a stage 2 page table walk), - * must be true if this is stage 2 of a stage 1+2 - * walk for an EL0 access. If @mmu_idx is anything else, - * @s1_is_el0 is ignored. * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); @@ -1596,7 +1592,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.prot =3D get_S2prot_noexecute(ap); } else { xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } } else { int ns =3D extract32(attrs, 5, 1); @@ -2819,7 +2815,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMSecuritySpace ipa_space, s2walk_space; - bool is_el0; uint64_t hcr; =20 ret =3D get_phys_addr_with_struct(env, ptw, address, access_type, resu= lt, fi); @@ -2844,7 +2839,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, s2walk_space =3D ipa_space; } =20 - is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; + ptw->in_s1_is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; ptw->in_ptw_idx =3D arm_space_to_phys(s2walk_space); ptw->in_secure =3D s2walk_secure; @@ -2863,8 +2858,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, ret =3D get_phys_addr_pmsav8(env, ipa, access_type, ptw->in_mmu_idx, s2walk_secure, result,= fi); } else { - ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, - is_el0, result, fi); + ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); } fi->s2addr =3D ipa; =20 @@ -3040,8 +3034,7 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, false, - result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, result, = fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi= ); --=20 2.34.1