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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id fh3-20020a17090b034300b00228e56d375asm283936pjb.33.2023.01.23.18.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 18:05:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rc/VY8rBEtL52bTFD8m38qtzf0giQYh7S+uKXuCEagE=; b=YnYPKSM5BFp/9AYH91jaXQWlpcQzaxJqbXOaOzI20HWx9ESqeYhMEJhKZtQY9bE9DN czgFCHCv1I1WXhqXqc0685fopdUleB1eiJl2R7zuG56RW0TKAbqQogr8d66CzACE4gt/ UbR1o4TcPqGuNqit1AXOPMNUv3MFmCj6kct3tLm2qc6pXzQBNeluFIFpEgdW3aQ5NdxG opOV1FwV0ebqoWGbpKNn9aAtLMqC6XZoFioTdC+PR3pV31CQNrJWPvipZy0hW+vy2EpQ Y7lpG1mRW6tMgUKsETPMpia04O3zV8kvaIihBMJCaBCuvJQWmeVo0THmtNSgNC+Hwf+5 k2HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rc/VY8rBEtL52bTFD8m38qtzf0giQYh7S+uKXuCEagE=; b=tKre7a2anc210iu/N6UOadnOq7h/ty2I+Kod0YJXl7veEOq1xdNjpFm5JOLX4/m2IX PmKjzEN/giN0zYngLpmwifPZUpTk0xB70nMd4wgC2Kyfivlk7mFKwVIvJD+ZW7eC6MDj S36koNkRWvnth4jwfRiZxgYg5olWFxc8z+jerrbAHDeku5k2bCtsCJ77kdYutOC2uX08 T3+1KpJKqEXgqnKpj44BlLKAzr2QkckHG91UmF2+ktn5/MxkziXfgpmLwe6rq6G4f09l tsSX11aUNek/hgaNtGjLl1ZsgFlEt1jTxwmM9EpZ+jc+1la5ApWZLRSeIW30/Ql58Khm kM9g== X-Gm-Message-State: AFqh2kq9ueCYhfCQ7XPGi4+A/8f7KgyWmqOBz9/QrfHx5paXB9aaYuT7 2jHHlQ/FQFxeLvQ848DpmWKPKZ7NjjUbuOS9 X-Google-Smtp-Source: AMrXdXv1NN9rAgMfXxEaxHOYuc2hg/x09IyIODH0GffhnNsD1Po+sk6M6VEk/tw2KrQZmWsPFNQQxg== X-Received: by 2002:a17:90a:a895:b0:229:d400:11c1 with SMTP id h21-20020a17090aa89500b00229d40011c1mr21364346pjq.10.1674525929219; Mon, 23 Jan 2023 18:05:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, WANG Xuerui Subject: [PULL v2 11/15] tcg/loongarch64: Introduce tcg_out_addi Date: Mon, 23 Jan 2023 16:05:03 -1000 Message-Id: <20230124020507.3732200-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124020507.3732200-1-richard.henderson@linaro.org> References: <20230124020507.3732200-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674526061070100001 Content-Type: text/plain; charset="utf-8" Adjust the constraints to allow any int32_t for immediate addition. Split immediate adds into addu16i + addi, which covers quite a lot of the immediate space. For the hole in the middle, load the constant into TMP0 instead. Reviewed-by: WANG Xuerui Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 4 +- tcg/loongarch64/tcg-target-con-str.h | 2 +- tcg/loongarch64/tcg-target.c.inc | 57 ++++++++++++++++++++++++---- 3 files changed, 53 insertions(+), 10 deletions(-) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-tar= get-con-set.h index 349c672687..7b5a7a3f5d 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -23,9 +23,11 @@ C_O1_I1(r, L) C_O1_I2(r, r, rC) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) +C_O1_I2(r, r, rJ) C_O1_I2(r, r, rU) C_O1_I2(r, r, rW) C_O1_I2(r, r, rZ) C_O1_I2(r, 0, rZ) -C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, ri) +C_O1_I2(r, rZ, rJ) C_O1_I2(r, rZ, rZ) diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-tar= get-con-str.h index c3986a4fd4..541ff47fa9 100644 --- a/tcg/loongarch64/tcg-target-con-str.h +++ b/tcg/loongarch64/tcg-target-con-str.h @@ -21,7 +21,7 @@ REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('I', TCG_CT_CONST_S12) -CONST('N', TCG_CT_CONST_N12) +CONST('J', TCG_CT_CONST_S32) CONST('U', TCG_CT_CONST_U12) CONST('Z', TCG_CT_CONST_ZERO) CONST('C', TCG_CT_CONST_C12) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 428f3abd71..8cc6c5eec2 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -126,7 +126,7 @@ static const int tcg_target_call_oarg_regs[] =3D { =20 #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 -#define TCG_CT_CONST_N12 0x400 +#define TCG_CT_CONST_S32 0x400 #define TCG_CT_CONST_U12 0x800 #define TCG_CT_CONST_C12 0x1000 #define TCG_CT_CONST_WSZ 0x2000 @@ -161,7 +161,7 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) if ((ct & TCG_CT_CONST_S12) && val =3D=3D sextreg(val, 0, 12)) { return true; } - if ((ct & TCG_CT_CONST_N12) && -val =3D=3D sextreg(-val, 0, 12)) { + if ((ct & TCG_CT_CONST_S32) && val =3D=3D (int32_t)val) { return true; } if ((ct & TCG_CT_CONST_U12) && val >=3D 0 && val <=3D 0xfff) { @@ -378,6 +378,45 @@ static void tcg_out_movi(TCGContext *s, TCGType type, = TCGReg rd, } } =20 +static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, + TCGReg rs, tcg_target_long imm) +{ + tcg_target_long lo12 =3D sextreg(imm, 0, 12); + tcg_target_long hi16 =3D sextreg(imm - lo12, 16, 16); + + /* + * Note that there's a hole in between hi16 and lo12: + * + * 3 2 1 0 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * ...+-------------------------------+-------+-----------------------+ + * | hi16 | | lo12 | + * ...+-------------------------------+-------+-----------------------+ + * + * For bits within that hole, it's more efficient to use LU12I and ADD. + */ + if (imm =3D=3D (hi16 << 16) + lo12) { + if (hi16) { + tcg_out_opc_addu16i_d(s, rd, rs, hi16); + rs =3D rd; + } + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_opc_addi_w(s, rd, rs, lo12); + } else if (lo12) { + tcg_out_opc_addi_d(s, rd, rs, lo12); + } else { + tcg_out_mov(s, type, rd, rs); + } + } else { + tcg_out_movi(s, type, TCG_REG_TMP0, imm); + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); + } else { + tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); + } + } +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_andi(s, ret, arg, 0xff); @@ -1350,14 +1389,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_add_i32: if (c2) { - tcg_out_opc_addi_w(s, a0, a1, a2); + tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2); } else { tcg_out_opc_add_w(s, a0, a1, a2); } break; case INDEX_op_add_i64: if (c2) { - tcg_out_opc_addi_d(s, a0, a1, a2); + tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2); } else { tcg_out_opc_add_d(s, a0, a1, a2); } @@ -1365,14 +1404,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_sub_i32: if (c2) { - tcg_out_opc_addi_w(s, a0, a1, -a2); + tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2); } else { tcg_out_opc_sub_w(s, a0, a1, a2); } break; case INDEX_op_sub_i64: if (c2) { - tcg_out_opc_addi_d(s, a0, a1, -a2); + tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2); } else { tcg_out_opc_sub_d(s, a0, a1, a2); } @@ -1586,8 +1625,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) return C_O1_I2(r, r, ri); =20 case INDEX_op_add_i32: + return C_O1_I2(r, r, ri); case INDEX_op_add_i64: - return C_O1_I2(r, r, rI); + return C_O1_I2(r, r, rJ); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: @@ -1616,8 +1656,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) return C_O1_I2(r, 0, rZ); =20 case INDEX_op_sub_i32: + return C_O1_I2(r, rZ, ri); case INDEX_op_sub_i64: - return C_O1_I2(r, rZ, rN); + return C_O1_I2(r, rZ, rJ); =20 case INDEX_op_mul_i32: case INDEX_op_mul_i64: --=20 2.34.1