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Wed, 25 Jan 2023 02:42:17 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 7C7CF5000B0; Tue, 24 Jan 2023 18:42:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=kOdObz2qBfqPOWC23iFZLydAEsWbKhc9/eCQPXsbTDM=; b=J6kUYasLm3z69JgZjYLWHHoOt2frHaKy/Mj5ceAYNJF7Qsa7NGOsPEuUPMGpCqxNEaxU wMg5ClU7yINl5Mqyy33cXC3/xfeDxVe/m3YLUL+KKVrhSpM4Ua44JbB6YFmHgWnXxP9A DIf1pvyrg7YO+KWThSd+0gHdB9/zaDIY8bOHlGKBJRNjiQEJT6EqiytjSGuCdG0R0veF 5TubHkaFlVOWtT4/HFvGBXjzY0kXo6fBlSzztVJbD28wq/rqdrDZOqdAHIgvFX2m4YFB Ssn4XYQG3x7VcjZ+FDiV/0DVJ+8+HIrFx2dEdGclmwgqoU6SQOSmxcAdmtV6fByMp/qB Zg== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v4 04/13] Hexagon (target/hexagon) Add overrides for dealloc-return instructions Date: Tue, 24 Jan 2023 18:42:06 -0800 Message-Id: <20230125024215.10430-5-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230125024215.10430-1-tsimpson@quicinc.com> References: <20230125024215.10430-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1674614665084100015 These instructions perform a deallocframe+return (jumpr r31) Add overrides for L4_return SL2_return L4_return_t L4_return_f L4_return_tnew_pt L4_return_fnew_pt L4_return_tnew_pnt L4_return_fnew_pnt SL2_return_t SL2_return_f SL2_return_tnew SL2_return_fnew This patch eliminates the last helper that uses write_new_pc, so we remove it from op_helper.c This patch also eliminates the last helper for load instructions, so we remove the pkt_has_store_s1 runtime field as well as the mem_load[1248] functions. Signed-off-by: Taylor Simpson --- target/hexagon/cpu.h | 3 +- target/hexagon/gen_tcg.h | 54 ++++++++++++++++++++++++ target/hexagon/genptr.c | 86 ++++++++++++++++++++++++++++++++++++++ target/hexagon/op_helper.c | 69 ------------------------------ target/hexagon/translate.c | 6 +-- 5 files changed, 142 insertions(+), 76 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 34c0ae0a67..8df5b5a236 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -98,7 +98,6 @@ typedef struct CPUArchState { target_ulong pred_written; =20 MemLog mem_log_stores[STORES_MAX]; - target_ulong pkt_has_store_s1; target_ulong dczero_addr; =20 float_status fp_status; diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 6267f51ccc..8282ff3fc5 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -508,6 +508,60 @@ #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN)) =20 +/* + * dealloc_return + * Assembler mapped to + * r31:30 =3D dealloc_return(r30):raw + */ +#define fGEN_TCG_L4_return(SHORTCODE) \ + gen_return(ctx, RddV, RsV) + +/* + * sub-instruction version (no RddV, so handle it manually) + */ +#define fGEN_TCG_SL2_return(SHORTCODE) \ + do { \ + TCGv_i64 RddV =3D tcg_temp_new_i64(); \ + gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \ + gen_log_reg_write_pair(HEX_REG_FP, RddV); \ + tcg_temp_free_i64(RddV); \ + } while (0) + +/* + * Conditional returns follow this naming convention + * _t predicate true + * _f predicate false + * _tnew_pt predicate.new true predict taken + * _fnew_pt predicate.new false predict taken + * _tnew_pnt predicate.new true predict not taken + * _fnew_pnt predicate.new false predict not taken + * Predictions are not modelled in QEMU + * + * Example: + * if (p1) r31:30 =3D dealloc_return(r30):raw + */ +#define fGEN_TCG_L4_return_t(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_EQ); +#define fGEN_TCG_L4_return_f(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_NE) +#define fGEN_TCG_L4_return_tnew_pt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ) +#define fGEN_TCG_L4_return_fnew_pt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE) +#define fGEN_TCG_L4_return_tnew_pnt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ) +#define fGEN_TCG_L4_return_fnew_pnt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE) + +#define fGEN_TCG_SL2_return_t(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_pred[0]) +#define fGEN_TCG_SL2_return_f(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_pred[0]) +#define fGEN_TCG_SL2_return_tnew(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_new_pred_value[0]) +#define fGEN_TCG_SL2_return_fnew(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_new_pred_value[0]) + /* * Mathematical operations with more than one definition require * special handling diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index e17ac93a59..efd36f760f 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -746,6 +746,92 @@ static void gen_cond_callr(DisasContext *ctx, gen_set_label(skip); } =20 +/* frame ^=3D (int64_t)FRAMEKEY << 32 */ +static void gen_frame_unscramble(TCGv_i64 frame) +{ + TCGv_i64 framekey =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(framekey, hex_gpr[HEX_REG_FRAMEKEY]); + tcg_gen_shli_i64(framekey, framekey, 32); + tcg_gen_xor_i64(frame, frame, framekey); + tcg_temp_free_i64(framekey); +} + +static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA) +{ + Insn *insn =3D ctx->insn; /* Needed for CHECK_NOSHUF */ + CHECK_NOSHUF(EA, 8); + tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx); +} + +static void gen_return_base(DisasContext *ctx, TCGv_i64 dst, TCGv src, + TCGv r29) +{ + /* + * frame =3D *src + * dst =3D frame_unscramble(frame) + * SP =3D src + 8 + * PC =3D dst.w[1] + */ + TCGv_i64 frame =3D tcg_temp_new_i64(); + TCGv r31 =3D tcg_temp_new(); + + gen_load_frame(ctx, frame, src); + gen_frame_unscramble(frame); + tcg_gen_mov_i64(dst, frame); + tcg_gen_addi_tl(r29, src, 8); + tcg_gen_extrh_i64_i32(r31, dst); + gen_jumpr(ctx, r31); + + tcg_temp_free_i64(frame); + tcg_temp_free(r31); +} + +static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src) +{ + TCGv r29 =3D tcg_temp_new(); + gen_return_base(ctx, dst, src, r29); + gen_log_reg_write(HEX_REG_SP, r29); + tcg_temp_free(r29); +} + +/* if (pred) dst =3D dealloc_return(src):raw */ +static void gen_cond_return(DisasContext *ctx, TCGv_i64 dst, TCGv src, + TCGv pred, TCGCond cond) +{ + TCGv LSB =3D tcg_temp_new(); + TCGv mask =3D tcg_temp_new(); + TCGv r29 =3D tcg_temp_local_new(); + TCGLabel *skip =3D gen_new_label(); + tcg_gen_andi_tl(LSB, pred, 1); + + /* Initialize the results in case the predicate is false */ + tcg_gen_movi_i64(dst, 0); + tcg_gen_movi_tl(r29, 0); + + /* Set the bit in hex_slot_cancelled if the predicate is flase */ + tcg_gen_movi_tl(mask, 1 << ctx->insn->slot); + tcg_gen_or_tl(mask, hex_slot_cancelled, mask); + tcg_gen_movcond_tl(cond, hex_slot_cancelled, LSB, tcg_constant_tl(0), + mask, hex_slot_cancelled); + tcg_temp_free(mask); + + tcg_gen_brcondi_tl(cond, LSB, 0, skip); + tcg_temp_free(LSB); + gen_return_base(ctx, dst, src, r29); + gen_set_label(skip); + gen_log_predicated_reg_write(HEX_REG_SP, r29, ctx->insn->slot); + tcg_temp_free(r29); +} + +/* sub-instruction version (no RddV, so handle it manually) */ +static void gen_cond_return_subinsn(DisasContext *ctx, TCGCond cond, TCGv = pred) +{ + TCGv_i64 RddV =3D tcg_temp_local_new_i64(); + gen_cond_return(ctx, RddV, hex_gpr[HEX_REG_FP], pred, cond); + gen_log_predicated_reg_write_pair(HEX_REG_FP, RddV, ctx->insn->slot); + tcg_temp_free_i64(RddV); +} + static void gen_endloop0(DisasContext *ctx) { TCGv lpcfg =3D tcg_temp_local_new(); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 35449ef524..cb43519edf 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -105,30 +105,6 @@ void log_store64(CPUHexagonState *env, target_ulong ad= dr, env->mem_log_stores[slot].data64 =3D val; } =20 -void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof, - target_ulong addr) -{ - HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); - - if (pkt_has_multi_cof) { - /* - * If more than one branch is taken in a packet, only the first one - * is actually done. - */ - if (env->branch_taken) { - HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, " - "ignoring the second one\n"); - } else { - fCHECK_PCALIGN(addr); - env->gpr[HEX_REG_PC] =3D addr; - env->branch_taken =3D 1; - } - } else { - fCHECK_PCALIGN(addr); - env->gpr[HEX_REG_PC] =3D addr; - } -} - /* Handy place to set a breakpoint */ void HELPER(debug_start_packet)(CPUHexagonState *env) { @@ -525,51 +501,6 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonSta= te *env, int mask, } } =20 -/* - * mem_noshuf - * Section 5.5 of the Hexagon V67 Programmer's Reference Manual - * - * If the load is in slot 0 and there is a store in slot1 (that - * wasn't cancelled), we have to do the store first. - */ -static void check_noshuf(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr, int size) -{ - if (slot =3D=3D 0 && env->pkt_has_store_s1 && - ((env->slot_cancelled & (1 << 1)) =3D=3D 0)) { - HELPER(probe_noshuf_load)(env, vaddr, size, MMU_USER_IDX); - HELPER(commit_store)(env, 1); - } -} - -uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr) -{ - uintptr_t ra =3D GETPC(); - check_noshuf(env, slot, vaddr, 1); - return cpu_ldub_data_ra(env, vaddr, ra); -} - -uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, target_ulong vaddr) -{ - uintptr_t ra =3D GETPC(); - check_noshuf(env, slot, vaddr, 2); - return cpu_lduw_data_ra(env, vaddr, ra); -} - -uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, target_ulong vaddr) -{ - uintptr_t ra =3D GETPC(); - check_noshuf(env, slot, vaddr, 4); - return cpu_ldl_data_ra(env, vaddr, ra); -} - -uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, target_ulong vaddr) -{ - uintptr_t ra =3D GETPC(); - check_noshuf(env, slot, vaddr, 8); - return cpu_ldq_data_ra(env, vaddr, ra); -} - /* Floating point */ float64 HELPER(conv_sf2df)(CPUHexagonState *env, float32 RsV) { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 75f28e08ad..5be24102aa 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -42,7 +42,6 @@ TCGv hex_store_addr[STORES_MAX]; TCGv hex_store_width[STORES_MAX]; TCGv hex_store_val32[STORES_MAX]; TCGv_i64 hex_store_val64[STORES_MAX]; -TCGv hex_pkt_has_store_s1; TCGv hex_dczero_addr; TCGv hex_llsc_addr; TCGv hex_llsc_val; @@ -287,7 +286,6 @@ static void gen_start_packet(DisasContext *ctx) for (i =3D 0; i < STORES_MAX; i++) { ctx->store_width[i] =3D 0; } - tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); ctx->s1_store_processed =3D false; ctx->pre_commit =3D true; =20 @@ -1026,8 +1024,6 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); hex_branch_taken =3D tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, branch_taken), "branch_taken"); - hex_pkt_has_store_s1 =3D tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); hex_dczero_addr =3D tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); hex_llsc_addr =3D tcg_global_mem_new(cpu_env, --=20 2.17.1