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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1674614572985100004 Extend the analyze_ functions for HVX vector and predicate writes Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py During gen_start_packet, reload the predicated HVX registers into fugure_VRegs and tmp_VRegs Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 14 ++++++++------ target/hexagon/translate.c | 30 +++++++++++++++++++++++++++++ target/hexagon/gen_analyze_funcs.py | 17 +++++++++++++--- target/hexagon/gen_tcg_funcs.py | 18 ----------------- 4 files changed, 52 insertions(+), 27 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d45d3a4bb0..e997f74278 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -54,6 +54,8 @@ typedef struct DisasContext { DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS); DECLARE_BITMAP(vregs_updated, NUM_VREGS); DECLARE_BITMAP(vregs_select, NUM_VREGS); + DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS); + DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS); int qreg_log[NUM_QREGS]; bool qreg_is_predicated[NUM_QREGS]; int qreg_log_idx; @@ -98,12 +100,6 @@ static inline void ctx_log_reg_write_pair(DisasContext = *ctx, int rnum, ctx_log_reg_write(ctx, rnum + 1, is_predicated); } =20 -static inline bool is_vreg_preloaded(DisasContext *ctx, int num) -{ - return test_bit(num, ctx->vregs_updated) || - test_bit(num, ctx->vregs_updated_tmp); -} - intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, int num, bool alloc_ok); intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, @@ -119,12 +115,18 @@ static inline void ctx_log_vreg_write(DisasContext *c= tx, ctx->vreg_log_idx++; =20 set_bit(rnum, ctx->vregs_updated); + if (is_predicated) { + set_bit(rnum, ctx->predicated_future_vregs); + } } if (type =3D=3D EXT_NEW) { set_bit(rnum, ctx->vregs_select); } if (type =3D=3D EXT_TMP) { set_bit(rnum, ctx->vregs_updated_tmp); + if (is_predicated) { + set_bit(rnum, ctx->predicated_tmp_vregs); + } } } =20 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 8f3436d69a..30a06bd442 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -362,6 +362,8 @@ static void gen_start_packet(DisasContext *ctx) bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS); bitmap_zero(ctx->vregs_updated, NUM_VREGS); bitmap_zero(ctx->vregs_select, NUM_VREGS); + bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS); + bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); ctx->qreg_log_idx =3D 0; for (i =3D 0; i < STORES_MAX; i++) { ctx->store_width[i] =3D 0; @@ -409,6 +411,34 @@ static void gen_start_packet(DisasContext *ctx) } } =20 + /* Preload the predicated HVX registers into future_VRegs and tmp_VReg= s */ + if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { + int i =3D find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); + while (i < NUM_VREGS) { + const intptr_t VdV_off =3D + ctx_future_vreg_off(ctx, i, 1, true); + intptr_t src_off =3D offsetof(CPUHexagonState, VRegs[i]); + tcg_gen_gvec_mov(MO_64, VdV_off, + src_off, + sizeof(MMVector), + sizeof(MMVector)); + i =3D find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i= + 1); + } + } + if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) { + int i =3D find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); + while (i < NUM_VREGS) { + const intptr_t VdV_off =3D + ctx_tmp_vreg_off(ctx, i, 1, true); + intptr_t src_off =3D offsetof(CPUHexagonState, VRegs[i]); + tcg_gen_gvec_mov(MO_64, VdV_off, + src_off, + sizeof(MMVector), + sizeof(MMVector)); + i =3D find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + = 1); + } + } + if (pkt->pkt_has_hvx) { tcg_gen_movi_tl(hex_VRegs_updated, 0); tcg_gen_movi_tl(hex_QRegs_updated, 0); diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py index 67a8e5e5e2..7b05b165a1 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -83,9 +83,16 @@ def analyze_opn_old(f, tag, regtype, regid, regno): else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "V"): + newv =3D "EXT_DFL" + if (hex_common.is_new_result(tag)): + newv =3D "EXT_NEW" + elif (hex_common.is_tmp_result(tag)): + newv =3D "EXT_TMP" if (regid in {"dd", "xx"}): - f.write("// const int %s =3D insn->regno[%d];\n" %\ + f.write(" const int %s =3D insn->regno[%d];\n" %\ (regN, regno)) + f.write(" ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \ + (regN, newv, predicated)) elif (regid in {"uu", "vv"}): f.write("// const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) @@ -93,14 +100,18 @@ def analyze_opn_old(f, tag, regtype, regid, regno): f.write("// const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) elif (regid in {"d", "x", "y"}): - f.write("// const int %s =3D insn->regno[%d];\n" % \ + f.write(" const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) + f.write(" ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \ + (regN, newv, predicated)) else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "Q"): if (regid in {"d", "e", "x"}): - f.write("// const int %s =3D insn->regno[%d];\n" % \ + f.write(" const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) + f.write(" ctx_log_qreg_write(ctx, %s, %s);\n" % \ + (regN, predicated)) elif (regid in {"s", "t", "u", "v"}): f.write("// const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 5d686ebcf1..3786ede44c 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -159,17 +159,6 @@ def genptr_decl(f, tag, regtype, regid, regno): f.write(" ctx_future_vreg_off(ctx, %s%sN," % \ (regtype, regid)) f.write(" 1, true);\n"); - if 'A_CONDEXEC' in hex_common.attribdict[tag]: - f.write(" if (!is_vreg_preloaded(ctx, %s)) {\n" % (regN= )) - f.write(" intptr_t src_off =3D") - f.write(" offsetof(CPUHexagonState, VRegs[%s%sN]);\n"% \ - (regtype, regid)) - f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \ - (regtype, regid)) - f.write(" src_off,\n") - f.write(" sizeof(MMVector),\n") - f.write(" sizeof(MMVector));\n") - f.write(" }\n") =20 if (not hex_common.skip_qemu_helper(tag)): f.write(" TCGv_ptr %s%sV =3D tcg_temp_new_ptr();\n" % \ @@ -495,9 +484,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv= =3D"EXT_DFL"): (regtype, regid, regtype, regid)) f.write("%s, insn->slot, %s);\n" % \ (newv, is_predicated)) - f.write(" ctx_log_vreg_write_pair(ctx, %s%sN, %s,\n" % \ - (regtype, regid, newv)) - f.write(" %s);\n" % (is_predicated)) elif (regid in {"d", "x", "y"}): if ('A_CONDEXEC' in hex_common.attribdict[tag]): is_predicated =3D "true" @@ -507,8 +493,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv= =3D"EXT_DFL"): (regtype, regid, regtype, regid, newv)) f.write("insn->slot, %s);\n" % \ (is_predicated)) - f.write(" ctx_log_vreg_write(ctx, %s%sN, %s, %s);\n" % \ - (regtype, regid, newv, is_predicated)) else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "Q"): @@ -520,8 +504,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv= =3D"EXT_DFL"): f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \ (regtype, regid, regtype, regid, newv)) f.write("insn->slot, %s);\n" % (is_predicated)) - f.write(" ctx_log_qreg_write(ctx, %s%sN, %s);\n" % \ - (regtype, regid, is_predicated)) else: print("Bad register parse: ", regtype, regid) else: --=20 2.17.1