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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id w14-20020a5d608e000000b002bc84c55758sm4609145wrt.63.2023.01.25.00.42.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 00:42:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cwmWUou3n7EK2dJeuj7/aaDxziEUHfXgfhDPpUIodg0=; b=WpL9rvglxaPJswbSjl+3hVNq/kFYhxjifUM9Ob7HJnPn44ZYY8X53kpuVkvdyBz9Rr hLwUupIAy7G/JYeO/Hbk1XcZXonFtqRWNmQENa1CzUguuVnvjeiXkCqN7YLqE/xd1UjT GCNjbuvpYkZPiUFfZQG6yfb65mY9ZYzzG2bQV/OLHaMBC2lfmSva7hg/hLktnR3/j2fe AK2Ky2IFPyBZz9jAbEKSmdOvu9JyB5PiqpJe7wrStb2qXOIGZJwEZafKqDU2X4tLqIiU BIZVsTYzDupDfl/BK1I1LR4Ee3J2Phrvfch69vKmDgrxR4hXomowtt57vFtyhgK/HJG3 SiqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cwmWUou3n7EK2dJeuj7/aaDxziEUHfXgfhDPpUIodg0=; b=qgJWAr0aW2mXOMidS5cJMLAFjQ8zVXqmEN6FLhKPag7FEacuuYTiaJTticqdwKOJsX jVxkm6pGeNvpymnLXA6br0Mg7fcHZrKg+5RYFhYfkxbY2Dy9nItY7MDu+Nt07UhzHqe1 FyW/5P6+Gw51g58zRn6hrad1F5mwNasvQQAL5MlTtBjb+W0O7XGVPUUhODtvJbWfECrI 10knDrLutEqJgN5B3xU810R0l9j4rCP6zJFgD9oJ7kWK86LN0WCh2x8mYe9V4FXG/zYI hHu+naEk9aYR75AfxPY+AyWPdqu7pLRk1mh7kXzuf2CtSNVL9ACirtNJ5mTqS4jlh9kV EhNg== X-Gm-Message-State: AO0yUKVD7Lwu0Zccqvp4D49wSX1veMoWVcmRm984CidQZcYLvgrTN2Jb dDlmzNtd1vsexKS48BbfFRa9iQ== X-Google-Smtp-Source: AK7set/F+bJPoWvq+YGQie12Nf1t3royEghLt6hYxMUUxx43b8XbzIBllSNNcA2OeN/X+GqwuX6nzQ== X-Received: by 2002:a05:6000:257:b0:2bf:bb48:ddaf with SMTP id m23-20020a056000025700b002bfbb48ddafmr834899wrz.7.1674636133233; Wed, 25 Jan 2023 00:42:13 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v7 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Wed, 25 Jan 2023 09:41:03 +0100 Message-Id: <20230125084107.1580972-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125084107.1580972-1-alexghiti@rivosinc.com> References: <20230125084107.1580972-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1674636166661100002 Content-Type: text/plain; charset="utf-8" One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..7181b34f86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } =20 #if defined(TARGET_RISCV64) @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif =20 @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { Property *prop; + DeviceState *dev =3D DEVICE(obj); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); --=20 2.37.2