From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103157; cv=none; d=zohomail.com; s=zohoarc; b=Loty5iA90Ke6Ikdcs952SYXnkoNAKy9Q7NY6Sb6VOm4XBDaQlLbC7Njqa3DB+jTvGTdtN4e8bEdOdllKEjZEr74x/axoWxFC2gARPYv6pnoaHdeDAuKT4zhTvptTvdfL3Tbb4ZCwkV2MbBUdlRd4ejksGpgo8EncJNpWzbSWwr0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103157; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=go2SaPky1rTKNTTKbI6nYsdnpD4UmWB7Rewm+CymwZw=; b=Fl+cjCheVyT3v9fNIESN7olGJj3vzpL0J8pMz6IlwAl/NT6IgcOK/U45tr62qAvR1tmsnG7cCwh9CEAXihwfoSB6xzfc6SDaixUmumcbebo94hypHrIt+g0ORSOYEuOaoudD6P1A/snjqFyB3OvQbZpMvbtC/+AXLossIKLJaEA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103157744579.6014825368713; Mon, 30 Jan 2023 10:25:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYq7-0000zF-Pf; Mon, 30 Jan 2023 13:25:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYq5-0000yQ-V7 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:09 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYq2-0008CF-P2 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:09 -0500 Received: by mail-wr1-x434.google.com with SMTP id bk16so11966584wrb.11 for ; Mon, 30 Jan 2023 10:25:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=go2SaPky1rTKNTTKbI6nYsdnpD4UmWB7Rewm+CymwZw=; b=HUeOK2D8a+YDbPcs7aL9SrhKNW6aBBLCjAfi5vJ95AxrVm8jto0l5UObpAnxyyO09c 4YxLKnlh/TT6/lcsfI0malZw3y2rMEEyO9DGjkyoyYFmnwEK3/GWj1bNgS0FHzAVzDSh AeSPxhAtQ5LE/xyB7iqO529sSfAzkYO30RveWlwD298ImITUvfUQJ25EXkdZRWNMUlha DsRdNscrhGzeODuZXfl51toBd6E18M0OhGKMrqMWbk/jbtrHFPOCB+1HIvaZDAYGVlfq LbW2SHii/tIYVdxdPlfLK4o52q5z8u5YANj9qkscGKHzT2lo2Y4Tg+iw/9g+Ml8LRXfW XMwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=go2SaPky1rTKNTTKbI6nYsdnpD4UmWB7Rewm+CymwZw=; b=7HeOk1kuWZtI1caN4+3zwoL89+4qO/cdzScHy0L9ue3/wYmfC3X9DXUPNodbjvO1ke RQYvnyoaHoRb7liwH5WOsanAzTwgmERpnTbmpTTj5zmD4JL0/Rh82MzpnKWjWF8RHleQ esY1tQW8M3OHZpUJijsDs3q3IdN56AgHOESIBhFsKZwToWXGvP2yeei1Om88dsk59Qha 3iDkOC+4r9pmwO/Pkfz89FSfMBKtyhm01nTomDznNfJcGxrNM0zgcoEB+tebees3fJ21 VNL61ckEa2HnUrszsA8FeIBETl6AbAP1wVsEJ2sZWTEVkFZKOgu9CKUDz59pHYOPxrVz WtYA== X-Gm-Message-State: AO0yUKVtDqouvkEWr7dZkREC1GM1uRqo/0wCI/hC2gJ5pQJFIboVKBrG DvdRQcscIZXLGzO35zhQZCvaJA== X-Google-Smtp-Source: AK7set8k++mqi582J9+/79n+4+Cg9mqX6AQlR3UzZ1alGr8AnLzM+cOjicJ/wMDhp2Mow/dvhiPdpg== X-Received: by 2002:a5d:4578:0:b0:2bf:c725:85 with SMTP id a24-20020a5d4578000000b002bfc7250085mr14591485wrc.12.1675103102487; Mon, 30 Jan 2023 10:25:02 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/23] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly Date: Mon, 30 Jan 2023 18:24:37 +0000 Message-Id: <20230130182459.3309057-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103158806100001 Content-Type: text/plain; charset="utf-8" The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name them AT S1E1R and AT S1E1W (which are entirely different instructions). Fix the names. (This has no guest-visible effect as the names are for debug purposes only.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-2-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 72b37b7cf17..ccb7d1e1712 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7734,11 +7734,11 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { =20 #ifndef CONFIG_USER_ONLY static const ARMCPRegInfo ats1e1_reginfo[] =3D { - { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + { .name =3D "AT_S1E1RP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write64 }, - { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + { .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write64 }, --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103205; cv=none; d=zohomail.com; s=zohoarc; b=XAriPyCmDpmo6+fDPgYaabuwD7XUQcR53dTav7TgQ3iWQlLnDM2xYkVGO2dElFl0WVXRpCt++UUIJ8EctSl0OkE1mLY1NUk5INKnsbkN+s+qfKO0Ap5PXSTSicEvLi3zbdNxqIQ5ilaX++uN6/Zyrffv2LF/BHplSKTKAVa9RF4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103205; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rq0lR9ne6I1nZstcxCOL1EodaQTBuWKIlIMnYQtQVEQ=; b=fzGtBWahzyAbOvsL6JI7By2w60Ipl+s6O1UBljZRUNB9TD3G544D7yyvgRiFo4cyfF0xLL4TOJcbd4jooU2oU166BcwtAel477DKKAwFi4UYM1HJahP8bTg8yC8Me9uCyCr5c+pt3RJWYueQWT0W/V6IjJSbE5lP1weGpnASFQg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103205881400.4015196313725; Mon, 30 Jan 2023 10:26:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqE-00011y-Bg; Mon, 30 Jan 2023 13:25:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYq7-0000yh-Ec for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:11 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYq3-0008IP-Bx for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:10 -0500 Received: by mail-wr1-x434.google.com with SMTP id q10so11991963wrm.4 for ; Mon, 30 Jan 2023 10:25:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rq0lR9ne6I1nZstcxCOL1EodaQTBuWKIlIMnYQtQVEQ=; b=CWBNV5kpX6yRYgoF+3K/zfNPHilLx7rVI7ZPhV9eX5W/Q66I20JRXkNF1ugMm6S4BM Dd9DNjnzaWbrncSHM8BzU89sjBwqxmD2fWyhcqS1uxyGmEHHvRGpC3eBDNom5AJJsyns zNfrnw9nDKSs2bjpiQnUcbg84hK59iTVYEBwPeqzp6/nMibgUcaclpSAxnUyUn1Sm4dF ZNleYuioKtbCjP6F5IHAimgP4cx++3MtoQaqFKeIGrYtTMgK1NWXUxQCzQ5NiIFw/ANN 5V7VGrSFu1PsGJNHcsxCeOlzJGqLewxYY3qbRaOvzWbr/JOypH5vYzzCtUTt7DpWaebU jiqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rq0lR9ne6I1nZstcxCOL1EodaQTBuWKIlIMnYQtQVEQ=; b=qgfHToq25vibMVCTCWTB2Hqfxv1GbA+TkSyGlwP3TaQiYNJP4UFBZ9gu/RVIp8i2eT lllVbS8vfRSxle6tK+VqcNoeM+rDjyTD3pWVMBT63vropEveAy0pV8cXKHdmJh+xJZou +3a6mgPzF/NoYsFqmiayAq1KTfo2RV2QhB8tbEx5bSG7GRu93dx3g4LAfAPq3dchIDHS fQQfQMXgaiEcPA30mcYfyDYAEXnhY3GYCgEZT0qpjuwBoUysY+6wLKy5hla8i759v7W0 FaZC0Ssr+yGWyTeX1aMylDTUOat402ODs/qljpbeml//Tq6b/guDyTxiDnXujJ7qXUID KlNQ== X-Gm-Message-State: AO0yUKV2qrjQJAMnXESYLmPvTG4ONtznwm2+AcH6dG8s9SxwakdCsvz7 UfMDjQBPLekBAUP34RunduePhA== X-Google-Smtp-Source: AK7set/MHq2NGtButXFb0sZ+cSHbDmXBxS7gKzGnzONKFC/XNlHskhCa9MBSYWWqftPRUuDAwNQp3A== X-Received: by 2002:a5d:5b0c:0:b0:2bf:eb2c:369 with SMTP id bx12-20020a5d5b0c000000b002bfeb2c0369mr320600wrb.66.1675103103713; Mon, 30 Jan 2023 10:25:03 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/23] target/arm: Correct syndrome for ATS12NSO* at Secure EL1 Date: Mon, 30 Jan 2023 18:24:38 +0000 Message-Id: <20230130182459.3309057-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103207263100003 Content-Type: text/plain; charset="utf-8" The AArch32 ATS12NSO* address translation operations are supposed to trap to either EL2 or EL3 if they're executed at Secure EL1 (which can only happen if EL3 is AArch64). We implement this, but we got the syndrome value wrong: like other traps to EL2 or EL3 on an AArch32 cpreg access, they should report the 0x3 syndrome, not the 0x0 'uncategorized' syndrome. This is clear in the access pseudocode for these instructions. Fix the syndrome value for these operations by correcting the returned value from the ats_access() function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ccb7d1e1712..6f6772d8e04 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3284,9 +3284,9 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, if (arm_current_el(env) =3D=3D 1) { if (arm_is_secure_below_el3(env)) { if (env->cp15.scr_el3 & SCR_EEL2) { - return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; + return CP_ACCESS_TRAP_EL2; } - return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; + return CP_ACCESS_TRAP_EL3; } return CP_ACCESS_TRAP_UNCATEGORIZED; } --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103205; cv=none; d=zohomail.com; s=zohoarc; b=BX7b6j8fVY1W9XdQiIIY8Hu/CB6XIEYjh/X9RYgVUlzZY58rmRFqzaZwVdW+mvM7CWsb1H40IN6LFFOTxV9LMJy7YfVp6BiHviKybcT5cA4kZyj07rTXlMeRbW+Vgrlo7AtOUVLkTIYYazu6dPB42qKovOJ6tBPs7lmrKMHtq4I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103205; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6nliOuAuRjTcf2JoYdVKu3rNo2RhYZa+jJOmXF9ZJUU=; b=JIdJj928zi9oDuRQCOftSZF+AV0Z5/c+jXqhbE9YNrEMxkgy50XgzAjC8kpeUJVYuR/wqpz14qNFPzzRxGYqE9jsGzr1iPV1lDe6Wr+atqX9NaFXBnctpwysZn3sAVab8IWuULos0JIQzqz7CZ4jCrNjzt+zAKOPOE1sFmVZnog= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103205874145.27601101998266; Mon, 30 Jan 2023 10:26:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqF-00012F-Ee; Mon, 30 Jan 2023 13:25:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYq9-0000zb-0t for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:13 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYq4-0008NL-GD for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:12 -0500 Received: by mail-wr1-x435.google.com with SMTP id t18so12010366wro.1 for ; Mon, 30 Jan 2023 10:25:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6nliOuAuRjTcf2JoYdVKu3rNo2RhYZa+jJOmXF9ZJUU=; b=kQwbvB71/z0WSJG9nauI5EZOVUcseABqYN/23Efvh70IYR9DqIU4GhSsPzKSLJOEKp 9VXaxaqtIqz/5nU21Cc0878kKi13t3QrgVohhEhZUyXU4I7/hl51m16OGZvQNSWec7V4 nEoMs8eoU/lZXFPeeyGkjsh3K03dBJosNxOs89u3JTiqZIdHl2tvU5nhTC3T/tvzOMvz Jv0QmH7HGKKpdC/cOD5QPgE9o1lUmkjqP6hwxPbahYUwOVW2ESjOe9NiVSCYcj6t8shx 9pREYPmBhYMOEAUaw9Tg7f2KEvgVngHBpcLtLya2lQQ+xktxc+C4YsKwng17D0UJFCIO Mvqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6nliOuAuRjTcf2JoYdVKu3rNo2RhYZa+jJOmXF9ZJUU=; b=HpkCZ0R5E6jcI0SWeMuVR/byLahnYrEKGku5ZAhm+hwEnSxm0y+SGktDKoVxMsSPd2 4LYVZtrMUy/gT1jc0REA+N/IXgt52ByUcZoiXtDBDH0/w3kJR4X4JciHKvrMN/b3rPaJ 0cjiJQhDOjtgMbrr+ednD0CtZY8/N4yYe6gd28ukNhS6jSO37qHuVZRDVCCwGLo3F44B 2xhRQOVcoScNmAAeqWgBweHQE/Jl4OkDzEJWNTRl2sS1hu7jCfpV5Hb/YjXtrc9mYSJM fNTDlCeZzkWND/51YJfPCjlQ36Tkne8o+0qENqMoKIYrMpYkkyILXARseLg3XMu269cR yDjg== X-Gm-Message-State: AO0yUKWY0NFqRV759qshie3ZiLGnEaHph9BrZi3u0c3qs4diBgXlmJHB tHSQRAx59+Heo6VJB9oYE3KLV7MYT6DZVniM X-Google-Smtp-Source: AK7set+W0A8z4DgvezmvSZAGf9HrJ1y70QwjYouy1sHU5nss5aNz632TeyQGrEghhQ4RLkCiQVp5RA== X-Received: by 2002:a05:6000:18a9:b0:2bf:b54f:61f0 with SMTP id b9-20020a05600018a900b002bfb54f61f0mr30607927wri.57.1675103104578; Mon, 30 Jan 2023 10:25:04 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/23] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} Date: Mon, 30 Jan 2023 18:24:39 +0000 Message-Id: <20230130182459.3309057-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103207274100004 Content-Type: text/plain; charset="utf-8" We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2 and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in the ats_access() function, but doing so was incorrect (a bug fixed in a previous commit). There aren't any cases where we want an access function to be able to request a trap to EL2 or EL3 with a zero syndrome value, so remove these enum values. As well as cleaning up dead code, the motivation here is that we'd like to implement fine-grained-trap handling in helper_access_check_cp_reg(). Although the fine-grained traps to EL2 are always lower priority than trap-to-same-EL and higher priority than trap-to-EL3, they are in the middle of various other kinds of trap-to-EL2. Knowing that a trap-to-EL2 must always for us have the same syndrome (ie that an access function will return CP_ACCESS_TRAP_EL2 and there is no other kind of trap-to-EL2 enum value) means we don't have to try to choose which of the two syndrome values to report if the access would trap to EL2 both for the fine-grained-trap and because the access function requires it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 4 ++-- target/arm/op_helper.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7e78c2c05c6..9744179df01 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -224,10 +224,10 @@ typedef enum CPAccessResult { * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). * Note that this is not a catch-all case -- the set of cases which may * result in this failure is specifically defined by the architecture. + * This trap is always to the usual target EL, never directly to a + * specified target EL. */ CP_ACCESS_TRAP_UNCATEGORIZED =3D (2 << 2), - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 2, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 3, } CPAccessResult; =20 typedef struct ARMCPRegInfo ARMCPRegInfo; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 31f89db8997..def5d3515e2 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -673,6 +673,8 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *en= v, uint32_t key, case CP_ACCESS_TRAP: break; case CP_ACCESS_TRAP_UNCATEGORIZED: + /* Only CP_ACCESS_TRAP traps are direct to a specified EL */ + assert((res & CP_ACCESS_EL_MASK) =3D=3D 0); if (cpu_isar_feature(aa64_ids, cpu) && isread && arm_cpreg_in_idspace(ri)) { /* --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103212; cv=none; d=zohomail.com; s=zohoarc; b=h0Ygt1/6m8nCFmNDAaaUk/qFcEuf9UBJyY5o9qFXz+pN7gT5x0ep7YedbbQH0PiN5W+TjtFO4NmpFEhnV20IVLBE4E+zpsbDOMPd3pI8XPSdrybn2gTe8HP2ZTySracu6vXsBJaxytpMtHSpkkbPVqHgQEXncaBuWt8wuZjsIlw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103212; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Jcvd+N8dP8c49YORsITsraMbFg3q5O5eU5IyRhoB5B0=; b=LDGKrJXWrUDyHG+fhNtbH5us0cTTTwJnmwvz1DEihGMGLD11vcS87bXeifKNatvf/RcBO/6h1ApADP595bvGtktVAsU7VFgFKUAenjZjab1ILobJezsRBqx9FXq7bscVyPTWBXAugHbxCl0MiXvZxXKvg2SBk++Jh3GgOxIRYi0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103212906187.7970397429374; Mon, 30 Jan 2023 10:26:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqH-00012b-2t; Mon, 30 Jan 2023 13:25:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYqA-000108-9V for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:15 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYq4-0008O3-Um for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:13 -0500 Received: by mail-wr1-x42a.google.com with SMTP id t18so12010432wro.1 for ; Mon, 30 Jan 2023 10:25:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Jcvd+N8dP8c49YORsITsraMbFg3q5O5eU5IyRhoB5B0=; b=Kjw1omPf+0Hh7OwZLbBENhSQhY0B1Rsvd++4cV9RmnQfpTyVzJ/1CECKCXB7ofGcyy CAk/f7xVBbFQdfs151DqGymz9pJxq+TNRR7zQalWDL3geeT4dqqXz3Zkiu5R+SVlUH8O 5/h8u5vD8ankaLCtJelg3lgJQH8yZy1DKgfOpy4ONNgyd6/szbdA4C0S5SRhdJf0B28T vTSWw3QzG7MIXiB4RbrS3qzZ8ycgdpJPcgkMmNrvcbKIYyGOvdYTL8ses/mveefJTL83 kFj0Gsl61NDBpDRxxhRB3C10Ty22mtg6y2WKFJH6RWOg6CHg/nTpDULqkX33VJtfAwoH Y54g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jcvd+N8dP8c49YORsITsraMbFg3q5O5eU5IyRhoB5B0=; b=CNr2iESA9LA97sZRWggQOqjxpaEY0UUuHwI8VXjW1ddG32oRm64KlP87O1wK3z2nrF hqPglHBCOfHYqLp3VVHAWObaaZmvq3lnajy0pLLoD52m3XBmFMBq4s4mVQ5OirJ1JwAt SYwbGiYbJcr+kgOYiCVn0OJsAFvX2M1CP+rwAbx6LXwrZ+g0hYivQ3lUPoGXfaCg3k0x jAKhU95SB+YqDyZPe+FXqc1fxzLZ9mPiyagFUYDycPfDGJmMofSy4DVYtEKPR6WnlJoP YN556A/tJXgwcmdYzYDcq/Vouobmqh58QOawfJxgc2qZMcbPj2aVOB07uCixoXHtZtn8 lBqA== X-Gm-Message-State: AO0yUKVj6Pio5FHOe3uydlEGZPsa2kYwDtJy5beyQJX6cj/J4Sip+dLu wqKyQFGE5TluKMolPbB6DSLT6A== X-Google-Smtp-Source: AK7set+5fPvL33JJJQcDu6JoaFL01YbvbV/vXkwKQGdI6gjk0aXL6l18fXzOEDfQ8ZFy7SDxcAu0hw== X-Received: by 2002:adf:a1ce:0:b0:2bf:cfc2:2eae with SMTP id v14-20020adfa1ce000000b002bfcfc22eaemr11920743wrv.69.1675103105798; Mon, 30 Jan 2023 10:25:05 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/23] target/arm: Move do_coproc_insn() syndrome calculation earlier Date: Mon, 30 Jan 2023 18:24:40 +0000 Message-Id: <20230130182459.3309057-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103214624100003 Content-Type: text/plain; charset="utf-8" Rearrange the code in do_coproc_insn() so that we calculate the syndrome value for a potential trap early; we're about to add a second check that wants this value earlier than where it is currently determined. (Specifically, a trap to EL2 because of HSTR_EL2 should take priority over an UNDEF to EL1, even when the UNDEF is because the register does not exist at all or because its ri->access bits non-configurably fail the access. So the check we put in for HSTR_EL2 trapping at EL1 (which needs the syndrome) is going to have to be done before the check "is the ARMCPRegInfo pointer NULL".) This commit is just code motion; the change to HSTR_EL2 handling that will use the 'syndrome' variable is in a subsequent commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-5-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/translate.c | 83 +++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 365e02fb0b8..9252a464a12 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4718,6 +4718,47 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); TCGv_ptr tcg_ri =3D NULL; bool need_exit_tb; + uint32_t syndrome; + + /* + * Note that since we are an implementation which takes an + * exception on a trapped conditional instruction only if the + * instruction passes its condition code check, we can take + * advantage of the clause in the ARM ARM that allows us to set + * the COND field in the instruction to 0xE in all cases. + * We could fish the actual condition out of the insn (ARM) + * or the condexec bits (Thumb) but it isn't necessary. + */ + switch (cpnum) { + case 14: + if (is64) { + syndrome =3D syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, + isread, false); + } else { + syndrome =3D syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, + rt, isread, false); + } + break; + case 15: + if (is64) { + syndrome =3D syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, + isread, false); + } else { + syndrome =3D syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, + rt, isread, false); + } + break; + default: + /* + * ARMv8 defines that only coprocessors 14 and 15 exist, + * so this can only happen if this is an ARMv7 or earlier CPU, + * in which case the syndrome information won't actually be + * guest visible. + */ + assert(!arm_dc_feature(s, ARM_FEATURE_V8)); + syndrome =3D syn_uncategorized(); + break; + } =20 if (!ri) { /* @@ -4755,48 +4796,6 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, * Note that on XScale all cp0..c13 registers do an access check * call in order to handle c15_cpar. */ - uint32_t syndrome; - - /* - * Note that since we are an implementation which takes an - * exception on a trapped conditional instruction only if the - * instruction passes its condition code check, we can take - * advantage of the clause in the ARM ARM that allows us to set - * the COND field in the instruction to 0xE in all cases. - * We could fish the actual condition out of the insn (ARM) - * or the condexec bits (Thumb) but it isn't necessary. - */ - switch (cpnum) { - case 14: - if (is64) { - syndrome =3D syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, false); - } else { - syndrome =3D syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, false); - } - break; - case 15: - if (is64) { - syndrome =3D syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, false); - } else { - syndrome =3D syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, false); - } - break; - default: - /* - * ARMv8 defines that only coprocessors 14 and 15 exist, - * so this can only happen if this is an ARMv7 or earlier CPU, - * in which case the syndrome information won't actually be - * guest visible. - */ - assert(!arm_dc_feature(s, ARM_FEATURE_V8)); - syndrome =3D syn_uncategorized(); - break; - } - gen_set_condexec(s); gen_update_pc(s, 0); tcg_ri =3D tcg_temp_new_ptr(); --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=i3PZZa+UR17dkZmHlwEV5fYemHt27708BnOn+3KkbpA=; b=Gd5ndaKn7442bBjZ0aruwzRjuBHGIE+iG4aXpSpuP3kdaARRujyOFKxIVCk2W9UYiI jp7f2uO/shhz0jHRycK9EEIZJcKCxfNxiGy2a21uAhnccYN7gGCT/t/148S4OWxrZFPD c+2alkwZpAEeUP+4HB0eHNNVARxSt0KxpvQjZMbWEONgUZrPcO6p5ryN7EnftYHaU/tl bSfW/s95zL5LOXhMgYsTI+t8cP8dIaUzXxJ44CCRC0mS9IyeIsmsKN54hPeWFlYsWc0j gZR8U3Umhxf1HBuEDzx2iwIFdGI01aZbHr0SaU3NZDdiY5mi0UVZJkXDRFBgE/B8FdBk U5Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i3PZZa+UR17dkZmHlwEV5fYemHt27708BnOn+3KkbpA=; b=mux1jFDkeKEfp6N+CE4yiNub7KeNT52hVLNVW7o9bBCNprdkD4VMIHi2njqIgoindC PT0bqLy9fRKMM6nwcvc2WvZmciJObUOi8RRg/ev+zMJc1TNYFJvxwR4zBcvBzNG21Xir Wrj4CnyBxoCngnkMVVbJOEwoZFGZK7O2MKHSPIhdIffa8WzHz+Tsoe8H23uejvg608Kx XTWcx+AfWUfKT+oh3lw4mBZwHOAFrDMlG0VqoWeZl7gmWCuCXYsjmqyGcfkMmeuaPIqU BEDIsuubmt30Y7q498ZDL/GA1GyvMcua2BuMmtR2fPRKajmkQIpWC+J1fQFAI1Vo11c3 wuVg== X-Gm-Message-State: AO0yUKV64YmJbF9pyqWBWzFeSH3/YglfYLjApL0RGqxxAgtU1xi6N0Ws /ecGCx0eIrGgAWL5nDc8nabPLeUewKEYYL7R X-Google-Smtp-Source: AK7set/HMb7eNENG2zQTrpGx+yXBMwFToBaeof1Jf4WmsQCZqZmkyJFWpcdMYlw1seaPYnBv2eY50A== X-Received: by 2002:a5d:4584:0:b0:2bf:dfa2:976f with SMTP id p4-20020a5d4584000000b002bfdfa2976fmr7687163wrq.39.1675103106666; Mon, 30 Jan 2023 10:25:06 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/23] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps Date: Mon, 30 Jan 2023 18:24:41 +0000 Message-Id: <20230130182459.3309057-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103319322100001 Content-Type: text/plain; charset="utf-8" The HSTR_EL2 register has a collection of trap bits which allow trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor registers. The specification of these bits is that when the bit is set we should trap * EL1 accesses * EL0 accesses, if the access is not UNDEFINED when the trap bit is 0 In other words, all UNDEF traps from EL0 to EL1 take precedence over the HSTR_EL2 trap to EL2. (Since this is all AArch32, the only kind of trap-to-EL1 is the UNDEF.) Our implementation doesn't quite get this right -- we check for traps in the order: * no such register * ARMCPRegInfo::access bits * HSTR_EL2 trap bits * ARMCPRegInfo::accessfn So UNDEFs that happen because of the access bits or because the register doesn't exist at all correctly take priority over the HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the accessfn we are incorrectly always taking the HSTR_EL2 trap. There aren't many of these, but one example is the PMCR; if you look at the access pseudocode for this register you can see that UNDEFs taken because of the value of PMUSERENR.EN are checked before the HSTR_EL2 bit. Rearrange helper_access_check_cp_reg() so that we always call the accessfn, and use its return value if it indicates that the access traps to EL0 rather than continuing to do the HSTR_EL2 check. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-6-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/op_helper.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index def5d3515e2..660dae696dd 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -640,10 +640,24 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *= env, uint32_t key, goto fail; } =20 + if (ri->accessfn) { + res =3D ri->accessfn(env, ri, isread); + } + /* - * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses - * to sysregs non accessible at EL0 to have UNDEF-ed already. + * If the access function indicates a trap from EL0 to EL1 then + * that always takes priority over the HSTR_EL2 trap. (If it indicates + * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicat= es + * a trap to EL2, then the syndrome is the same either way so we don't + * care whether technically the architecture says that HSTR_EL2 trap or + * the other trap takes priority. So we take the "check HSTR_EL2" path + * for all of those cases.) */ + if (res !=3D CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) =3D=3D 0) && + arm_current_el(env) =3D=3D 0) { + goto fail; + } + if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp =3D=3D 15 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { uint32_t mask =3D 1 << ri->crn; @@ -661,9 +675,6 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *en= v, uint32_t key, } } =20 - if (ri->accessfn) { - res =3D ri->accessfn(env, ri, isread); - } if (likely(res =3D=3D CP_ACCESS_OK)) { return ri; } --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103333; cv=none; d=zohomail.com; s=zohoarc; b=S9t90srAR6bc7LMSUUwi2Kf4bmd3F87J46XlvZyIFAtMb8ybS+uoFOLxPvyO+4qJ532n/J+WvFSejroMiB6U+sWDibavUSbEVzYGdGrc0gWLGbAGQtgwILh7GU5OaA+TAhVSGo1XxcsBdPLc5Wh/Kz34TS1XUXvCzMjD1R74uTo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103333; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uUpOqstoH60mQhVzBpZ4GM1GT3DjE6YD5hOQtGdm25E=; b=ALPokMY3jL/5QFfpbmxHOlJpgWuRkfdJGbRaa6GGt+ZW/dnCv3uWWGArDlMTQ9nQC8ZzQIzHjVlL2iRg27QrQw41+kla9sX5WDiVFQCikq8SCKZ2svX+ZBfECT7nKypmhttRmlopDbBP7YcYXZeNEJm9Ur2pTAgLUTcET6Uoua0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103333227482.8519527445304; Mon, 30 Jan 2023 10:28:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqK-00016i-7t; Mon, 30 Jan 2023 13:25:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYqB-00010w-Lv for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:16 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYq5-0008P7-QT for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:15 -0500 Received: by mail-wr1-x42b.google.com with SMTP id d14so11975366wrr.9 for ; Mon, 30 Jan 2023 10:25:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uUpOqstoH60mQhVzBpZ4GM1GT3DjE6YD5hOQtGdm25E=; b=TuoPWIPX4hDhIhXa97+MR3D8H6w+92wmcxvxsZ+BzOlomH+QxPJGtCQp9Np+zTafZI QnWQycoAZ37xS8FVQYMUrbKUMOySC2q7CCArDurmpmrWnWoDrjo0yNRODQ90dVpSNKOy dgR1/t4GBlSHoD3hmGJp4YvY1iCqTbHvohnBR6z6NUQekr9kp68zIhevKM3txMe6xOAa WzIAfN3RdSTX9ietsZFSwlpbNFp0ZDl+aCCtLeVgQmk6kbVt3ZpKfzMAL8NduyZJu8fF cTe58caNvsXvX3fLM+0OtHbHZxHyP6yhHybIjRnVI/n6Mhn1nMFRgPSBHULnmY/uyFC3 NDrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uUpOqstoH60mQhVzBpZ4GM1GT3DjE6YD5hOQtGdm25E=; b=rxbPeAgC6DIJCdxxGa8stnxqawfRLMf8ExRPMCMyC0KHwZqiRqhWB2Q7OA+nlXgg0j e1iEYNMws6kLms9BedBnvQ6DZuOiFR4Y1lpXli50TcA9lua/pNMU/SgAghVDjDk3K6oP k5Kf3wVHK1jZkvbIrYM2pG6IQTUJFc42So/Rzrc/HyO2KiX/69oz8qdnoyQJ+mV1wQCR UyCF+JOBO5HQVM5fuVvG1kMIAqqyktdTRRMxiNE3LQiMTLyYYUX5X65hpn9k2oNw2WlV S5iTMEaecW/gOZEO8zYtalNtedXCtTIKiqtpcXAiMv7CPYGTIEUKRmHEVbwUpqhG1iwE Ry5w== X-Gm-Message-State: AFqh2krQSMU/sbnzF3Q5B546vEDJkO6uf5PkzoEkFxa333NeSOgn+pdE OpFja7OhQ09kMB7K9+MJw2MUAg== X-Google-Smtp-Source: AMrXdXvkXR2iepqnLdu/EYN59WDNQOyaXWMbg/3j/xhqTsHDQNXZ+TZNYE6knr469MV0RWvZxOp5Gg== X-Received: by 2002:a5d:4e01:0:b0:2bd:e531:8e58 with SMTP id p1-20020a5d4e01000000b002bde5318e58mr42153976wrt.24.1675103107567; Mon, 30 Jan 2023 10:25:07 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/23] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 Date: Mon, 30 Jan 2023 18:24:42 +0000 Message-Id: <20230130182459.3309057-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103333459100004 Content-Type: text/plain; charset="utf-8" The semantics of HSTR_EL2 require that it traps cpreg accesses to EL2 for: * EL1 accesses * EL0 accesses, if the access is not UNDEFINED when the trap bit is 0 (You can see this in the I_ZFGJP priority ordering, where HSTR_EL2 traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and HSTR_EL2 traps from EL0 are priority 15.) However, we don't get this right for EL1 accesses which UNDEF because the register doesn't exist at all or because its ri->access bits non-configurably forbid the access. At EL1, check for the HSTR_EL2 trap early, before either of these UNDEF reasons. We have to retain the HSTR_EL2 check in access_check_cp_reg(), because at EL0 any kind of UNDEF-to-EL1 (including "no such register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'") takes precedence over the trap to EL2. But we only need to do that check for EL0 now. Signed-off-by: Peter Maydell Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org Reviewed-by: Richard Henderson Tested-by: Fuad Tabba --- target/arm/op_helper.c | 6 +++++- target/arm/translate.c | 28 +++++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 660dae696dd..7797a137af6 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -658,7 +658,11 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *e= nv, uint32_t key, goto fail; } =20 - if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp =3D=3D 15 && + /* + * HSTR_EL2 traps from EL1 are checked earlier, in generated code; + * we only need to check here for traps from EL0. + */ + if (!is_a64(env) && arm_current_el(env) =3D=3D 0 && ri->cp =3D=3D 15 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { uint32_t mask =3D 1 << ri->crn; =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9252a464a12..f4bfe55158e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4760,6 +4760,32 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, break; } =20 + if (s->hstr_active && cpnum =3D=3D 15 && s->current_el =3D=3D 1) { + /* + * At EL1, check for a HSTR_EL2 trap, which must take precedence + * over the UNDEF for "no such register" or the UNDEF for "access + * permissions forbid this EL1 access". HSTR_EL2 traps from EL0 + * only happen if the cpreg doesn't UNDEF at EL0, so we do those in + * access_check_cp_reg(), after the checks for whether the access + * configurably trapped to EL1. + */ + uint32_t maskbit =3D is64 ? crm : crn; + + if (maskbit !=3D 4 && maskbit !=3D 14) { + /* T4 and T14 are RES0 so never cause traps */ + TCGv_i32 t; + DisasLabel over =3D gen_disas_label(s); + + t =3D load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2= )); + tcg_gen_andi_i32(t, t, 1u << maskbit); + tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); + tcg_temp_free_i32(t); + + gen_exception_insn(s, 0, EXCP_UDEF, syndrome); + set_disas_label(s, over); + } + } + if (!ri) { /* * Unknown register; this might be a guest error or a QEMU @@ -4788,7 +4814,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, return; } =20 - if (s->hstr_active || ri->accessfn || + if ((s->hstr_active && s->current_el =3D=3D 0) || ri->accessfn || (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) { /* * Emit code to perform further access permissions checks at --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103338; cv=none; d=zohomail.com; s=zohoarc; b=EjoasoUWICkXQL+fNueL+LTN0OGoKbpcUhFi6vSwC3PrgbQPG7AfcVlRP6XXFCceMWz303AfsN/bw2DcGrH3gNIOcCnTTg/GDR0mKgxEi3C6j2RGYqa/q03efAF+3wApR/Wlw956PxhWV2szXW7jBjilSz4LYkXEEkY0tz58Opo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103338; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dmGYMqKT6htGJ/lTyLu1tD0GGum+71lym1RaJ3XxWLg=; b=TRQ1kb3/T9y0yYoMHrXUkMjV3C/N8yI4Txl24wZLf80l9/CWsAcisPl92Xg1/ZnDh9+CyRMOMfbEnNW0ZZ10xwKKpjkD3dgJ+yCThWa4voM+bBSZjIyNcMkEN7tlUfg/C58exUE/mukie4Nd65Ci9maQSTUl8a0Lk5Q3KdWngD4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103338968251.9613801398409; Mon, 30 Jan 2023 10:28:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqL-00018g-L6; Mon, 30 Jan 2023 13:25:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYqB-00010y-Pl for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:16 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYq6-0008PX-8e for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:15 -0500 Received: by mail-wr1-x435.google.com with SMTP id y1so12006013wru.2 for ; Mon, 30 Jan 2023 10:25:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dmGYMqKT6htGJ/lTyLu1tD0GGum+71lym1RaJ3XxWLg=; b=H1y2mzdOHOSORIQzj9iahYah96m2hGwyd6xypXMOvmgTru8xwnE5zFV8LchVpO30lA U/Jam26NFhMQNJQSsBrpKRfVQIXe4y7W2ImwaUXpi5b1J7o1nLw0NMsl7S/cAfe73DmX kA3Lc1uiSUzSwDh33nbodFqtJwl4EJGypkVXUQy/CnFWP9tu1V1/u155kp9WrOIRdMCD QayWnPSqsuFVrZgs+meJYwZif/f93f0HkCLHK+UE7dD9PhF/PqipXZrGMxJMAe8nKfk1 L2zRt9+AzbHZJrqb24/nSoL+ojGP+tcz2lVrhjn4oZCgPRq99FEBOY5Dt8YWzCaJIP5O pGHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dmGYMqKT6htGJ/lTyLu1tD0GGum+71lym1RaJ3XxWLg=; b=EnT1/QghExnuQ7rmkNSzaVmwc/Ld+eh1uA/m3REOLhdK2iaB0vG54yyNS+OKM6Gk4M bCE5kqw/XGBqtIGIk6CXEsvIm0XIgn8LJG+vxHqrbEDFQMiZARk4gqXJ10nAiTRcHLzE 3JHolTAe8u40M+PUekATmux0wg/qSxnP20+jMwg9+4qbaesHxGiJ6v7MERSIFlHQ2arF lvjRM4nQzce3YbT5PTRYS6aVSuBtWE6/lt4j53+a5f+F0zQ4dGKq2fd8ULpWt21hXEIz kKpKcq4nSShGH5nsjHPEw0Y0ILzLvdgjK3kUzejjPkY8YtBiVq4/Meh0q8CwEP3Mhkrm 7O9A== X-Gm-Message-State: AO0yUKV7YEKsNd8kcpNXYaJCKb0JEc2Njpi+b5I2UuELlNcJEfJ9SwLc p+pnmchubJt5xbM2Y8sk8xXWmEd/g9tKcZLr X-Google-Smtp-Source: AK7set+c6hH8F7IPrNYZuDy33uks9oDtnkBFSm0fgpJoiNFSYvghKwXphhKaTjH+qgtydm3kOWEJSQ== X-Received: by 2002:a5d:4dc1:0:b0:2bf:b2fe:a2ca with SMTP id f1-20020a5d4dc1000000b002bfb2fea2camr21536087wru.20.1675103108515; Mon, 30 Jan 2023 10:25:08 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled Date: Mon, 30 Jan 2023 18:24:43 +0000 Message-Id: <20230130182459.3309057-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103339430100012 Content-Type: text/plain; charset="utf-8" The HSTR_EL2 register is not supposed to have an effect unless EL2 is enabled in the current security state. We weren't checking for this, which meant that if the guest set up the HSTR_EL2 register we would incorrectly trap even for accesses from Secure EL0 and EL1. Add the missing checks. (Other places where we look at HSTR_EL2 for the not-in-v8A bits TTEE and TJDBX are already checking that we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/helper.c | 2 +- target/arm/op_helper.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6f6772d8e04..66966869218 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11716,7 +11716,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState= *env, int fp_el, DP_TBFLAG_A32(flags, VFPEN, 1); } =20 - if (el < 2 && env->cp15.hstr_el2 && + if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7797a137af6..dec03310ad5 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -663,6 +663,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *en= v, uint32_t key, * we only need to check here for traps from EL0. */ if (!is_a64(env) && arm_current_el(env) =3D=3D 0 && ri->cp =3D=3D 15 && + arm_is_el2_enabled(env) && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { uint32_t mask =3D 1 << ri->crn; =20 --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103335; cv=none; d=zohomail.com; s=zohoarc; b=Tf0UKymM4PrEzF1DalxVHqcjgThvNv/ts/WR9tkEYIj7aTWtNRL5EYjAREBtdhCCyM/D5qLHrRVkUScDkzb0HW55JyC825TuA8DX3GI0LG3oEDG43KuWwzRGPMj5sdQPYvXeCqs2OxGXfmCeCAfdq/a5odlDNofz1vZ06qGaV/w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103335; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GZlNUmnacOCKtXq4PeFo0U7gTRR7fZxtFGOCvMCXmM4=; b=L7QZhBmyeF+RnLSjoNOQONTiw7v1AN6C8Dc0yD+TGs9NzBvZ15dOH4H8O00dlx9O5nNR27/yGSDML0UIQG34pQySGD0QCRoN7B6Ai6v8tJiOr+WUzTBk9gHfHAvuxRMqGPB0vcQ+NC69AmMiuSPzOi3sycDBDGpvqC9qtkZ98tk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103335480193.40157735419825; Mon, 30 Jan 2023 10:28:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqK-00017J-JS; Mon, 30 Jan 2023 13:25:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYqF-00012J-NT for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:20 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYq7-0008QE-2L for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:17 -0500 Received: by mail-wr1-x42a.google.com with SMTP id y1so12006052wru.2 for ; Mon, 30 Jan 2023 10:25:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=GZlNUmnacOCKtXq4PeFo0U7gTRR7fZxtFGOCvMCXmM4=; b=M1yW+ngBPV67xrzHeCuvn0ZrLdC0Epb75YVORxSWZMs8fvbPHUszqklRyB62XG6t8E U+htVwyEC1oSiwSdSPliaJxCjfZOCqjgzG6Ibs5pTKD2k1wpjZ2tsZAfNo1vM8GZrBsf h3+Z79d6N2PFTb+Vm2BUPb2+Vnda+/fjXc4n6CR3PXLi73rxD62GM2tC9Ebw2tBSHI8M 303OJH8s9VSCUl/5n2pNBX5dL5i3YUeNzInxzlJL+c2HsgVAz3gkh/qpp7NewxqQXY3G 2yLjSGE/+fhDQbbilFwdxR7Iq1I3SaZ5M43ErhTT0Rbb1oq0+uoamvGgcmhLPHt7biOB CU1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GZlNUmnacOCKtXq4PeFo0U7gTRR7fZxtFGOCvMCXmM4=; b=2oD8x8ogltg7Zxu6kf4tYPWxGOYZ9jwSUozu0uWF4UUXXMq8ciKK49bRNtQvR8Q2u0 TGEE7Y992Bwcv2TkIfE3MxjA5X5ATCulM0a0qSLzKkk0ncSwXBIqMSfM85KrY05d8FcO mINDXmGVGPbLB4kpqXb7rMoSLdlhMGnHnmoBvki8erCLO1R17BWnUhncCr16PZII7seA Pfs66cCF09oPSVDj4HklDFRQRsyjTm+E4Eo2veNzwuqkra3Q3EmSP2r1ya1uwCbS5RBx clgt+FEMTby1JThcbNuy7u9oNr7nUGXcsakVfvccOEprManoL5iwHl6KxRCT7T4YZOo+ rQ+Q== X-Gm-Message-State: AO0yUKXit6tM1rc7WqcuJBJX0nv9aQ6c+8oR2UOu75wQxQkxqgYs80ue ktAJHn/oyX65U9rnRyomk7is/Q== X-Google-Smtp-Source: AK7set+tH+HdP5QkkhJtbOrG4a3U4tlqzqi+joYDv3SbWziT+SQdrQx5OrMmVzR3NBSZEKvUfdPSVg== X-Received: by 2002:adf:e90f:0:b0:2bf:ee0f:9f04 with SMTP id f15-20020adfe90f000000b002bfee0f9f04mr3721055wrm.45.1675103109538; Mon, 30 Jan 2023 10:25:09 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/23] target/arm: Define the FEAT_FGT registers Date: Mon, 30 Jan 2023 18:24:44 +0000 Message-Id: <20230130182459.3309057-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103337459100011 Content-Type: text/plain; charset="utf-8" Define the system registers which are provided by the FEAT_FGT fine-grained trap architectural feature: HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2 All these registers are a set of bit fields, where each bit is set for a trap and clear to not trap on a particular system register access. The R and W register pairs are for system registers, allowing trapping to be done separately for reads and writes; the I register is for system instructions where trapping is on instruction execution. The data storage in the CPU state struct is arranged as a set of arrays rather than separate fields so that when we're looking up the bits for a system register access we can just index into the array rather than having to use a switch to select a named struct member. The later FEAT_FGT2 will add extra elements to these arrays. The field definitions for the new registers are in cpregs.h because in practice the code that needs them is code that also needs the cpregs information; cpu.h is included in a lot more files. We're also going to add some FGT-specific definitions to cpregs.h in the next commit. We do not implement HAFGRTR_EL2, because we don't implement FEAT_AMUv1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 285 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 15 +++ target/arm/helper.c | 40 +++++++ 3 files changed, 340 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 9744179df01..cb3dc567819 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -230,6 +230,291 @@ typedef enum CPAccessResult { CP_ACCESS_TRAP_UNCATEGORIZED =3D (2 << 2), } CPAccessResult; =20 +/* Indexes into fgt_read[] */ +#define FGTREG_HFGRTR 0 +#define FGTREG_HDFGRTR 1 +/* Indexes into fgt_write[] */ +#define FGTREG_HFGWTR 0 +#define FGTREG_HDFGWTR 1 +/* Indexes into fgt_exec[] */ +#define FGTREG_HFGITR 0 + +FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) +FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1) +FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1) +FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1) +FIELD(HFGRTR_EL2, APDAKEY, 4, 1) +FIELD(HFGRTR_EL2, APDBKEY, 5, 1) +FIELD(HFGRTR_EL2, APGAKEY, 6, 1) +FIELD(HFGRTR_EL2, APIAKEY, 7, 1) +FIELD(HFGRTR_EL2, APIBKEY, 8, 1) +FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1) +FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1) +FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1) +FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1) +FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1) +FIELD(HFGRTR_EL2, CTR_EL0, 14, 1) +FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1) +FIELD(HFGRTR_EL2, ESR_EL1, 16, 1) +FIELD(HFGRTR_EL2, FAR_EL1, 17, 1) +FIELD(HFGRTR_EL2, ISR_EL1, 18, 1) +FIELD(HFGRTR_EL2, LORC_EL1, 19, 1) +FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1) +FIELD(HFGRTR_EL2, LORID_EL1, 21, 1) +FIELD(HFGRTR_EL2, LORN_EL1, 22, 1) +FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1) +FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1) +FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1) +FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1) +FIELD(HFGRTR_EL2, PAR_EL1, 27, 1) +FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1) +FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1) +FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1) +FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1) +FIELD(HFGRTR_EL2, TCR_EL1, 32, 1) +FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1) +FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1) +FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1) +FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1) +FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1) +FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1) +FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1) +FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1) +FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1) +FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1) +FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1) +FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1) +FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1) +FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1) +FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) +FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) +FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) +FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) +/* 51-53: RES0 */ +FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) +FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) +/* 56-63: RES0 */ + +/* These match HFGRTR but bits for RO registers are RES0 */ +FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) +FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1) +FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1) +FIELD(HFGWTR_EL2, APDAKEY, 4, 1) +FIELD(HFGWTR_EL2, APDBKEY, 5, 1) +FIELD(HFGWTR_EL2, APGAKEY, 6, 1) +FIELD(HFGWTR_EL2, APIAKEY, 7, 1) +FIELD(HFGWTR_EL2, APIBKEY, 8, 1) +FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1) +FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1) +FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1) +FIELD(HFGWTR_EL2, ESR_EL1, 16, 1) +FIELD(HFGWTR_EL2, FAR_EL1, 17, 1) +FIELD(HFGWTR_EL2, LORC_EL1, 19, 1) +FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1) +FIELD(HFGWTR_EL2, LORN_EL1, 22, 1) +FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1) +FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1) +FIELD(HFGWTR_EL2, PAR_EL1, 27, 1) +FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1) +FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1) +FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1) +FIELD(HFGWTR_EL2, TCR_EL1, 32, 1) +FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1) +FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1) +FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1) +FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1) +FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1) +FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1) +FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1) +FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1) +FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1) +FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1) +FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1) +FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) +FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) +FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) +FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) +FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) +FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) + +FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) +FIELD(HFGITR_EL2, ICIALLU, 1, 1) +FIELD(HFGITR_EL2, ICIVAU, 2, 1) +FIELD(HFGITR_EL2, DCIVAC, 3, 1) +FIELD(HFGITR_EL2, DCISW, 4, 1) +FIELD(HFGITR_EL2, DCCSW, 5, 1) +FIELD(HFGITR_EL2, DCCISW, 6, 1) +FIELD(HFGITR_EL2, DCCVAU, 7, 1) +FIELD(HFGITR_EL2, DCCVAP, 8, 1) +FIELD(HFGITR_EL2, DCCVADP, 9, 1) +FIELD(HFGITR_EL2, DCCIVAC, 10, 1) +FIELD(HFGITR_EL2, DCZVA, 11, 1) +FIELD(HFGITR_EL2, ATS1E1R, 12, 1) +FIELD(HFGITR_EL2, ATS1E1W, 13, 1) +FIELD(HFGITR_EL2, ATS1E0R, 14, 1) +FIELD(HFGITR_EL2, ATS1E0W, 15, 1) +FIELD(HFGITR_EL2, ATS1E1RP, 16, 1) +FIELD(HFGITR_EL2, ATS1E1WP, 17, 1) +FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1) +FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1) +FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1) +FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1) +FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1) +FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1) +FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1) +FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1) +FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1) +FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1) +FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1) +FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1) +FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1) +FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1) +FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1) +FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1) +FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1) +FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1) +FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1) +FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1) +FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1) +FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1) +FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1) +FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1) +FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1) +FIELD(HFGITR_EL2, TLBIVAE1, 43, 1) +FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1) +FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1) +FIELD(HFGITR_EL2, TLBIVALE1, 46, 1) +FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1) +FIELD(HFGITR_EL2, CFPRCTX, 48, 1) +FIELD(HFGITR_EL2, DVPRCTX, 49, 1) +FIELD(HFGITR_EL2, CPPRCTX, 50, 1) +FIELD(HFGITR_EL2, ERET, 51, 1) +FIELD(HFGITR_EL2, SVC_EL0, 52, 1) +FIELD(HFGITR_EL2, SVC_EL1, 53, 1) +FIELD(HFGITR_EL2, DCCVAC, 54, 1) +FIELD(HFGITR_EL2, NBRBINJ, 55, 1) +FIELD(HFGITR_EL2, NBRBIALL, 56, 1) + +FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) +FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) +FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1) +FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1) +FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1) +FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1) +FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1) +FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1) +/* 8: RES0: OSLAR_EL1 is WO */ +FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1) +FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1) +FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1) +FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1) +FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1) +FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1) +FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1) +FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1) +FIELD(HDFGRTR_EL2, PMINTEN, 17, 1) +FIELD(HDFGRTR_EL2, PMOVS, 18, 1) +FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1) +/* 20: RES0: PMSWINC_EL0 is WO */ +/* 21: RES0: PMCR_EL0 is WO */ +FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1) +FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1) +FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1) +FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1) +FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1) +FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1) +FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1) +FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1) +FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1) +FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1) +FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1) +FIELD(HDFGRTR_EL2, TRC, 33, 1) +FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1) +FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1) +FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1) +FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1) +/* 38, 39: RES0 */ +FIELD(HDFGRTR_EL2, TRCID, 40, 1) +FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1) +/* 42: RES0: TRCOSLAR is WO */ +FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1) +FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1) +FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1) +FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1) +FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1) +FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1) +/* 49: RES0: TRFCR_EL1 is WO */ +FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1) +FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1) +FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1) +FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1) +FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1) +FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1) +FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1) +FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1) +FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1) +FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1) +FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1) +FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1) +FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1) +FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1) + +/* + * These match HDFGRTR_EL2, but bits for RO registers are RES0. + * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0. + */ +FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1) +FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1) +FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1) +FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1) +FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1) +FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1) +FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1) +FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1) +FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1) +FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1) +FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1) +FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1) +FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1) +FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1) +FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1) +FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1) +FIELD(HDFGWTR_EL2, PMINTEN, 17, 1) +FIELD(HDFGWTR_EL2, PMOVS, 18, 1) +FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1) +FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1) +FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1) +FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1) +FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1) +FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1) +FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1) +FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1) +FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1) +FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1) +FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1) +FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1) +FIELD(HDFGWTR_EL2, TRC, 33, 1) +FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1) +FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1) +FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1) +FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1) +FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1) +FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1) +FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1) +FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1) +FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1) +FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1) +FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1) +FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1) +FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1) +FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1) +FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1) +FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1) +FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1) +FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) +FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) +FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) + typedef struct ARMCPRegInfo ARMCPRegInfo; =20 /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8cf70693be4..063024508af 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -529,6 +529,16 @@ typedef struct CPUArchState { uint64_t disr_el1; uint64_t vdisr_el2; uint64_t vsesr_el2; + + /* + * Fine-Grained Trap registers. We store these as arrays so the + * access checking code doesn't have to manually select + * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. + * FEAT_FGT2 will add more elements to these arrays. + */ + uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ + uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ + uint64_t fgt_exec[1]; /* HFGITR */ } cp15; =20 struct { @@ -4164,6 +4174,11 @@ static inline bool isar_feature_aa64_tgran64_2(const= ARMISARegisters *id) return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran64(id)); } =20 +static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) !=3D 0; +} + static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 66966869218..20527995359 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1869,6 +1869,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_hcx, cpu)) { valid_mask |=3D SCR_HXEN; } + if (cpu_isar_feature(aa64_fgt, cpu)) { + valid_mask |=3D SCR_FGTEN; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -7546,6 +7549,39 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[3]) }, }; + +static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 2 && + arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGT= EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo fgt_reginfo[] =3D { + { .name =3D "HFGRTR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR])= }, + { .name =3D "HFGWTR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 5, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]= ) }, + { .name =3D "HDFGRTR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]= ) }, + { .name =3D "HDFGWTR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 1, .opc2 =3D 5, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR= ]) }, + { .name =3D "HFGITR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR])= }, +}; #endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -8933,6 +8969,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_scxtnum, cpu)) { define_arm_cp_regs(cpu, scxtnum_reginfo); } + + if (cpu_isar_feature(aa64_fgt, cpu)) { + define_arm_cp_regs(cpu, fgt_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103331; cv=none; d=zohomail.com; s=zohoarc; b=GsnzJ5TjXgkuA+klxvekcc6V42aFyf/iD/0rNuB0Rvmta9pp9oISRcchJLjqXG2V1k8D6Wzt83ewE2twPhGL0HzEL1CQuTTUtyKavLFeZumZQ3Vh18jR+NUUPABdFT1S2/pQbKqZyS0uGOrggWxnz//f4tkRgCRH1e25q4W0jY8= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EVOSpvvgc0c08kjvKAV1mQyt5VqYcuC7dnoU3ab1G88=; b=LHXJmZbE+MBxXfJSuU4qdNm2SpqZK5KymnsaWwe3yLksb+lTVotYMubVULIz5QkCt5 j426TBkdnm+qdexEESum8H36Mt0fTK0fsQ3EFK8mfEhKGNpnr2atIHu0CjwHyias+bnl KhwxLbV9ucam2qOYhWOJVOv+xi6B/D2zabimNqEuDsWv6qtZmIwwuBIo2DiMpjegy08f 90pVukoex4tjopmoFMUGjhRb9Pzu0pdaSPXI2JqVwkB0mRzMxteATQ94aGdJoBOmMTLb iPD+seOVAVqh7vHncmXYh6x6k0fenn3UqCcQtnjgyirh80HBAqoWwcfj9hdcoaDrWOvS ytnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EVOSpvvgc0c08kjvKAV1mQyt5VqYcuC7dnoU3ab1G88=; b=MaazSbDtJ1haZ/aMDDhVlvFlgkyrASmMyytlIvkIzN279fPfZBVyhFvseoJkL1pBMV V6CHjugY3/oWafkbn05v1oUrc5YVQ2KWlLj0vQi2htHZROWLbZL/0otP6AAkXelzXJPo apaRaMVrH3fgdjGHj21JPs9K+4p7UpDuSdMDYedlFBY0mhgd0unYvmpfYwztKFGI1HmN o9iWTnHX8rrcEK4B39nL/Obdx9K6hPxZ5hJJbFoiAmRYSyEJHNFO+UeMcBRd3neLeTVa bX/dUwMxe/gsCv/8gO1IJsPnGpfDnr6k3ytmblh4xsd2Jjhyf6alZVwwcw58oUriMJ4g rqhA== X-Gm-Message-State: AO0yUKW6wPzx1A6Yqb9XDiEW8sqQpA4ui7TLIh5kfuj5YGUSn1QopY5B 5lHCTW7n5TQqUZjDzIyliatahg== X-Google-Smtp-Source: AK7set9FMGyOqsr2ldxoTb2MOIX7Pq8Hopcy+gDFbcytRgu9BV78BU+NBq95EXNqK+FWqrSq1a+fRg== X-Received: by 2002:a5d:5690:0:b0:2bb:ede4:5dd4 with SMTP id f16-20020a5d5690000000b002bbede45dd4mr359860wrv.34.1675103110567; Mon, 30 Jan 2023 10:25:10 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/23] target/arm: Implement FGT trapping infrastructure Date: Mon, 30 Jan 2023 18:24:45 +0000 Message-Id: <20230130182459.3309057-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103333457100003 Content-Type: text/plain; charset="utf-8" Implement the machinery for fine-grained traps on normal sysregs. Any sysreg with a fine-grained trap will set the new field to indicate which FGT register bit it should trap on. FGT traps only happen when an AArch64 EL2 enables them for an AArch64 EL1. They therefore are only relevant for AArch32 cpregs when the cpreg can be accessed from EL0. The logic in access_check_cp_reg() will check this, so it is safe to add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo. The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname which can be used to specify the FGT bit, eg .fgt =3D FGT_AFSR0_EL1 (We assume that there is no bit name duplication across the FGT registers, for brevity's sake.) Subsequent commits will add the .fgt fields to the relevant register definitions and define the FGT_nnn values for them. Note that some of the FGT traps are for instructions that we don't handle via the cpregs mechanisms (mostly these are instruction traps). Those we will have to handle separately. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 72 ++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 1 + target/arm/internals.h | 20 +++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 9 +++++ target/arm/op_helper.c | 30 ++++++++++++++++ target/arm/translate-a64.c | 3 +- target/arm/translate.c | 2 ++ 8 files changed, 138 insertions(+), 1 deletion(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index cb3dc567819..8cc12045af6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -515,6 +515,73 @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) =20 +/* Which fine-grained trap bit register to check, if any */ +FIELD(FGT, TYPE, 10, 3) +FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ +FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */ +FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */ + +/* + * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::f= gt + * fields. We assume for brevity's sake that there are no duplicated + * bit names across the various FGT registers. + */ +#define DO_BIT(REG, BITNAME) \ + FGT_##BITNAME =3D FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT + +/* Some bits have reversed sense, so 0 means trap and 1 means not */ +#define DO_REV_BIT(REG, BITNAME) \ + FGT_##BITNAME =3D FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT + +typedef enum FGTBit { + /* + * These bits tell us which register arrays to use: + * if FGT_R is set then reads are checked against fgt_read[]; + * if FGT_W is set then writes are checked against fgt_write[]; + * if FGT_EXEC is set then all accesses are checked against fgt_exec[]. + * + * For almost all bits in the R/W register pairs, the bit exists in + * both registers for a RW register, in HFGRTR/HDFGRTR for a RO regist= er + * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-ver= sa + * for a WO register. There are unfortunately a couple of exceptions + * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but + * the FGT system only allows trapping of writes, not reads. + * + * Note that we arrange these bits so that a 0 FGTBit means "no trap". + */ + FGT_R =3D 1 << R_FGT_TYPE_SHIFT, + FGT_W =3D 2 << R_FGT_TYPE_SHIFT, + FGT_EXEC =3D 4 << R_FGT_TYPE_SHIFT, + FGT_RW =3D FGT_R | FGT_W, + /* Bit to identify whether trap bit is reversed sense */ + FGT_REV =3D R_FGT_REV_MASK, + + /* + * If a bit exists in HFGRTR/HDFGRTR then either the register being + * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either + * want to trap for both reads and writes or else it's harmless to mark + * it as trap-on-writes. + * If a bit exists only in HFGWTR/HDFGWTR then either the register bei= ng + * trapped is WO, or else it is one of the two oddball special cases + * which are RW but have only a write trap. We mark these as only + * FGT_W so we get the right behaviour for those special cases. + * (If a bit was added in future that provided only a read trap for an + * RW register we'd need to do something special to get the FGT_R bit + * only. But this seems unlikely to happen.) + * + * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if + * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGW= TR. + */ + FGT_HFGRTR =3D FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT), + FGT_HFGWTR =3D FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT), + FGT_HDFGRTR =3D FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), + FGT_HDFGWTR =3D FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), + FGT_HFGITR =3D FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), +} FGTBit; + +#undef DO_BIT +#undef DO_REV_BIT + typedef struct ARMCPRegInfo ARMCPRegInfo; =20 /* @@ -569,6 +636,11 @@ struct ARMCPRegInfo { CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ CPSecureState secure; + /* + * Which fine-grained trap register bit to check, if any. This + * value encodes both the trap register and bit within it. + */ + FGTBit fgt; /* * The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 063024508af..5cc81bec9bf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3170,6 +3170,7 @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) +FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/internals.h b/target/arm/internals.h index d9555309df0..e1e018da463 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1377,4 +1377,24 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState = *env) ((1 << (1 - 1)) | (1 << (2 - 1)) | \ (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) =20 +/* + * Return true if it is possible to take a fine-grained-trap to EL2. + */ +static inline bool arm_fgt_active(CPUARMState *env, int el) +{ + /* + * The Arm ARM only requires the "{E2H,TGE} !=3D {1,1}" test for traps + * that can affect EL0, but it is harmless to do the test also for + * traps on registers that are only accessible at EL1 because if the t= est + * returns true then we can't be executing at EL1 anyway. + * FGT traps only happen when EL2 is enabled and EL1 is AArch64; + * traps from AArch32 only happen for the EL0 is AArch32 case. + */ + return cpu_isar_feature(aa64_fgt, env_archcpu(env)) && + el < 2 && arm_is_el2_enabled(env) && + arm_el_is_aa64(env, 1) && + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE) && + (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FG= TEN)); +} + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index f17f095cbe2..599902016dc 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -130,6 +130,8 @@ typedef struct DisasContext { bool is_nonstreaming; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; + /* True if fine-grained traps are active */ + bool fgt_active; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 20527995359..2389e41bd07 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11689,6 +11689,7 @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMSt= ate *env, int fp_el, if (arm_singlestep_active(env)) { DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); } + return flags; } =20 @@ -11761,6 +11762,10 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } =20 + if (arm_fgt_active(env, el)) { + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + } + if (env->uncached_cpsr & CPSR_IL) { DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } @@ -11895,6 +11900,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMStat= e *env, int el, int fp_el, DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } =20 + if (arm_fgt_active(env, el)) { + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + } + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { /* * Set MTE_ACTIVE if any access may be Checked, and leave clear diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index dec03310ad5..3baf8004f64 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -680,6 +680,36 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *e= nv, uint32_t key, } } =20 + /* + * Fine-grained traps also are lower priority than undef-to-EL1, + * higher priority than trap-to-EL3, and we don't care about priority + * order with other EL2 traps because the syndrome value is the same. + */ + if (arm_fgt_active(env, arm_current_el(env))) { + uint64_t trapword =3D 0; + unsigned int idx =3D FIELD_EX32(ri->fgt, FGT, IDX); + unsigned int bitpos =3D FIELD_EX32(ri->fgt, FGT, BITPOS); + bool rev =3D FIELD_EX32(ri->fgt, FGT, REV); + bool trapbit; + + if (ri->fgt & FGT_EXEC) { + assert(idx < ARRAY_SIZE(env->cp15.fgt_exec)); + trapword =3D env->cp15.fgt_exec[idx]; + } else if (isread && (ri->fgt & FGT_R)) { + assert(idx < ARRAY_SIZE(env->cp15.fgt_read)); + trapword =3D env->cp15.fgt_read[idx]; + } else if (!isread && (ri->fgt & FGT_W)) { + assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); + trapword =3D env->cp15.fgt_write[idx]; + } + + trapbit =3D extract64(trapword, bitpos, 1); + if (trapbit !=3D rev) { + res =3D CP_ACCESS_TRAP_EL2; + goto fail; + } + } + if (likely(res =3D=3D CP_ACCESS_OK)) { return ri; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 52b1b8a1f0a..a47dab4f1dd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1962,7 +1962,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, return; } =20 - if (ri->accessfn) { + if (ri->accessfn || (ri->fgt && s->fgt_active)) { /* Emit code to perform further access permissions checks at * runtime; this may result in an exception. */ @@ -14741,6 +14741,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); + dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl =3D (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; diff --git a/target/arm/translate.c b/target/arm/translate.c index f4bfe55158e..3f51dc6a6bf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4815,6 +4815,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, } =20 if ((s->hstr_active && s->current_el =3D=3D 0) || ri->accessfn || + (ri->fgt && s->fgt_active) || (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) { /* * Emit code to perform further access permissions checks at @@ -9415,6 +9416,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); + dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); =20 if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled =3D 1; --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103205; cv=none; d=zohomail.com; s=zohoarc; b=Ve/WZdK+zCBbC3Gl4nDkN8jhnIMB7pbt6brd4XShefPqnY3HHMJ90KGYgITg6gnXtyNV0fYwwXBvSlnIgIXp9RMUuiJxiyf7qQhaYjB7xj267TZK+provnGp2QhrZwKB7eo3bvz2cHQP/rFfvzfSd4cNTL2eADKxHIk7thRdv3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103205; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ot3R8lszKLTWDHJu832shWug096nL7dcemqGGdqcIoc=; b=UD8E8PTPYv8j69oYQpLCQ9bNUKK/eOJcGKVergZYlDz08N00v6q3zHgA+WQmoIb3zK 8lDR7MEsolbCtkq+rLsc8ljDlAWWadfW1nGO0PVUppfK5h43DIGZx2Roaw6JV0Yvyt4S wBQhZEyaHhQS1znIla1IP3ehyJI3xnTt0SfTO37UqlvBly/yla4sJEl9yaNZwxujpwLp R6+s8vUvcWxFiiLfqtqtCCfeXqrRf10rUZwX0SoNQ7FOYi78LEU5EpSViziwPJVxufc/ mzzDorXA5oKe+eEmUw1Kddz9bFtyO6WSOPChnXw/1ibUgtvdR6s13KzMjyN7cnJKUX2g BQ/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ot3R8lszKLTWDHJu832shWug096nL7dcemqGGdqcIoc=; b=sKifGjH0nun8eGKq5GyW6VTgVhCRc3CssvyOOCSKh2dohNOFHrhOr5pleCaqPwEUd/ kQ5d03SUxll8qe9OE1CvjIFMfVVIEcFG0J/fSby15bb6zqRIcjBH00Nmy0cWxTBFfbcl 6DgZ4FrOXQafEXofewJsXYIamkb6kt0m5VajWwMTxOxWpzOmKojFt1m1wQVyt5iFMkQd YrtgYeChu07F/SFZl7OdIOPbkIyZlldt/15BOQCnrb5Yt+ZS58Q7MwrUt7Ln1cDcg7D4 g5iT9/u1EdNJ33XdWUMO3Hdad6CrzPA9/LGe6ocznZrqYe676Y241tC8rcIeQbQnAWdn 77Sg== X-Gm-Message-State: AO0yUKUS1wMU8AdubTtzg94ZF+70egbMMOHxJdWYvLhxDvyTNW/YkZNW INpD/ZWJSNtDyweQGri3WqdNIRk/x/22k/jo X-Google-Smtp-Source: AK7set9jOREykXFrRpetAfFxKZ3p1YfeFUgCUqExzMPvBcQl9KXd5nNy9wMvNn1hzhixakwafKRCgQ== X-Received: by 2002:a5d:4cd0:0:b0:2bf:cfb4:817c with SMTP id c16-20020a5d4cd0000000b002bfcfb4817cmr12131264wrt.35.1675103111698; Mon, 30 Jan 2023 10:25:11 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/23] target/arm: Mark up sysregs for HFGRTR bits 0..11 Date: Mon, 30 Jan 2023 18:24:46 +0000 Message-Id: <20230130182459.3309057-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103207294100005 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 0..11. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 14 ++++++++++++++ target/arm/helper.c | 17 +++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 8cc12045af6..82f2cefff0a 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -577,6 +577,20 @@ typedef enum FGTBit { FGT_HDFGRTR =3D FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), FGT_HDFGWTR =3D FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), FGT_HFGITR =3D FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), + + /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ + DO_BIT(HFGRTR, AFSR0_EL1), + DO_BIT(HFGRTR, AFSR1_EL1), + DO_BIT(HFGRTR, AIDR_EL1), + DO_BIT(HFGRTR, AMAIR_EL1), + DO_BIT(HFGRTR, APDAKEY), + DO_BIT(HFGRTR, APDBKEY), + DO_BIT(HFGRTR, APGAKEY), + DO_BIT(HFGRTR, APIAKEY), + DO_BIT(HFGRTR, APIBKEY), + DO_BIT(HFGRTR, CCSIDR_EL1), + DO_BIT(HFGRTR, CLIDR_EL1), + DO_BIT(HFGRTR, CONTEXTIDR_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 2389e41bd07..30e54455ac7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -633,6 +633,7 @@ static const ARMCPRegInfo cp_reginfo[] =3D { { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_CONTEXTIDR_EL1, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, @@ -2163,6 +2164,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, .access =3D PL1_R, .accessfn =3D access_tid4, + .fgt =3D FGT_CCSIDR_EL1, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW }, { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, @@ -2179,6 +2181,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid1, + .fgt =3D FGT_AIDR_EL1, .resetvalue =3D 0 }, /* * Auxiliary fault status registers: these also are IMPDEF, and we @@ -2187,10 +2190,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AFSR0_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AFSR1_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * MAIR can just read-as-written because we don't implement caches @@ -4392,6 +4397,7 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AMAIR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, @@ -7041,42 +7047,52 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { { .name =3D "APDAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apda.lo) }, { .name =3D "APDAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apda.hi) }, { .name =3D "APDBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apdb.lo) }, { .name =3D "APDBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apdb.hi) }, { .name =3D "APGAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APGAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apga.lo) }, { .name =3D "APGAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APGAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apga.hi) }, { .name =3D "APIAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apia.lo) }, { .name =3D "APIAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apia.hi) }, { .name =3D "APIBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apib.lo) }, { .name =3D "APIBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, }; =20 @@ -7940,6 +7956,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_tid4, + .fgt =3D FGT_CLIDR_EL1, .resetvalue =3D cpu->clidr }; define_one_arm_cp_reg(cpu, &clidr); --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103230; cv=none; d=zohomail.com; s=zohoarc; b=kYMhCBBOHSXCflOevHy4nOVidLq8regiibMaM8MDJfmWtjTe4TqzxbG0gWDR7isbycEI3lWM6aMaVa2CXgBBsQyngXaAl9APhndPlngPK/b/qB4STyx3bkdX+kbuLdJ4iBTavH0/pYG94e716cci0JCj1ui52pyNv+f5nejle6c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103230; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=24jkTFmaj/fGUGVkla7XQaIA14eLmoW1hHzHZ+N4mAg=; b=KgSVppG6NLO2fftookQXRXxkDS3N9EXhp52fdLgghKR84tDK/nLei+GHSID4iCECEi NWP9uMrtRvwbVmZBu8US7sI/YZjjbnBAXHnIYuxpWGXhIJ/6oXqrk6DfsK8cvLWZO53n AWz6YycEbsA3fMCOkZvFfDh8c4oy3RrSKcAqOvmIF3Wl85Khzvq7fQMn8aXG7F2iSUr3 fKxvNR6W4pg29hOWUXRpC6GYH9hDoX4GsNp6jeDA2BX+dcQZV2dDIZBpON5rIP+0Nv2x oYGKGUh6+IJ3WM26cSoFozBsFDUrvDzrS/6QDuvPPEIjDvEbBD007lzfPHQsTprVhP1y QmHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=24jkTFmaj/fGUGVkla7XQaIA14eLmoW1hHzHZ+N4mAg=; b=TXg/7cfqaBUGtE30iDQPpxqAelljspB7s3pg3xTrvcFRBItP26oammdcHp7bO1Hx0v jpWNvBVe+5lyqD5xetoH1rjeLubdMOehARVcJ45JK4JMAJ0/+iXawZbmld41tD9atOBQ Sj7zibETpRKXggVHOhWHgPf8/Ee4ZNce0FPsP9X7PranAed8mptbeHPuaLw0coRs427U OTelAKh8DgOCi5UZTJT2hYh4Bvax9JTDEqH1bExBscOC+3rk91YdRuhENzGSjCL98kl3 n9/Qdom1WWMPRy3HrBjQcETjPDU3TB0S7ORQqu5LijZupjxSb/oVUASFDio/QtBvCHFG 5BnA== X-Gm-Message-State: AO0yUKV87aIjgnkarFrk3BmXLUsNxNSSN1P8143+QgR+0N2gX+A2uSMG mtItAt29zhhQzWyUdONFGVvEZSaIif8ng9lc X-Google-Smtp-Source: AK7set8/bma/+DeCV1QEZ+vzXsSYI6FTX4162GHzIOApaRf1ygoyhD+giXVg+UkCUdVajV1ArQmmNg== X-Received: by 2002:adf:f88e:0:b0:2bf:b047:d4ab with SMTP id u14-20020adff88e000000b002bfb047d4abmr22462207wrp.13.1675103112616; Mon, 30 Jan 2023 10:25:12 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/23] target/arm: Mark up sysregs for HFGRTR bits 12..23 Date: Mon, 30 Jan 2023 18:24:47 +0000 Message-Id: <20230130182459.3309057-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103232414100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 12..23. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/helper.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 82f2cefff0a..67d87ae8bf5 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -591,6 +591,18 @@ typedef enum FGTBit { DO_BIT(HFGRTR, CCSIDR_EL1), DO_BIT(HFGRTR, CLIDR_EL1), DO_BIT(HFGRTR, CONTEXTIDR_EL1), + DO_BIT(HFGRTR, CPACR_EL1), + DO_BIT(HFGRTR, CSSELR_EL1), + DO_BIT(HFGRTR, CTR_EL0), + DO_BIT(HFGRTR, DCZID_EL0), + DO_BIT(HFGRTR, ESR_EL1), + DO_BIT(HFGRTR, FAR_EL1), + DO_BIT(HFGRTR, ISR_EL1), + DO_BIT(HFGRTR, LORC_EL1), + DO_BIT(HFGRTR, LOREA_EL1), + DO_BIT(HFGRTR, LORID_EL1), + DO_BIT(HFGRTR, LORN_EL1), + DO_BIT(HFGRTR, LORSA_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 30e54455ac7..c059935d0e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -869,6 +869,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, + .fgt =3D FGT_CPACR_EL1, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, }; @@ -2170,6 +2171,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tid4, + .fgt =3D FGT_CSSELR_EL1, .writefn =3D csselr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, @@ -2233,6 +2235,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, { .name =3D "ISR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, + .fgt =3D FGT_ISR_EL1, .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, /* 32 bit ITLB invalidates */ { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, @@ -4135,6 +4138,7 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_FAR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, }; @@ -4143,6 +4147,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_ESR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, @@ -5215,6 +5220,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, + .fgt =3D FGT_DCZID_EL0, .readfn =3D aa64_dczid_read }, { .name =3D "DC_ZVA", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 1, @@ -7005,22 +7011,27 @@ static const ARMCPRegInfo lor_reginfo[] =3D { { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORSA_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LOREA_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORN_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORC_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, .access =3D PL1_R, .accessfn =3D access_lor_ns, + .fgt =3D FGT_LORID_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 @@ -8619,6 +8630,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "CTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 0, .crm =3D = 0, .access =3D PL0_R, .accessfn =3D ctr_el0_access, + .fgt =3D FGT_CTR_EL0, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ { .name =3D "TCMTR", --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103242; cv=none; d=zohomail.com; s=zohoarc; b=COCqPYIC51rr4uFsl+JCVXZpMEh9xWP4rRGy9tyNa9/sQr4D52cQp1quPixBDL/OzByOH4loHmuwLoq2JFpamg4C64OEnZM4fNm3jLJrBGZ0cfUaErJ1CzL7hp/aOK0ugh3ICgz2nCiloGZsyzzRphYlDahF4kB4owZxsPJkL6g= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uBNTWQQLxGxHOy4+W6TEzUkaANrDoD5kHnZ+7qxh+v4=; b=exQuGf7YJfLzeq+F5yE6uSyYsWQ5xCjQiCYLX1olWVI7Mx9tFTUxH9NxSFk2tOUoBe kEZ/nteEooX03Bqam6wtHC7H9qmUC8Kn3zARGYCyFhWhrrGVw8cxDlTIJPvkutO3Msas /WVHscZEzCZA7hgPY4Rz+B889QGj0vi02zcK91Uvt58SySLXjABXzLM4axNdJCbDoS02 v/9OosqkDEqzTVbgMrIrDUCYie5WVeMbsjlPe5adg7xiWXx8aj/EJKPidrtgcrNIDWYH 0TT7yiSiQQORK+tJR3+5KXVYgaNhS1gk0tyVZitCtyZcrPGzarL+ZwG5X4i/SajCNmaL ZnlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uBNTWQQLxGxHOy4+W6TEzUkaANrDoD5kHnZ+7qxh+v4=; b=K9i/fdBlsv6anrWYMXmttWgXCUz/8fkSGJw0in0EHwmi82U/G7UBfgWJxJAE8D5ohg KM6ZM5IEkHck2dWKmzHAFOmaFkAiiOUPQ/i3UasnWA0yt+dl4q2HqrTr42Tse/eFV8cN X65fOZTd9KDLCbIOVvdP8rCmxK3EmgJMeQ+PSYPC33NfqnJDioKt6WZp3r7EqL+rCvGq JQuHCEGk70QpJ58wLmhuqRvqu8ck9YXdlfWbfc41iWoMr1krEo3fsPFtM9sa3Eeh3W3Q 7EjhITULzaBfIzYcrdnC96lXHCuWVjIVTObR1YlUMiP1uDoqpcmPb8a8u1grVt7PlGvO d8NA== X-Gm-Message-State: AO0yUKUYvEew75wYC3ZW5Dfj9GDNCILYgoPeK00ceMJTCULjezNxh2Ms 7e9znTgkyD8+Xv+jH5KcfqpGoA== X-Google-Smtp-Source: AK7set9j8p8UNzIIfkzs6Mwnb+sCP/UxS9q873PnOJpU3WCFVaxMy6Cat5TOQ+WxH1N7We8HaPSOAQ== X-Received: by 2002:a5d:5908:0:b0:2bf:f027:3c30 with SMTP id v8-20020a5d5908000000b002bff0273c30mr3160086wrd.56.1675103113510; Mon, 30 Jan 2023 10:25:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/23] target/arm: Mark up sysregs for HFGRTR bits 24..35 Date: Mon, 30 Jan 2023 18:24:48 +0000 Message-Id: <20230130182459.3309057-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103244571100005 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 24..35. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/helper.c | 14 ++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 67d87ae8bf5..1b219242d5d 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -603,6 +603,18 @@ typedef enum FGTBit { DO_BIT(HFGRTR, LORID_EL1), DO_BIT(HFGRTR, LORN_EL1), DO_BIT(HFGRTR, LORSA_EL1), + DO_BIT(HFGRTR, MAIR_EL1), + DO_BIT(HFGRTR, MIDR_EL1), + DO_BIT(HFGRTR, MPIDR_EL1), + DO_BIT(HFGRTR, PAR_EL1), + DO_BIT(HFGRTR, REVIDR_EL1), + DO_BIT(HFGRTR, SCTLR_EL1), + DO_BIT(HFGRTR, SCXTNUM_EL1), + DO_BIT(HFGRTR, SCXTNUM_EL0), + DO_BIT(HFGRTR, TCR_EL1), + DO_BIT(HFGRTR, TPIDR_EL1), + DO_BIT(HFGRTR, TPIDRRO_EL0), + DO_BIT(HFGRTR, TPIDR_EL0), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index c059935d0e6..9f6d9e2a3c9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2206,6 +2206,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_MAIR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, @@ -2349,25 +2350,30 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { { .name =3D "TPIDR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 2, .crn =3D 13, .crm =3D 0, .access =3D PL0_RW, + .fgt =3D FGT_TPIDR_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalu= e =3D 0 }, { .name =3D "TPIDRURW", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 2, .access =3D PL0_RW, + .fgt =3D FGT_TPIDR_EL0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrurw_s), offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = }, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, .access =3D PL0_R | PL1_W, + .fgt =3D FGT_TPIDRRO_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el[0]), .resetvalue =3D 0}, { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, .access =3D PL0_R | PL1_W, + .fgt =3D FGT_TPIDRRO_EL0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D 13, .crm =3D 0, .access =3D PL1_RW, + .fgt =3D FGT_TPIDR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalu= e =3D 0 }, { .name =3D "TPIDRPRW", .opc1 =3D 0, .cp =3D 15, .crn =3D 13, .crm =3D= 0, .opc2 =3D 4, .access =3D PL1_RW, @@ -4164,6 +4170,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_TCR_EL1, .writefn =3D vmsa_tcr_el12_write, .raw_writefn =3D raw_write, .resetvalue =3D 0, @@ -5399,6 +5406,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 7, .crm =3D 4, .opc2 =3D 0, .access =3D PL1_RW, .resetvalue =3D 0, + .fgt =3D FGT_PAR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]), .writefn =3D par_write }, #endif @@ -7562,10 +7570,12 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { { .name =3D "SCXTNUM_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, .access =3D PL0_RW, .accessfn =3D access_scxtnum, + .fgt =3D FGT_SCXTNUM_EL0, .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[0]) }, { .name =3D "SCXTNUM_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, .access =3D PL1_RW, .accessfn =3D access_scxtnum, + .fgt =3D FGT_SCXTNUM_EL1, .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, @@ -8604,6 +8614,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, + .fgt =3D FGT_MIDR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 7 : AArch32 aliases o= f MIDR */ @@ -8614,6 +8625,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, .access =3D PL1_R, .accessfn =3D access_aa64_tid1, + .fgt =3D FGT_REVIDR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; ARMCPRegInfo id_v8_midr_alias_cp_reginfo =3D { @@ -8785,6 +8797,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo mpidr_cp_reginfo[] =3D { { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, + .fgt =3D FGT_MPIDR_EL1, .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, }; #ifdef CONFIG_USER_ONLY @@ -8884,6 +8897,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_SCTLR_EL1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, --=20 2.34.1 From nobody Fri Apr 19 18:42:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uE1+7b7gus+hNDmeHdUGfNEuDyGv3C2iBvjQ8HFmN3M=; b=uhf5Rof4IxtTqsfdvUIRiVRRRk2K2j77EYOBa1xh2gchWP5FYp7UGaKk1tMr5swKeD SCOYTYn6eP5XM++d/Bav4bcgpAVkt1V4f0B18JP27xhz8qcoT5umkjiE74kM2g3FVp2G my6ueZ2wkdM+BV2zntJp2q+gJnpBy5nJqu2eytmVeHOPSPJX3uSDWVQIHKsiJuV0fHzv k+3UaKMoay4uEsE8ykSXN8JHBNIGVeY1Vh2uGmka68JOoT5S/Oti4hm5MtRPbimWY5+E VfbH1u8op0SnfSuCncqgTcB3sKL29JE4P9BgKD3wc+/nmaGqUZ4m9edUm0iOwf2nUbzE ziNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uE1+7b7gus+hNDmeHdUGfNEuDyGv3C2iBvjQ8HFmN3M=; b=dlkq0kvb850MA8qFMCivMpC9lWtZ5RCLRCHxxnseQBfIlWjD9/jefYm90n/Ipbvx/F KnpVl0zOa54awWovH+BNxuDYKwRLOMdXhl/sMeOiljBEgxU7Jb23sDSWGAcubCW71v9b X7bTr/ABdUHqIMiQ4vgwv3M9sCjjRFIghzzbCIYd1F9PkuNgihuLt7Zcm+BEDywuNnom ckuOcbFcDUV71WNCeZT2H25OAlT6k5BD92tkHsrXYBJ2EtfC2FEtU5vGcvm8q7nVwToc KLbzufuXF1W8xPeUds24mO9ps2H+P5dWZYWPrhosOFHptvIpkiCRcANjkLVrkFj4XJHJ HOsQ== X-Gm-Message-State: AFqh2kqLJie68nylirvQLTIriQsqPk+ZXEQpSc+s3jLgdVd2K9pKHSjh FJEOefh6Ani2D/gCufKNSvbJjBiwsd7hfjMK X-Google-Smtp-Source: AMrXdXsa07wUeNFiMV5ArHfohJS9piJWFbGXJ7c6up9Rm0Ht1XuI6igAltzP6P+geU4Qhqowo+ZnkQ== X-Received: by 2002:a05:6000:38a:b0:2be:4c32:a7df with SMTP id u10-20020a056000038a00b002be4c32a7dfmr39515156wrf.63.1675103114414; Mon, 30 Jan 2023 10:25:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/23] target/arm: Mark up sysregs for HFGRTR bits 36..63 Date: Mon, 30 Jan 2023 18:24:49 +0000 Message-Id: <20230130182459.3309057-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103218312100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 36..63. Of these, some correspond to RAS registers which we implement as always-UNDEF: these don't need any extra handling for FGT because the UNDEF-to-EL1 always takes priority over any theoretical FGT-trap-to-EL2. Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part of the FEAT_LS64_ACCDATA feature which we don't yet implement. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 7 +++++++ hw/intc/arm_gicv3_cpuif.c | 2 ++ target/arm/helper.c | 10 ++++++++++ 3 files changed, 19 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1b219242d5d..fef8ad08acc 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -615,6 +615,13 @@ typedef enum FGTBit { DO_BIT(HFGRTR, TPIDR_EL1), DO_BIT(HFGRTR, TPIDRRO_EL0), DO_BIT(HFGRTR, TPIDR_EL0), + DO_BIT(HFGRTR, TTBR0_EL1), + DO_BIT(HFGRTR, TTBR1_EL1), + DO_BIT(HFGRTR, VBAR_EL1), + DO_BIT(HFGRTR, ICC_IGRPENN_EL1), + DO_BIT(HFGRTR, ERRIDR_EL1), + DO_REV_BIT(HFGRTR, NSMPRI_EL1), + DO_REV_BIT(HFGRTR, NTPIDR2_EL0), } FGTBit; =20 #undef DO_BIT diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index b17b29288c7..6a3ca482fff 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2376,6 +2376,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 6, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .access =3D PL1_RW, .accessfn =3D gicv3_fiq_access, + .fgt =3D FGT_ICC_IGRPENN_EL1, .readfn =3D icc_igrpen_read, .writefn =3D icc_igrpen_write, }, @@ -2384,6 +2385,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 7, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .access =3D PL1_RW, .accessfn =3D gicv3_irq_access, + .fgt =3D FGT_ICC_IGRPENN_EL1, .readfn =3D icc_igrpen_read, .writefn =3D icc_igrpen_write, }, diff --git a/target/arm/helper.c b/target/arm/helper.c index 9f6d9e2a3c9..a48b022def6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4158,12 +4158,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_TTBR0_EL1, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_TTBR1_EL1, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, @@ -6488,6 +6490,10 @@ static void disr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t val) * ERRSELR_EL1 * may generate UNDEFINED, which is the effect we get by not * listing them at all. + * + * These registers have fine-grained trap bits, but UNDEF-to-EL1 + * is higher priority than FGT-to-EL2 so we do not need to list them + * in order to check for an FGT. */ static const ARMCPRegInfo minimal_ras_reginfo[] =3D { { .name =3D "DISR_EL1", .state =3D ARM_CP_STATE_BOTH, @@ -6497,6 +6503,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] =3D { { .name =3D "ERRIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_R, .accessfn =3D access_terr, + .fgt =3D FGT_ERRIDR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, @@ -6819,6 +6826,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "TPIDR2_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 5, .access =3D PL0_RW, .accessfn =3D access_tpidr2, + .fgt =3D FGT_NTPIDR2_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr2_el0) }, { .name =3D "SVCR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 2, @@ -6856,6 +6864,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "SMPRI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 4, .access =3D PL1_RW, .accessfn =3D access_esm, + .fgt =3D FGT_NSMPRI_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "SMPRIMAP_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 5, @@ -8884,6 +8893,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, .access =3D PL1_RW, .writefn =3D vbar_write, + .fgt =3D FGT_VBAR_EL1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, --=20 2.34.1 From nobody Fri Apr 19 18:42:09 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IWPQN4vkNjJzt63xX8IOcIRiw+Y6TTVa6ogjDXQC6Lw=; b=es3iru9LgM464huXRMtdf5rQzPnVCDTY53vxWp1T86SIkAANwKh/+LbB3ndX3Otnp+ xDskOj/em8bJ82Rahoh4P8HRccojEDh3V/EyIxbR5Mxa4N0d7E9XcV9MojruYNpVrFRH Vkj9iHWd1Z0mxrzlQmKWpvZmIQferPjAz639vYncrmLgqE9naE2a7SrPy56mQUkcy+ut gv7isT4xnwWmfhd+3pwyS6mNzVxKi7OO9BA2TjqnW3/cXyRoQ+ER51VjCobz6MZYAd1q 7ql6m5SpdTRh4H52HwmFZf7rgjrrn0dBZCk6zQ2EI4l593xtMAWnUZgetagmqKDBNIfy q8ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IWPQN4vkNjJzt63xX8IOcIRiw+Y6TTVa6ogjDXQC6Lw=; b=lKb1LobO4d2L2LA1+YHwY3XB8YgNi7WJ5TgNwnlyrZlSOPbKPxm0HGa9YZz1wsGmMl HqiFyeL9WGO4Vg8HW9Rj50wKvvt2tN4yoLyUYxbjRRJJNNL7S/iy+MJZvNXXrO/KvuYS atONCVIYpiqEAJputNeUH17c8h37xWNB6FxnJ6+s81UVuV8eCJKyCw/j90M8U9lRdiX/ HOqVwrFzSLnX5s4Vy1gqpfneIXFkEDyeR4W+Sj7FPTAAgfku2eL4w+Bly+m20y+DyN68 NhmSRbsBE27oRmAJd9iPiczVOQCrBMW89gsb4HJNGYgoZRKhxWoXMkEMLUepQxJcrFkK I3AQ== X-Gm-Message-State: AO0yUKWaD0mjIjwISI2tglGzeN6evi4xNfZ4a9B+VZJ4vE1IKdEcz2Ey AkZcaR0kGtXwcsyKnKe4s7caZQ== X-Google-Smtp-Source: AK7set8GqAQ+oCVD7AxTtm77D59wfXVaEPac3FhHn8LjQkc8Z0U8sgpbvsRMKrsorKfgtW7khNFHaQ== X-Received: by 2002:adf:f409:0:b0:2bf:d411:a4f6 with SMTP id g9-20020adff409000000b002bfd411a4f6mr10676407wro.1.1675103115217; Mon, 30 Jan 2023 10:25:15 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/23] target/arm: Mark up sysregs for HDFGRTR bits 0..11 Date: Mon, 30 Jan 2023 18:24:50 +0000 Message-Id: <20230130182459.3309057-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103295140100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitons for the registers trapped by HDFGRTR/HDFGWTR bits 0..11. These cover various debug related registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/debug_helper.c | 11 +++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index fef8ad08acc..7c4d07ed9c6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -622,6 +622,18 @@ typedef enum FGTBit { DO_BIT(HFGRTR, ERRIDR_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), + + /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ + DO_BIT(HDFGRTR, DBGBCRN_EL1), + DO_BIT(HDFGRTR, DBGBVRN_EL1), + DO_BIT(HDFGRTR, DBGWCRN_EL1), + DO_BIT(HDFGRTR, DBGWVRN_EL1), + DO_BIT(HDFGRTR, MDSCR_EL1), + DO_BIT(HDFGRTR, DBGCLAIM), + DO_BIT(HDFGWTR, OSLAR_EL1), + DO_BIT(HDFGRTR, OSLSR_EL1), + DO_BIT(HDFGRTR, OSECCR_EL1), + DO_BIT(HDFGRTR, OSDLR_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cced3f168d0..b106746b0e1 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -672,6 +672,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_MDSCR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), .resetvalue =3D 0 }, /* @@ -702,6 +703,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "OSECCR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_OSECCR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as @@ -717,16 +719,19 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSLAR_EL1, .writefn =3D oslar_write }, { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, .access =3D PL1_R, .resetvalue =3D 10, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSLSR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, /* Dummy OSDLR_EL1: 32-bit Linux will read this */ { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, .access =3D PL1_RW, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSDLR_EL1, .writefn =3D osdlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.osdlr_el1) }, /* @@ -763,10 +768,12 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 = =3D 6, .type =3D ARM_CP_ALIAS, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGCLAIM, .writefn =3D dbgclaimset_write, .readfn =3D dbgclaimset_read }, { .name =3D "DBGCLAIMCLR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 = =3D 6, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGCLAIM, .writefn =3D dbgclaimclr_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgclaim) }, }; @@ -1127,12 +1134,14 @@ void define_debug_regs(ARMCPU *cpu) { .name =3D dbgbvr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGBVRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write }, { .name =3D dbgbcr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGBCRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write }, @@ -1149,12 +1158,14 @@ void define_debug_regs(ARMCPU *cpu) { .name =3D dbgwvr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGWVRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write }, { .name =3D dbgwcr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGWCRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write }, --=20 2.34.1 From nobody Fri Apr 19 18:42:09 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Bits 12..22 and bit 58 are for PMU registers. The remaining bits in HDFGRTR/HDFGWTR are for traps on registers that are part of features we don't implement: Bits 23..32 and 63 : FEAT_SPE Bits 33..48 : FEAT_ETE Bits 50..56 : FEAT_TRBE Bits 59..61 : FEAT_BRBE Bit 62 : FEAT_SPEv1p2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7c4d07ed9c6..c37e013b8f3 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -634,6 +634,18 @@ typedef enum FGTBit { DO_BIT(HDFGRTR, OSLSR_EL1), DO_BIT(HDFGRTR, OSECCR_EL1), DO_BIT(HDFGRTR, OSDLR_EL1), + DO_BIT(HDFGRTR, PMEVCNTRN_EL0), + DO_BIT(HDFGRTR, PMEVTYPERN_EL0), + DO_BIT(HDFGRTR, PMCCFILTR_EL0), + DO_BIT(HDFGRTR, PMCCNTR_EL0), + DO_BIT(HDFGRTR, PMCNTEN), + DO_BIT(HDFGRTR, PMINTEN), + DO_BIT(HDFGRTR, PMOVS), + DO_BIT(HDFGRTR, PMSELR_EL0), + DO_BIT(HDFGWTR, PMSWINC_EL0), + DO_BIT(HDFGWTR, PMCR_EL0), + DO_BIT(HDFGRTR, PMMIR_EL1), + DO_BIT(HDFGRTR, PMCEIDN_EL0), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index a48b022def6..2e494b8f924 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2035,21 +2035,25 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenset_write, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .raw_writefn =3D raw_write }, { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, .type =3D = ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL0_RW, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .writefn =3D pmcntenclr_write, .type =3D ARM_CP_ALIAS | ARM_CP_IO }, { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, @@ -2057,41 +2061,49 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .fgt =3D FGT_PMSWINC_EL0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .writefn =3D pmswinc_write }, { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .fgt =3D FGT_PMSWINC_EL0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .writefn =3D pmswinc_write }, { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fgt =3D FGT_PMSELR_EL0, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), .accessfn =3D pmreg_access_selr, .writefn =3D pmselr_write, .raw_writefn =3D raw_write}, { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, .access =3D PL0_RW, .accessfn =3D pmreg_access_selr, + .fgt =3D FGT_PMSELR_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, + .fgt =3D FGT_PMCCNTR_EL0, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, .accessfn =3D pmreg_access_ccntr }, { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, + .fgt =3D FGT_PMCCNTR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, @@ -2099,32 +2111,38 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCCFILTR_EL0, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .resetvalue =3D 0, }, { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCCFILTR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), .resetvalue =3D 0, }, { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMEVTYPERN_EL0, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMEVTYPERN_EL0, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access_xevcntr, + .fgt =3D FGT_PMEVCNTRN_EL0, .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access_xevcntr, + .fgt =3D FGT_PMEVCNTRN_EL0, .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, @@ -2139,6 +2157,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), .resetvalue =3D 0, @@ -2146,18 +2165,21 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, .resetvalue =3D 0x0 }, { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenclr_write, }, { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenclr_write }, @@ -2293,6 +2315,7 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { /* PMOVSSET is not implemented in v7 before v7ve */ { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, @@ -2300,6 +2323,7 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, @@ -6884,6 +6908,7 @@ static void define_pmu_regs(ARMCPU *cpu) ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_RW, + .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), .accessfn =3D pmreg_access, .writefn =3D pmcr_write, @@ -6893,6 +6918,7 @@ static void define_pmu_regs(ARMCPU *cpu) .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), .resetvalue =3D cpu->isar.reset_pmcr_el0, @@ -6910,23 +6936,27 @@ static void define_pmu_regs(ARMCPU *cpu) { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fgt =3D FGT_PMEVCNTRN_EL0, .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, .accessfn =3D pmreg_access_xevcntr }, { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess_xevcntr, .type =3D ARM_CP_IO, + .fgt =3D FGT_PMEVCNTRN_EL0, .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, .raw_readfn =3D pmevcntr_rawread, .raw_writefn =3D pmevcntr_rawwrite }, { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fgt =3D FGT_PMEVTYPERN_EL0, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .accessfn =3D pmreg_access }, { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .fgt =3D FGT_PMEVTYPERN_EL0, .type =3D ARM_CP_IO, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .raw_writefn =3D pmevtyper_rawwrite }, @@ -6942,10 +6972,12 @@ static void define_pmu_regs(ARMCPU *cpu) { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, }; define_arm_cp_regs(cpu, v81_pmu_regs); @@ -6955,6 +6987,7 @@ static void define_pmu_regs(ARMCPU *cpu) .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, + .fgt =3D FGT_PMMIR_EL1, .resetvalue =3D 0 }; define_one_arm_cp_reg(cpu, &v84_pmmir); @@ -8251,18 +8284,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D cpu->pmceid0 }, { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D cpu->pmceid1 }, }; #ifdef CONFIG_USER_ONLY --=20 2.34.1 From nobody Fri Apr 19 18:42:09 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103243; cv=none; d=zohomail.com; s=zohoarc; b=DYH/Io+Q7f447V4UXaxgBCFtniaXRy+AoW2trAPyiPDtlCQjIwicpIxDp8a8CLqoZx2Ujby1vRNorpIAk2DpeNywFMZc7to0qq7JHtdiGWY9qMhJ0zyk4632R5zlPhskcz3xRgmom53mup9pgjry9GXHijYGEEkgXkdtRxXrXrw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103243; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UzHZUC2Q/Mer8SDW1LpV1AWKuWIz5z5lMzrsLDlqH9k=; b=GVVR/fc1lytWMg94yq8DaEsF+or+vFyshvXYBlTUq8ZFEVcQr6w/edCGL9Mz5upQzJ MIXWqT6nCC1fALdrJDytD0iiyIZ0UzbO3cxfQN8a4DSk6rb4ZhrHGuEKeGCbyRM06fBU kFqIv5jXs3UlLt3cpN8UI6LxoMb0poLUfW6Dyq8Y8kycy6q27CRdbe/9yRMrH0nAagzg BjlPCdjlkWplNtbKK7prfnwCRe/7wHbk30jj/MiO77r77NYN9NOpk7BiEqBe1QgwLZHM fp2+mWauKGHFSKRtqP3bPB1znVUnHEh9ttxJjHICLC5xJh10/roeyHTEWGFHhCsewpR3 tktg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UzHZUC2Q/Mer8SDW1LpV1AWKuWIz5z5lMzrsLDlqH9k=; b=7nGElZnOeeEgdfew7fG0I2qPKMm+qDR4tTDW+RLMhL9Ix6qq3a8eBT++D/7ButDqt1 x7i67VcbOomx/X/2GZkAHFC78HY2RFTs3AXvM1bhFQyqaXdVjf4oo/jprre6C6xvP6i/ gGnxDWlGhD2XigeRs7ifxpfkueWaaAAy5ugklkejdJNuYLbbUC4I+ox6qFpoBBV2ytee /v4lhmEmDOEWFyvjye+j6M7AKetFXHTXTV61lSD+SlVN2xq4bvt2qZ6BYHHbh70EzEGd bmpanln9MMVvA/TEE3PcaDDLkba8+bLYigIWOSlj+RGV4ICe54xm/AZfNRKeBeY76VjJ Btlg== X-Gm-Message-State: AO0yUKXiNhGPnnne/vszWADim4XA7zWcrUMa/une89kQCq1PAoNMu83M 1dAOOPoDOUWkwxA+RopQJ3soBb2z/yaiqK6x X-Google-Smtp-Source: AK7set8AfYFBv7MSr5zWTk2MI8HpJviYTwSI14TzQzzniPfNUQK0XK+xtvbQg7H4E1SiPxEyqFwRAw== X-Received: by 2002:a05:6000:143:b0:2bf:b88b:aae8 with SMTP id r3-20020a056000014300b002bfb88baae8mr343749wrx.50.1675103117499; Mon, 30 Jan 2023 10:25:17 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/23] target/arm: Mark up sysregs for HFGITR bits 0..11 Date: Mon, 30 Jan 2023 18:24:52 +0000 Message-Id: <20230130182459.3309057-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103244594100006 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 0..11. These bits cover various cache maintenance operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 14 ++++++++++++++ target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c37e013b8f3..6596c2a1233 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -646,6 +646,20 @@ typedef enum FGTBit { DO_BIT(HDFGWTR, PMCR_EL0), DO_BIT(HDFGRTR, PMMIR_EL1), DO_BIT(HDFGRTR, PMCEIDN_EL0), + + /* Trap bits in HFGITR_EL2, starting from bit 0 */ + DO_BIT(HFGITR, ICIALLUIS), + DO_BIT(HFGITR, ICIALLU), + DO_BIT(HFGITR, ICIVAU), + DO_BIT(HFGITR, DCIVAC), + DO_BIT(HFGITR, DCISW), + DO_BIT(HFGITR, DCCSW), + DO_BIT(HFGITR, DCCISW), + DO_BIT(HFGITR, DCCVAU), + DO_BIT(HFGITR, DCCVAP), + DO_BIT(HFGITR, DCCVADP), + DO_BIT(HFGITR, DCCIVAC), + DO_BIT(HFGITR, DCZVA), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 2e494b8f924..51866ba70e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5261,6 +5261,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, @@ -5270,21 +5271,26 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIALLUIS, .accessfn =3D access_ticab }, { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIALLU, .accessfn =3D access_tocu }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIVAU, .accessfn =3D access_tocu }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, + .fgt =3D FGT_DCIVAC, .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, + .fgt =3D FGT_DCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, @@ -5292,17 +5298,21 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, + .fgt =3D FGT_DCCSW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCVAU, .accessfn =3D access_tocu }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, + .fgt =3D FGT_DCCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, @@ -7413,6 +7423,7 @@ static const ARMCPRegInfo dcpop_reg[] =3D { { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, }; =20 @@ -7420,6 +7431,7 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, }; #endif /*CONFIG_USER_ONLY*/ @@ -7499,28 +7511,36 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "DC_IGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL1_W, + .fgt =3D FGT_DCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_IGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, + .fgt =3D FGT_DCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_IGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL1_W, + .fgt =3D FGT_DCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_IGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, + .fgt =3D FGT_DCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, + .fgt =3D FGT_DCCSW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, + .fgt =3D FGT_DCCSW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CIGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, + .fgt =3D FGT_DCCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, + .fgt =3D FGT_DCCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, }; =20 @@ -7542,26 +7562,32 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[]= =3D { { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_GVA", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, @@ -7569,6 +7595,7 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, { .name =3D "DC_GZVA", .state =3D ARM_CP_STATE_AA64, @@ -7577,6 +7604,7 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MAYX9K/USg+OVRf9ZuIQOjuYSB6K+peI9C4rgnqGo8A=; b=MluMrtj5ve5Ko5h5H2tr99El3EC7BzgY/Ps9e82nzxZz/ip5szJnDgUWcmu5o/ZtPw /dH8z14ODI1/ydttoY5n3icEGmL2X8o0ecKaCgrsIYDP6f2y3zdfDo0dRgzUNQFYl1xl 4QjGLkdkDGPF8TYg68Q54f7kH99QTk36Tm5nQxQgE+49a2xMr8KehH+XHz5xwg4CS20V p0474pIIkaVTcNA1A24oDVyQn4Gj+1yfUpR3imFtqkZ3lCUhNqjWV0jjcC8yUcuvlWiV v4PEMiO3hqZk+ouWfj3lkVN1XWcULb5IHPGBqPH0sraicG+jUM9snPQvlEKNONnQYPOy Fm6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MAYX9K/USg+OVRf9ZuIQOjuYSB6K+peI9C4rgnqGo8A=; b=Dqr7Vo5Xpk2YzFCRC+uyWzC9PjJLEXRzQDB/QwM9t9o9e+bAPXjsGqUqClql8sNZrb S3K0aj76SBP3S4EpDYk7uC0CssR6HfrCyACOz2Wpvr5pFgH8LG7dnrmwknhxLlcwG71L HAdjQavQO6A7/zHg25QfqAwuVYIep/Y28c+KTlxygnpRgLO8FET9VGMdcKVowrLiQrac 3dsLB+DBFwVCh1XzkFPzTlt4jHylUeAgKSS1ANpbYjs0AKZtMWkOMxeZY1ohE7O54Vms 6ni/xI4o3kL1a4KNhw5JziOVnRSACSXioUQD1AZcjBVg3KcFDuVFWt6gg03pLkMCpQLm W74w== X-Gm-Message-State: AO0yUKWu3ydiRTtyNLEFRsSw/LcXZ7NwbgFqP9uzjNGXLR+KM2oeBd/p Nm0mPAx1zjUsDwOs8YFLDNZKKg== X-Google-Smtp-Source: AK7set+uz0uC3EQGJjZMtCN50Uk7Fi2K+yoKdCiAGu1XsH19ADHhMPl3d2neyI4gu329oE60eLDSOQ== X-Received: by 2002:a5d:595e:0:b0:2bf:ee58:72ae with SMTP id e30-20020a5d595e000000b002bfee5872aemr3591306wri.50.1675103118598; Mon, 30 Jan 2023 10:25:18 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/23] target/arm: Mark up sysregs for HFGITR bits 12..17 Date: Mon, 30 Jan 2023 18:24:53 +0000 Message-Id: <20230130182459.3309057-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103222319100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 12..17. These bits cover AT address translation instructions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 6 ++++++ target/arm/helper.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 6596c2a1233..1f74308ef5d 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -660,6 +660,12 @@ typedef enum FGTBit { DO_BIT(HFGITR, DCCVADP), DO_BIT(HFGITR, DCCIVAC), DO_BIT(HFGITR, DCZVA), + DO_BIT(HFGITR, ATS1E1R), + DO_BIT(HFGITR, ATS1E1W), + DO_BIT(HFGITR, ATS1E0R), + DO_BIT(HFGITR, ATS1E0W), + DO_BIT(HFGITR, ATS1E1RP), + DO_BIT(HFGITR, ATS1E1WP), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 51866ba70e9..8b9c7fcc3a4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5400,18 +5400,22 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1R, .writefn =3D ats_write64 }, { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1W, .writefn =3D ats_write64 }, { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E0R, .writefn =3D ats_write64 }, { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E0W, .writefn =3D ats_write64 }, { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, @@ -7880,10 +7884,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] =3D { { .name =3D "AT_S1E1RP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1RP, .writefn =3D ats_write64 }, { .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1WP, .writefn =3D ats_write64 }, }; =20 --=20 2.34.1 From nobody Fri Apr 19 18:42:09 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103345; cv=none; d=zohomail.com; s=zohoarc; b=TI21KUtIXxp9k1v4psLr1KM+ips8NHBLBT4YrKl+Zgw9NZomvzaaznd6hZ2rK7Dma7N8oNFMOXQVlBUarSOVJTOk0HF77ZkYadpMil3GNrzNMqz5qf1TzlcN6DKFtTuR5khyau1eL4EE+H4BRVvkQUQyXJX1QmMgJgoPA2e9rPI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103345; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F++zAkK2fRYjHug1M8O2hF79PTDP/GEk7kbXJXgLTXs=; b=V2lIMrsaPyAb0uA4sdvhthPesJVkPjIh7+nMsgikBoj1++BtLsnyDICyjV1XkqK20rZumcPOGccfLFXBEMEf1uysq4CJT5UTpXt6SDgQLrAJOe2tMP3Jlk0NGAA6KjEm3i9bkEDD8DEGTjQSa53D+87FeBacy61+I9+BW10mpCo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103345056842.7758245623435; Mon, 30 Jan 2023 10:29:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqR-0001DR-52; Mon, 30 Jan 2023 13:25:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYqL-00018h-Ka for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:25 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYqG-0008QF-OS for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:25 -0500 Received: by mail-wr1-x42f.google.com with SMTP id d14so11975840wrr.9 for ; Mon, 30 Jan 2023 10:25:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=F++zAkK2fRYjHug1M8O2hF79PTDP/GEk7kbXJXgLTXs=; b=mATVpeygNuIZRd3iWVb0y3jQ0hpk3p3Z7GGJQeIgTPS04gYj6e4RMEhb//3uHSs6DK aciOOTXu8XmzLsZ5ut48HctoNoUeF+zrIO+kii3WhPngMhNvRCxfJNXYfB+OYqjl5MWz NCI1zt2QI16hlpPQMh5Oi8PjwyLfheOaW3vAIvlJRjjOYGouSEVtNwooUE/Lo2fSezU0 QHPcRohVu8AdfNfXZUbsMy9/vzfCY3aNF8svuxFeLn5edgEmvCquC+x2nr+gajRJ6MFp s/sf/Z7d6667fZYbq9snVYUS+0k85bbbgL2p15u5wqUQSN5N8NHA/NqNle/q39lVC9Uc TmpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F++zAkK2fRYjHug1M8O2hF79PTDP/GEk7kbXJXgLTXs=; b=mmWZy8P/pOWurYZ/EiNoD4URNM2RIf/HYWogCUKwueiBZ/AzCNeqQBXEcBn3Kcq+3h eB7gZpwmYcKIMNv3yYKmE4+Jku7R7m2MxGxU8pOK0DZymylEX9WlYFo5AihiiZI9V2it qCWBeSQgAjjF6K/oryYa/jnNWGKvWm4wUVyXzwBVVQRo7wUQB2WwFbOzI7U1UL+62wht BPOLuLaMBAbr1ArzUs8HFPW7o+Hxf8mYC2cAavhHHTE3gfLuQjDnzUv1bDkuAwqUJRKE Ehb5Txt/NSWUc0ZcgHF72FLcxVTWKzavT4mfZWL/qfota5oLaFdM6vFzJ99nRSKJlHVi SvSg== X-Gm-Message-State: AO0yUKVC47TNykus/0+ZZWyOrYwiHXmsPY91BeVpleBUf2SVjQ8Ua0/T AFOyqJDPrl8o53mlmKNWu6gTYw== X-Google-Smtp-Source: AK7set9oFTvy9gLg0v2Uw1hq/MDh+ZrN7iANrZsJBN0miAhGaZhsmo94uAcMLQGNj9WoYahk1BHIpg== X-Received: by 2002:adf:a493:0:b0:2bf:b5c0:f157 with SMTP id g19-20020adfa493000000b002bfb5c0f157mr19018507wrb.39.1675103119514; Mon, 30 Jan 2023 10:25:19 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/23] target/arm: Mark up sysregs for HFGITR bits 18..47 Date: Mon, 30 Jan 2023 18:24:54 +0000 Message-Id: <20230130182459.3309057-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103345687100001 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 18..47. These bits cover TLBI TLB maintenance instructions. (If we implemented FEAT_XS we would need to trap some of the instructions added by that feature using these bits; but we don't yet, so will need to add the .fgt markup when we do.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 30 ++++++++++++++++++++++++++++++ target/arm/helper.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1f74308ef5d..2e5ac6b4f98 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -666,6 +666,36 @@ typedef enum FGTBit { DO_BIT(HFGITR, ATS1E0W), DO_BIT(HFGITR, ATS1E1RP), DO_BIT(HFGITR, ATS1E1WP), + DO_BIT(HFGITR, TLBIVMALLE1OS), + DO_BIT(HFGITR, TLBIVAE1OS), + DO_BIT(HFGITR, TLBIASIDE1OS), + DO_BIT(HFGITR, TLBIVAAE1OS), + DO_BIT(HFGITR, TLBIVALE1OS), + DO_BIT(HFGITR, TLBIVAALE1OS), + DO_BIT(HFGITR, TLBIRVAE1OS), + DO_BIT(HFGITR, TLBIRVAAE1OS), + DO_BIT(HFGITR, TLBIRVALE1OS), + DO_BIT(HFGITR, TLBIRVAALE1OS), + DO_BIT(HFGITR, TLBIVMALLE1IS), + DO_BIT(HFGITR, TLBIVAE1IS), + DO_BIT(HFGITR, TLBIASIDE1IS), + DO_BIT(HFGITR, TLBIVAAE1IS), + DO_BIT(HFGITR, TLBIVALE1IS), + DO_BIT(HFGITR, TLBIVAALE1IS), + DO_BIT(HFGITR, TLBIRVAE1IS), + DO_BIT(HFGITR, TLBIRVAAE1IS), + DO_BIT(HFGITR, TLBIRVALE1IS), + DO_BIT(HFGITR, TLBIRVAALE1IS), + DO_BIT(HFGITR, TLBIRVAE1), + DO_BIT(HFGITR, TLBIRVAAE1), + DO_BIT(HFGITR, TLBIRVALE1), + DO_BIT(HFGITR, TLBIRVAALE1), + DO_BIT(HFGITR, TLBIVMALLE1), + DO_BIT(HFGITR, TLBIVAE1), + DO_BIT(HFGITR, TLBIASIDE1), + DO_BIT(HFGITR, TLBIVAAE1), + DO_BIT(HFGITR, TLBIVALE1), + DO_BIT(HFGITR, TLBIVAALE1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b9c7fcc3a4..5b9cc087e28 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5318,50 +5318,62 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVMALLE1IS, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAE1IS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIASIDE1IS, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAAE1IS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVALE1IS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAALE1IS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVMALLE1, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVAE1, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIASIDE1, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVAAE1, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVALE1, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVAALE1, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, @@ -7175,50 +7187,62 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAE1IS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAAE1IS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVALE1IS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAALE1IS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAE1OS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAAE1OS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVALE1OS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAALE1OS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIRVAE1, .writefn =3D tlbi_aa64_rvae1_write }, { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIRVAAE1, .writefn =3D tlbi_aa64_rvae1_write }, { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIRVALE1, .writefn =3D tlbi_aa64_rvae1_write }, { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIRVAALE1, .writefn =3D tlbi_aa64_rvae1_write }, { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, @@ -7290,26 +7314,32 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVMALLE1OS, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, + .fgt =3D FGT_TLBIVAE1OS, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIASIDE1OS, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAAE1OS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVALE1OS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Lt2f6IiUFpXwxZX1E9UJcu2gXVFrqyPjbwO3PpeBNvc=; b=Ak2dB8hqZeIV6RlBSzLdna9jzJD6cF4Iika9/hItNpUMOpRZB6Q84/fDrFigmkWe65 gnUQFM+2oVZ/s0sJjT+WToZAfzFNRCChzo0vDyRHFEioQr3ul02yvuAeBgYkmhgnUzFq rn3dQ6Asp0fkJTE/EUdKK0Vwxa+P/QcWeAntkNSXiVGgX4APT1FZHoPMO3kGomyX9Ouz A0m2Q5Zi/UIEeZ5pev4LTvi9SlfLqma0bjaNz7n23sHUWuK1gVorbdR/YL5DZQ7LC5JW +QGqfhLna0Ri/DV3RoieAeR7coORipRnbkAeHW0TTmB80UbRMrUUPX4tqnOjT86u8Z8k s1HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lt2f6IiUFpXwxZX1E9UJcu2gXVFrqyPjbwO3PpeBNvc=; b=sL3p5Ka6Isvn0hfi11lRnPGGhJnnwbIcIAoEaIS6srg0SiA/6dYTvNIgXAKfRd2Swm cEdWktiH4GWrnquylvsuLOPR0wVplIgBTwO0AhM6pH0aGcvXktaWgx4mnsH0VRWliqlx oCqaO8C1XD6x0muT21C4pkycmds42q7yetNDg5oX8niVXx4xP3Ir56eNp4qxXWdPJ1nI R9mBO0b2X+CD+knTAgAxf9cVjJXjKmRfvZBnTVaJWO2v7sN9DQgUNa/QMr8xMMAKF7wA fwvXS3Bk3uTrI6NcL+GCnSizeqxwNc4xYNVI8eoeUeNpiyNSPcRA5Dy+22emGM0egwTq q5lw== X-Gm-Message-State: AFqh2krHRkpOQ3bDxvUf+ImL3l2gEO5VPr5vWRMAYMHPeZFuYqR7BmYI fC/XC/NCrtojMptvhKyYooRatw== X-Google-Smtp-Source: AMrXdXuPGThBtZ87uJwlYsZyVSMddTjgACC9RdTnZ9hxUiDC0xe2KbrIp8Z/9ukjmjMmWS4Bn3I6uA== X-Received: by 2002:a5d:58e8:0:b0:2be:b07:d411 with SMTP id f8-20020a5d58e8000000b002be0b07d411mr40212469wrd.3.1675103120543; Mon, 30 Jan 2023 10:25:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 19/23] target/arm: Mark up sysregs for HFGITR bits 48..63 Date: Mon, 30 Jan 2023 18:24:55 +0000 Message-Id: <20230130182459.3309057-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103264840100001 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 48..63. Some of these bits are for trapping instructions which are not in the system instruction encoding (i.e. which are not handled by the ARMCPRegInfo mechanism): * ERET, ERETAA, ERETAB * SVC We will have to handle those separately and manually. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpregs.h | 4 ++++ target/arm/helper.c | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2e5ac6b4f98..efcf9181b97 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -696,6 +696,10 @@ typedef enum FGTBit { DO_BIT(HFGITR, TLBIVAAE1), DO_BIT(HFGITR, TLBIVALE1), DO_BIT(HFGITR, TLBIVAALE1), + DO_BIT(HFGITR, CFPRCTX), + DO_BIT(HFGITR, DVPRCTX), + DO_BIT(HFGITR, CPPRCTX), + DO_BIT(HFGITR, DCCVAC), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 5b9cc087e28..c0403aadae2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5295,6 +5295,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, @@ -7588,10 +7589,12 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[]= =3D { { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, @@ -7747,24 +7750,30 @@ static CPAccessResult access_predinv(CPUARMState *e= nv, const ARMCPRegInfo *ri, static const ARMCPRegInfo predinv_reginfo[] =3D { { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .fgt =3D FGT_CFPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .fgt =3D FGT_DVPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .fgt =3D FGT_CPPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, /* * Note the AArch32 opcodes have a different OPC1. */ { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .fgt =3D FGT_CFPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .fgt =3D FGT_DVPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .fgt =3D FGT_CPPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dwXHqLhKo35zy7gR+OyfjbB1+IphkLeWns/fzBcm5MU=; b=El+QkQeS8W7ibSQtZja1vdZAB5LOAD1ZUhJyaXTyyIWGtkb8PHijLGIZjyKqGpqNxg PGQrR6nLG058D4gkMxTfc4+c666W+fLCZgECo8LEzo7A7cq0AONks1SwMwPQat5/mq4I 6lMl9lHZEGNkhYGFVPspSaDFL0z18SK8stqKDMO7YPdXpBQklMqZYztwUX2jqi5imKvv nZSiL6uRw+HPK5Xo8mS2eaS/evfCzdCTeoonvuETedDxj92MYrkL0k3EukZpnt+M5X8m eIlWG7sozfziuhRRRU7Ca+y4N4CGPyrcUVNaYnUGzZkgFm2NTZeFb6WLnxnVLwKCpTb6 wpOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dwXHqLhKo35zy7gR+OyfjbB1+IphkLeWns/fzBcm5MU=; b=VRRfPF8coxHKM9O2qa6/YGSePGLD0IJ+iVVKRyYLh6zSLp4Iip+jpL88gRgjpLbRyU /JG+a7BChG90+wmy+pqAGwzjKmsXxK0rbInvJqsXSgQk0OrijmoJJU4tmqcMh9sbdk2+ LcXdCvZa3IH1798gAocr+S1b+q2SqkClUwIISZNrvr1VxSvvzXT5qm+EQLhfGYtNQAiJ C9BBYxm/BZx8eblaREZJWhs1k3muqJV6CFCStLrL13Y2yg09bWU+Ae64Ykk59asM/AFb HWpr/PeWSjKSjkjCuhqmt2S3NfJP8mHr7WjXGQhWV4kp1whzbB8KVJ6/XPJYEwjuPYWI ja6Q== X-Gm-Message-State: AO0yUKVnS2dEBgfp2dML7ZOgidvKlYwDT28jBezK8P/uAfzxq3HfqRQg WiVOD9m6qbeFsMgR9sL+YEcWL4EPz44U54WX X-Google-Smtp-Source: AK7set9tNvBnEkCfIs53YM9Ztnyz9SbOAdBVO3ImlaAWn+83IWouRZktOmkILBySZEZ02XCJ587Bwg== X-Received: by 2002:a05:6000:1f91:b0:2bf:d1a1:ff5d with SMTP id bw17-20020a0560001f9100b002bfd1a1ff5dmr10615471wrb.32.1675103121461; Mon, 30 Jan 2023 10:25:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 20/23] target/arm: Implement the HFGITR_EL2.ERET trap Date: Mon, 30 Jan 2023 18:24:56 +0000 Message-Id: <20230130182459.3309057-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103341437100017 Content-Type: text/plain; charset="utf-8" Implement the HFGITR_EL2.ERET fine-grained trap. This traps execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is reported with a syndrome value of 0x1a. The trap must take precedence over a possible pointer-authentication trap for ERETAA and ERETAB. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpu.h | 1 + target/arm/syndrome.h | 10 ++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 3 +++ target/arm/translate-a64.c | 10 ++++++++++ 5 files changed, 26 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5cc81bec9bf..ec2a7716ce7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3245,6 +3245,7 @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) FIELD(TBFLAG_A64, SVL, 24, 4) /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. = */ FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) +FIELD(TBFLAG_A64, FGT_ERET, 29, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 73df5e37938..d27d1bc31f0 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -48,6 +48,7 @@ enum arm_exception_class { EC_AA64_SMC =3D 0x17, EC_SYSTEMREGISTERTRAP =3D 0x18, EC_SVEACCESSTRAP =3D 0x19, + EC_ERETTRAP =3D 0x1a, EC_SMETRAP =3D 0x1d, EC_INSNABORT =3D 0x20, EC_INSNABORT_SAME_EL =3D 0x21, @@ -215,6 +216,15 @@ static inline uint32_t syn_sve_access_trap(void) return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; } =20 +/* + * eret_op is bits [1:0] of the ERET instruction, so: + * 0 for ERET, 2 for ERETAA, 3 for ERETAB. + */ +static inline uint32_t syn_erettrap(int eret_op) +{ + return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; +} + static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) { return (EC_SMETRAP << ARM_EL_EC_SHIFT) diff --git a/target/arm/translate.h b/target/arm/translate.h index 599902016dc..62a7706eabd 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -132,6 +132,8 @@ typedef struct DisasContext { bool mve_no_pred; /* True if fine-grained traps are active */ bool fgt_active; + /* True if fine-grained trap on ERET is enabled */ + bool fgt_eret; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index c0403aadae2..6151c775053 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12065,6 +12065,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, =20 if (arm_fgt_active(env, el)) { DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET= )) { + DP_TBFLAG_A64(flags, FGT_ERET, 1); + } } =20 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a47dab4f1dd..11bfa3f717a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2385,6 +2385,10 @@ static void disas_uncond_b_reg(DisasContext *s, uint= 32_t insn) if (op4 !=3D 0) { goto do_unallocated; } + if (s->fgt_eret) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), = 2); + return; + } dst =3D tcg_temp_new_i64(); tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUARMState, elr_el[s->current_el])); @@ -2398,6 +2402,11 @@ static void disas_uncond_b_reg(DisasContext *s, uint= 32_t insn) if (rn !=3D 0x1f || op4 !=3D 0x1f) { goto do_unallocated; } + /* The FGT trap takes precedence over an auth trap. */ + if (s->fgt_eret) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), = 2); + return; + } dst =3D tcg_temp_new_i64(); tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUARMState, elr_el[s->current_el])); @@ -14742,6 +14751,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); + dc->fgt_eret =3D EX_TBFLAG_A64(tb_flags, FGT_ERET); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl =3D (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; --=20 2.34.1 From nobody Fri Apr 19 18:42:09 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103277; cv=none; d=zohomail.com; s=zohoarc; b=YD0jh3G290QzIfE6jJGCcLJUgLJWa55UuCkDaZjwmgiUo9512p3fVMgEliLhI98HY6NEaOkF+Xw7FE46X4N9VhuwqC/zVZjDuWAT6cwyRzL+TgUclwuChFAIqZCErFymfiunQi+KtvQliQsAZNDUQbJyziAB3AFoyEE0t4E6ZJ0= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VeFx9B0Mzz35VrXD2mipraCVegd6Rxt0nAjW/UplbN4=; b=A3sdf5PIuD4Pv/SyIV5fxs3BaQUCZ4p5N9i/qgbiEW9jdqvYZaACf6SWA+bIVwf4aZ Da6kg+VYWu++RcD2mCliEXXT2h7KsXQ3WHR1QwkRnixG8RgLj5w9sAFfKkbMQWlP1qeY ZxSBz97vOgThfunKwQJswoOGSmVzcvgg8sKFjUHDbjtSXYyM4NVMMwM6STmotcFc7Dsb u6FI86NeRfqu8xZGG3jajRwRIl6A0EKoROOk72QAH/4o207QIt/P4XoW/FBAnWhpuWji 9+iIbfkGl1qH4qQegCSsSCMnN548IFLu7Mz2SxoJBZV7w1pogDMEhud7pVKhi02lWJY/ qzUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VeFx9B0Mzz35VrXD2mipraCVegd6Rxt0nAjW/UplbN4=; b=flDIIXKRmq3hX7KPblP/pdnc2yHPg+BLjY+NliHlf4BODQkSCqecL/l5fVFP4zw7vB SkR7cUT3TIEs7GtG77pcaxLbkV7XiNR9sIfnebN4u+VT2DzE75o6nRJCPgr8GwrKXyt9 8OhGOOaolZgU/2WZPUpNM7+y0m0VhWaBSkJgnOQH/q1GQAC7yRI3sTZYXpk0QneAbdjE YafU1InQY8rqpqoWnXq7iV/9GOhu5c77F8wIt8tsox6m4wAiIhHUAnHVZg9eqGKdO8H2 Gly2R4kQNCbNNcJV2FkmAnKVAtlSBkfdH3UBwJYjvkjVNWc3LrpwiocIE3LYJ9EOxuhG yhpQ== X-Gm-Message-State: AO0yUKV0vdOv0FU+l1b3RzTlHUtkzUvpP0QXsuu2jMpiP3nJX949I7AX 1wNkEAn1xb/oi8rV2199XHHzzFN+d0EJtC9K X-Google-Smtp-Source: AK7set+k3mDKQbLzLKfCNCTEoLO09cNacMeZH/6962EonFWx3LQhcnWHvRPubFts8hZQWX4Ah4fokA== X-Received: by 2002:adf:9790:0:b0:2bf:d425:11ba with SMTP id s16-20020adf9790000000b002bfd42511bamr484301wrb.22.1675103122521; Mon, 30 Jan 2023 10:25:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 21/23] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps Date: Mon, 30 Jan 2023 18:24:57 +0000 Message-Id: <20230130182459.3309057-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103278974100003 Content-Type: text/plain; charset="utf-8" Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps. These trap execution of the SVC instruction from AArch32 and AArch64. (As usual, AArch32 can only trap from EL0, as fine grained traps are disabled with an AArch32 EL1.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/cpu.h | 1 + target/arm/translate.h | 2 ++ target/arm/helper.c | 20 ++++++++++++++++++++ target/arm/translate-a64.c | 9 ++++++++- target/arm/translate.c | 12 +++++++++--- 5 files changed, 40 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec2a7716ce7..7bc97fece97 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3171,6 +3171,7 @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) +FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index 62a7706eabd..3717824b754 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -134,6 +134,8 @@ typedef struct DisasContext { bool fgt_active; /* True if fine-grained trap on ERET is enabled */ bool fgt_eret; + /* True if fine-grained trap on SVC is enabled */ + bool fgt_svc; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 6151c775053..c62ed05c122 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11842,6 +11842,20 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 +static inline bool fgt_svc(CPUARMState *env, int el) +{ + /* + * Assuming fine-grained-traps are active, return true if we + * should be trapping on SVC instructions. Only AArch64 can + * trap on an SVC at EL1, but we don't need to special-case this + * because if this is AArch32 EL1 then arm_fgt_active() is false. + * We also know el is 0 or 1. + */ + return el =3D=3D 0 ? + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0)= : + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -11927,6 +11941,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState= *env, int fp_el, =20 if (arm_fgt_active(env, el)) { DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } } =20 if (env->uncached_cpsr & CPSR_IL) { @@ -12068,6 +12085,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET= )) { DP_TBFLAG_A64(flags, FGT_ERET, 1); } + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } } =20 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 11bfa3f717a..bbfadb7c2e8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2179,6 +2179,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) int opc =3D extract32(insn, 21, 3); int op2_ll =3D extract32(insn, 0, 5); int imm16 =3D extract32(insn, 5, 16); + uint32_t syndrome; =20 switch (opc) { case 0: @@ -2189,8 +2190,13 @@ static void disas_exc(DisasContext *s, uint32_t insn) */ switch (op2_ll) { case 1: /* SVC= */ + syndrome =3D syn_aa64_svc(imm16); + if (s->fgt_svc) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + break; + } gen_ss_advance(s); - gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16)); + gen_exception_insn(s, 4, EXCP_SWI, syndrome); break; case 2: /* HVC= */ if (s->current_el =3D=3D 0) { @@ -14751,6 +14757,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); + dc->fgt_svc =3D EX_TBFLAG_ANY(tb_flags, FGT_SVC); dc->fgt_eret =3D EX_TBFLAG_A64(tb_flags, FGT_ERET); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); diff --git a/target/arm/translate.c b/target/arm/translate.c index 3f51dc6a6bf..c23a3462bfc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8834,9 +8834,14 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) (a->imm =3D=3D semihost_imm)) { gen_exception_internal_insn(s, EXCP_SEMIHOST); } else { - gen_update_pc(s, curr_insn_len(s)); - s->svc_imm =3D a->imm; - s->base.is_jmp =3D DISAS_SWI; + if (s->fgt_svc) { + uint32_t syndrome =3D syn_aa32_svc(a->imm, s->thumb); + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + } else { + gen_update_pc(s, curr_insn_len(s)); + s->svc_imm =3D a->imm; + s->base.is_jmp =3D DISAS_SWI; + } } return true; } @@ -9417,6 +9422,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); + dc->fgt_svc =3D EX_TBFLAG_ANY(tb_flags, FGT_SVC); =20 if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled =3D 1; --=20 2.34.1 From nobody Fri Apr 19 18:42:09 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103285; cv=none; d=zohomail.com; s=zohoarc; b=P28/I60SOgL1Q6NK0fH6OThrOHZSF12uT1PNeNH4Ar6p8kQJDy0GchYRBj/puD8RglqbMSLZOty3QNGJPrxBIhbkzBIw4u7kUvZ5wMThejACKAoeqtp5NdGP2jFC87ICbrGOH1glciboUsur+szjHNnJEn6BjNsWAKw63dL/te4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103285; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5OppjKsEFWrzHuMej0d7TRJ+lmUSsgoknvJv6YnUZ9I=; b=iO8g3aAoSmI4JHtH3kA+JA6w8EI6AqCXrACoteJBXTbK05jj/coZrnaHGEGGFQkFjy 3/1GC4CY9cXon5gJcR92jZJ3e+vrk/lQIRo9TzjKLK3mRtm1Xm/7vRu8vGHbn/IPLchb aHeue2EyQ7yoAuBWRjV6sIjE6+Jr6Y5SdO8k3qSlcxftPvrgv3hRo8eUrMqNTO9xOFWx TXgFy4oyKHC7pDmJaKUe7bLceJcqW6tAHZc2xj1jfbmiU72B+YXfRhkWtrjexVWDMzDD OOI/nKyu1ZkTY6bJu0vl9W0va9j50pL2gauLc2TMNt5UHchGM+BEePRnf+IGsvsz8uEN QviA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5OppjKsEFWrzHuMej0d7TRJ+lmUSsgoknvJv6YnUZ9I=; b=UMpV8igfy48EnSA8A+oz/t/zpTGfvFLGBJ2cjhQj4Eh1LuY9vsZ4bg8u5JjWWOXooz BEVq0RcoY6lfbtR1QNJLhhdEGFZ39CEpxel1LI+NwLTyYGeS75/eT8yKg9hDbKqgmmBO psIA0kv5Xm5zULcNxYTyN/qtaBW/Xa4aZ63SdjTCyxgaSgMwzSEF+gR+jxGHKJ2lHeFj 7CohjbqZqZmHjxLjd54aQmNN8LK5ve2xN/UUCFroSA7HhgEWFDf97CjGpyh69OoqFvKI GUWytmDcJSFkZkuCapj8LvAKbsmTPPX7pbj4bAbN0dlzCxpUgBMmg8kj8J4ssHGdIyFC iv0A== X-Gm-Message-State: AO0yUKXcVOr/MuGYNytOYyGoWY9XYHmB/A1URk65XWjgNOp2FiJx+l6a P/CyN6txc6lhqdNvfqQl7aGjD7sqmeIbrQtw X-Google-Smtp-Source: AK7set+XOXZj5LnJMyRzEkFTrtbCT5i8+AP200tQPrA1DwpTdqMdZtCK1x8ONnChR9GHzCjVQg0+jw== X-Received: by 2002:a5d:650f:0:b0:2bf:ae11:c40c with SMTP id x15-20020a5d650f000000b002bfae11c40cmr20484662wru.32.1675103123539; Mon, 30 Jan 2023 10:25:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 22/23] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps Date: Mon, 30 Jan 2023 18:24:58 +0000 Message-Id: <20230130182459.3309057-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103287019100003 Content-Type: text/plain; charset="utf-8" FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0, MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their AArch32 equivalents). This trapping is independent of whether fine-grained traps are enabled or not. Implement these extra traps. (We don't implement DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org Tested-by: Fuad Tabba --- target/arm/debug_helper.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b106746b0e1..3c671c88c1a 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -599,6 +599,33 @@ static CPAccessResult access_tda(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* + * Check for traps to Debug Comms Channel registers. If FEAT_FGT + * is implemented then these are controlled by MDCR_EL2.TDCC for + * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by + * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA. + */ +static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || + (arm_hcr_el2_eff(env) & HCR_TGE); + bool mdcr_el2_tdcc =3D cpu_isar_feature(aa64_fgt, env_archcpu(env)) && + (mdcr_el2 & MDCR_TDCC); + bool mdcr_el3_tdcc =3D cpu_isar_feature(aa64_fgt, env_archcpu(env)) && + (env->cp15.mdcr_el3 & MDCR_TDCC); + + if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -681,7 +708,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { */ { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, + .access =3D PL0_R, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_E= L0. @@ -689,11 +716,11 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { */ { .name =3D "OSDTRRX_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, + .access =3D PL1_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "OSDTRTX_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, + .access =3D PL1_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * OSECCR_EL1 provides a mechanism for an operating system @@ -757,7 +784,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { */ { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, + .access =3D PL1_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_NOP }, /* * Dummy DBGCLAIM registers. --=20 2.34.1 From nobody Fri Apr 19 18:42:09 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103255; cv=none; d=zohomail.com; s=zohoarc; b=RaOLf2/Ustj7jg/ujbYv0rYHcZjP3sKbuXquIkX6x2UKnpun9SLLNILOHwrYYi+aszzyKPui7W60XOkixH7IszZOZ29GHWYtkNrSTH0IWBQrM0Jm7NXCxQ81y5dQEHKBOW6E96g/l/NwYTCnWYi6yms53q58WQwq4pzJZalx6BM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103255; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Vj+8R3eAUWvoTvt+rtdp3a8e8+qsFowbhWMk+Fsc6nE=; b=axbTDnGCEyqVhEXtseGN24QBPpiPyiQHCUj8IXvFu7ID1p/Pc5ymhRg4W26ekWuDE2BfMHc4N7tiy2bzLiOH6ZRzvH3MO7SoLoUJx7ksTWFdJWIx2IDo1sACNgdqWDVWJH7YSaaFYh29SFQJn+zGXhEArr1kJW97oKcTG4mEefg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103255707825.5783054597313; Mon, 30 Jan 2023 10:27:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqU-0001Fk-G8; Mon, 30 Jan 2023 13:25:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYqP-0001CQ-UP for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:30 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYqL-0008R5-AC for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:29 -0500 Received: by mail-wr1-x431.google.com with SMTP id m7so11984239wru.8 for ; Mon, 30 Jan 2023 10:25:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Vj+8R3eAUWvoTvt+rtdp3a8e8+qsFowbhWMk+Fsc6nE=; b=JRELcrA3NnnBuZvuy/RVQCm1kH2JcvOT5mju9FW6IjVjmBBUd1PPDPDd8E28Prp3sL 82ruCcn6Yx/WTuCIbNVMdd9oStM8ehSCkyP6uZkxsfBmPj7L5a8l3BrC+1eXoxQYOgjc VjDmUddULcDPwjgdXhBPjHs0nOItDUo8kEoSka71ZvxnO86ccvm0Xyq6jaCRzWepy1E/ DCrcCEYMXSC0n3buqUaP7ykrcXLa5H5UphbuLUXaJFavgcwR+gXyTe1KJ0xDxBTX4znq 2LXp5U0ebIiu/v213y1B4DcJvFJdsOvf7WtL/PUtwhi8pY4FscesA253oamxqM3Agd97 Tl4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vj+8R3eAUWvoTvt+rtdp3a8e8+qsFowbhWMk+Fsc6nE=; b=T4G0fnBUv+hZyFK7liQqJdDeFQjGYGyB7iwlpAseqkIBsQ1aG8hu2EPjWb5O+4cXRY kulXyJSOPftBGv1C+gc1UCnn/4wSa1p7ZJYhod4JPy4e7TJcuO6iqS4F4ghE+LHvaWnJ tA/bAzFIJLSqFMIMC1oA0PLh7gO+i6DQjy7De5P2E6HArO/LQybDsQhZOdTxPIGz5kjD XyD9eawZqIlJE7/jP07TKNfzUJSePEqf3hbzkY26+7pYnCYaD/eb3F9LpiAqmTO5qnXS y+9VfUt9b1cdjwXNR9kDqgY3RvnCuMJrdBTArxVZPfA7oQXQ8Qt/NR0LSlzAOIUWkTkg hmeQ== X-Gm-Message-State: AO0yUKWQ/pRaazU6ALhFB0OIL4NA1RcaPMrpfShqBOBJU9y13eZtjxSO 98+xn3S9cbX+BxSXzWgO0B+YZmKnbn4ykVyR X-Google-Smtp-Source: AK7set8Cc7yrPBQCx55/jMfF9PP+Zx+5/mp7kHpISYM2ZspW8O4yl0Sv0HH9gFTxPHlGEcTOmxTzig== X-Received: by 2002:adf:f14a:0:b0:2bf:cd9f:37f9 with SMTP id y10-20020adff14a000000b002bfcd9f37f9mr11830193wro.4.1675103124529; Mon, 30 Jan 2023 10:25:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 23/23] target/arm: Enable FEAT_FGT on '-cpu max' Date: Mon, 30 Jan 2023 18:24:59 +0000 Message-Id: <20230130182459.3309057-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103256637100003 Content-Type: text/plain; charset="utf-8" Update the ID registers for TCG's '-cpu max' to report the presence of FEAT_FGT Fine-Grained Traps support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org Tested-by: Fuad Tabba --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b33d7c28dc1..c76555f51a7 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -28,6 +28,7 @@ the following architecture extensions: - FEAT_ETS (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) - FEAT_FCMA (Floating-point complex number instructions) +- FEAT_FGT (Fine-Grained Traps) - FEAT_FHM (Floating-point half-precision multiplication instructions) - FEAT_FP16 (Half-precision floating-point data processing) - FEAT_FRINTTS (Floating-point to integer instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0e021960fb5..4066950da15 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1224,6 +1224,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; --=20 2.34.1