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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UzHZUC2Q/Mer8SDW1LpV1AWKuWIz5z5lMzrsLDlqH9k=; b=GVVR/fc1lytWMg94yq8DaEsF+or+vFyshvXYBlTUq8ZFEVcQr6w/edCGL9Mz5upQzJ MIXWqT6nCC1fALdrJDytD0iiyIZ0UzbO3cxfQN8a4DSk6rb4ZhrHGuEKeGCbyRM06fBU kFqIv5jXs3UlLt3cpN8UI6LxoMb0poLUfW6Dyq8Y8kycy6q27CRdbe/9yRMrH0nAagzg BjlPCdjlkWplNtbKK7prfnwCRe/7wHbk30jj/MiO77r77NYN9NOpk7BiEqBe1QgwLZHM fp2+mWauKGHFSKRtqP3bPB1znVUnHEh9ttxJjHICLC5xJh10/roeyHTEWGFHhCsewpR3 tktg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UzHZUC2Q/Mer8SDW1LpV1AWKuWIz5z5lMzrsLDlqH9k=; b=7nGElZnOeeEgdfew7fG0I2qPKMm+qDR4tTDW+RLMhL9Ix6qq3a8eBT++D/7ButDqt1 x7i67VcbOomx/X/2GZkAHFC78HY2RFTs3AXvM1bhFQyqaXdVjf4oo/jprre6C6xvP6i/ gGnxDWlGhD2XigeRs7ifxpfkueWaaAAy5ugklkejdJNuYLbbUC4I+ox6qFpoBBV2ytee /v4lhmEmDOEWFyvjye+j6M7AKetFXHTXTV61lSD+SlVN2xq4bvt2qZ6BYHHbh70EzEGd bmpanln9MMVvA/TEE3PcaDDLkba8+bLYigIWOSlj+RGV4ICe54xm/AZfNRKeBeY76VjJ Btlg== X-Gm-Message-State: AO0yUKXiNhGPnnne/vszWADim4XA7zWcrUMa/une89kQCq1PAoNMu83M 1dAOOPoDOUWkwxA+RopQJ3soBb2z/yaiqK6x X-Google-Smtp-Source: AK7set8AfYFBv7MSr5zWTk2MI8HpJviYTwSI14TzQzzniPfNUQK0XK+xtvbQg7H4E1SiPxEyqFwRAw== X-Received: by 2002:a05:6000:143:b0:2bf:b88b:aae8 with SMTP id r3-20020a056000014300b002bfb88baae8mr343749wrx.50.1675103117499; Mon, 30 Jan 2023 10:25:17 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/23] target/arm: Mark up sysregs for HFGITR bits 0..11 Date: Mon, 30 Jan 2023 18:24:52 +0000 Message-Id: <20230130182459.3309057-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103244594100006 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 0..11. These bits cover various cache maintenance operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org --- target/arm/cpregs.h | 14 ++++++++++++++ target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c37e013b8f3..6596c2a1233 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -646,6 +646,20 @@ typedef enum FGTBit { DO_BIT(HDFGWTR, PMCR_EL0), DO_BIT(HDFGRTR, PMMIR_EL1), DO_BIT(HDFGRTR, PMCEIDN_EL0), + + /* Trap bits in HFGITR_EL2, starting from bit 0 */ + DO_BIT(HFGITR, ICIALLUIS), + DO_BIT(HFGITR, ICIALLU), + DO_BIT(HFGITR, ICIVAU), + DO_BIT(HFGITR, DCIVAC), + DO_BIT(HFGITR, DCISW), + DO_BIT(HFGITR, DCCSW), + DO_BIT(HFGITR, DCCISW), + DO_BIT(HFGITR, DCCVAU), + DO_BIT(HFGITR, DCCVAP), + DO_BIT(HFGITR, DCCVADP), + DO_BIT(HFGITR, DCCIVAC), + DO_BIT(HFGITR, DCZVA), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 2e494b8f924..51866ba70e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5261,6 +5261,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, @@ -5270,21 +5271,26 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIALLUIS, .accessfn =3D access_ticab }, { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIALLU, .accessfn =3D access_tocu }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIVAU, .accessfn =3D access_tocu }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, + .fgt =3D FGT_DCIVAC, .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, + .fgt =3D FGT_DCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, @@ -5292,17 +5298,21 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, + .fgt =3D FGT_DCCSW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCVAU, .accessfn =3D access_tocu }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, + .fgt =3D FGT_DCCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, @@ -7413,6 +7423,7 @@ static const ARMCPRegInfo dcpop_reg[] =3D { { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, }; =20 @@ -7420,6 +7431,7 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, }; #endif /*CONFIG_USER_ONLY*/ @@ -7499,28 +7511,36 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "DC_IGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL1_W, + .fgt =3D FGT_DCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_IGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, + .fgt =3D FGT_DCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_IGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL1_W, + .fgt =3D FGT_DCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_IGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, + .fgt =3D FGT_DCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, + .fgt =3D FGT_DCCSW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, + .fgt =3D FGT_DCCSW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CIGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, + .fgt =3D FGT_DCCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, + .fgt =3D FGT_DCCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, }; =20 @@ -7542,26 +7562,32 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[]= =3D { { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_GVA", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, @@ -7569,6 +7595,7 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, { .name =3D "DC_GZVA", .state =3D ARM_CP_STATE_AA64, @@ -7577,6 +7604,7 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, }; --=20 2.34.1