From nobody Tue May 13 13:17:12 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675103277; cv=none; d=zohomail.com; s=zohoarc; b=YD0jh3G290QzIfE6jJGCcLJUgLJWa55UuCkDaZjwmgiUo9512p3fVMgEliLhI98HY6NEaOkF+Xw7FE46X4N9VhuwqC/zVZjDuWAT6cwyRzL+TgUclwuChFAIqZCErFymfiunQi+KtvQliQsAZNDUQbJyziAB3AFoyEE0t4E6ZJ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675103277; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VeFx9B0Mzz35VrXD2mipraCVegd6Rxt0nAjW/UplbN4=; b=dSUUYDTeG/JMDasaxrwG+cK6M7ICuKUKHxgAl+8AfRArRO3P0gcfy7CL559nr2i0bc/iJ4pGKuhpjtIb++pbAmyknCtwYR+Ddw6TrZyQ2ixd62XNwSj3igGCcFNlTGbf8uU8ajjq/8DLs8xH+bCa5OkJJzLDmELu8hyxB9LghHA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675103277046341.1805227963065; Mon, 30 Jan 2023 10:27:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMYqU-0001Fh-2e; Mon, 30 Jan 2023 13:25:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYqO-0001BL-Kw for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:28 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYqJ-0008O3-9L for qemu-devel@nongnu.org; Mon, 30 Jan 2023 13:25:28 -0500 Received: by mail-wr1-x42a.google.com with SMTP id t18so12011113wro.1 for ; Mon, 30 Jan 2023 10:25:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020adffe90000000b002b8fe58d6desm12245202wrr.62.2023.01.30.10.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:25:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VeFx9B0Mzz35VrXD2mipraCVegd6Rxt0nAjW/UplbN4=; b=A3sdf5PIuD4Pv/SyIV5fxs3BaQUCZ4p5N9i/qgbiEW9jdqvYZaACf6SWA+bIVwf4aZ Da6kg+VYWu++RcD2mCliEXXT2h7KsXQ3WHR1QwkRnixG8RgLj5w9sAFfKkbMQWlP1qeY ZxSBz97vOgThfunKwQJswoOGSmVzcvgg8sKFjUHDbjtSXYyM4NVMMwM6STmotcFc7Dsb u6FI86NeRfqu8xZGG3jajRwRIl6A0EKoROOk72QAH/4o207QIt/P4XoW/FBAnWhpuWji 9+iIbfkGl1qH4qQegCSsSCMnN548IFLu7Mz2SxoJBZV7w1pogDMEhud7pVKhi02lWJY/ qzUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VeFx9B0Mzz35VrXD2mipraCVegd6Rxt0nAjW/UplbN4=; b=flDIIXKRmq3hX7KPblP/pdnc2yHPg+BLjY+NliHlf4BODQkSCqecL/l5fVFP4zw7vB SkR7cUT3TIEs7GtG77pcaxLbkV7XiNR9sIfnebN4u+VT2DzE75o6nRJCPgr8GwrKXyt9 8OhGOOaolZgU/2WZPUpNM7+y0m0VhWaBSkJgnOQH/q1GQAC7yRI3sTZYXpk0QneAbdjE YafU1InQY8rqpqoWnXq7iV/9GOhu5c77F8wIt8tsox6m4wAiIhHUAnHVZg9eqGKdO8H2 Gly2R4kQNCbNNcJV2FkmAnKVAtlSBkfdH3UBwJYjvkjVNWc3LrpwiocIE3LYJ9EOxuhG yhpQ== X-Gm-Message-State: AO0yUKV0vdOv0FU+l1b3RzTlHUtkzUvpP0QXsuu2jMpiP3nJX949I7AX 1wNkEAn1xb/oi8rV2199XHHzzFN+d0EJtC9K X-Google-Smtp-Source: AK7set+k3mDKQbLzLKfCNCTEoLO09cNacMeZH/6962EonFWx3LQhcnWHvRPubFts8hZQWX4Ah4fokA== X-Received: by 2002:adf:9790:0:b0:2bf:d425:11ba with SMTP id s16-20020adf9790000000b002bfd42511bamr484301wrb.22.1675103122521; Mon, 30 Jan 2023 10:25:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 21/23] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps Date: Mon, 30 Jan 2023 18:24:57 +0000 Message-Id: <20230130182459.3309057-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130182459.3309057-1-peter.maydell@linaro.org> References: <20230130182459.3309057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675103278974100003 Content-Type: text/plain; charset="utf-8" Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps. These trap execution of the SVC instruction from AArch32 and AArch64. (As usual, AArch32 can only trap from EL0, as fine grained traps are disabled with an AArch32 EL1.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org --- target/arm/cpu.h | 1 + target/arm/translate.h | 2 ++ target/arm/helper.c | 20 ++++++++++++++++++++ target/arm/translate-a64.c | 9 ++++++++- target/arm/translate.c | 12 +++++++++--- 5 files changed, 40 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec2a7716ce7..7bc97fece97 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3171,6 +3171,7 @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) +FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index 62a7706eabd..3717824b754 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -134,6 +134,8 @@ typedef struct DisasContext { bool fgt_active; /* True if fine-grained trap on ERET is enabled */ bool fgt_eret; + /* True if fine-grained trap on SVC is enabled */ + bool fgt_svc; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 6151c775053..c62ed05c122 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11842,6 +11842,20 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 +static inline bool fgt_svc(CPUARMState *env, int el) +{ + /* + * Assuming fine-grained-traps are active, return true if we + * should be trapping on SVC instructions. Only AArch64 can + * trap on an SVC at EL1, but we don't need to special-case this + * because if this is AArch32 EL1 then arm_fgt_active() is false. + * We also know el is 0 or 1. + */ + return el =3D=3D 0 ? + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0)= : + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -11927,6 +11941,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState= *env, int fp_el, =20 if (arm_fgt_active(env, el)) { DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } } =20 if (env->uncached_cpsr & CPSR_IL) { @@ -12068,6 +12085,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET= )) { DP_TBFLAG_A64(flags, FGT_ERET, 1); } + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } } =20 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 11bfa3f717a..bbfadb7c2e8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2179,6 +2179,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) int opc =3D extract32(insn, 21, 3); int op2_ll =3D extract32(insn, 0, 5); int imm16 =3D extract32(insn, 5, 16); + uint32_t syndrome; =20 switch (opc) { case 0: @@ -2189,8 +2190,13 @@ static void disas_exc(DisasContext *s, uint32_t insn) */ switch (op2_ll) { case 1: /* SVC= */ + syndrome =3D syn_aa64_svc(imm16); + if (s->fgt_svc) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + break; + } gen_ss_advance(s); - gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16)); + gen_exception_insn(s, 4, EXCP_SWI, syndrome); break; case 2: /* HVC= */ if (s->current_el =3D=3D 0) { @@ -14751,6 +14757,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); + dc->fgt_svc =3D EX_TBFLAG_ANY(tb_flags, FGT_SVC); dc->fgt_eret =3D EX_TBFLAG_A64(tb_flags, FGT_ERET); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); diff --git a/target/arm/translate.c b/target/arm/translate.c index 3f51dc6a6bf..c23a3462bfc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8834,9 +8834,14 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) (a->imm =3D=3D semihost_imm)) { gen_exception_internal_insn(s, EXCP_SEMIHOST); } else { - gen_update_pc(s, curr_insn_len(s)); - s->svc_imm =3D a->imm; - s->base.is_jmp =3D DISAS_SWI; + if (s->fgt_svc) { + uint32_t syndrome =3D syn_aa32_svc(a->imm, s->thumb); + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + } else { + gen_update_pc(s, curr_insn_len(s)); + s->svc_imm =3D a->imm; + s->base.is_jmp =3D DISAS_SWI; + } } return true; } @@ -9417,6 +9422,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); + dc->fgt_svc =3D EX_TBFLAG_ANY(tb_flags, FGT_SVC); =20 if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled =3D 1; --=20 2.34.1