From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115635; cv=none; d=zohomail.com; s=zohoarc; b=WIwUVMgWPnVuSAFTITJpZK/7IJt6/akLWHSDcT5Q87loRazXFPrOyptdNT7GjMYs33fDCAhJPDRmbrKdvk2fVrRPon/vq0dTzeDKQ3UoVbZKbVQBgc13MEaFDLFwtns5eNqNTpIHYZC0SKOFDp221KgPnJ+CBQukPmTzeWdAEJM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115635; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uYhih3WzBvljJJYreEPqLN+cqoryMajrlaD+6+DuEUE=; b=NuBmP0iGS+Ujs8ERLU9/rG222ZpHXfucaW4dT7lWh6l2KYSsv/VFq+KsaFK7zE1KuyZwL6FfIs5hsazVn30RUjqlSOd6uXMY8jI9ejbvBBwEep6G8LW3XQGJdReT5W5WIdmyKrib6i0bve74hQToTtNU8bobGwaxcAa5oUtrRuU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115635415642.4511438381281; Mon, 30 Jan 2023 13:53:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1I-0001rY-VL; Mon, 30 Jan 2023 16:48:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1G-0001rE-UG for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:48:54 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1E-0005Zl-VB for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:48:54 -0500 Received: by mail-pj1-x1032.google.com with SMTP id cl23-20020a17090af69700b0022c745bfdc3so5892136pjb.3 for ; Mon, 30 Jan 2023 13:48:52 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.48.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:48:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uYhih3WzBvljJJYreEPqLN+cqoryMajrlaD+6+DuEUE=; b=aOaD6hhCyCDgJ9fBD1H14xElnrVJ9c/h/TzTjC4s3LybO4+F2czuY24sGtMFrjDYmG yJmDhBOGYskjaIDduxfKnVaiBUKWS5gj2h+NxDhGZ67WH/cSv2K4CPTX1oyy9MSrsQHr 8auVZP0FIimBmnDpb4tbJ7OSxm3FI5vI2aE7unI/mdA5KBBn7RyROBn18dvzM+fiUehr K8M25c+egsRlNL+2abMMyqIyRa95WeKTFcX9XslmNy4aV2DW/NpT+OHAEDHd4CI5NNI0 ILnFuu/Bthn6jz+lAHwFxhN/X/WmNryGYNO+m6bTyMnZCp47f0ezAvgaflbbc9cc52x6 fNqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uYhih3WzBvljJJYreEPqLN+cqoryMajrlaD+6+DuEUE=; b=Rfr4T/8vVJN+HR8jmp27uj6EIYy8LHG9JJrULWG5ltnQEtYcZw0xILHNcU0YAHiox5 iqINKJsxUANuW+yrfHczQhKaKpCP39YEVxvbuhnCik77wyH4G7qeDvRGbsTy2dhi3B8F H/LzWC2c6JcbcNCdTKAdaY3vdXtrDA25ke+yPbs7ZlAJ31d7BlWfpMXFAhXSEeat2gkl +6p6DRuXGou8WAHKXWvBXkCEgZH3BeMZiZK6wrdHzDUqks8Z8u5pf+Zq3gn31SLOqWpg cYPpvFoTrbT0pNubagwZfNZWXGc5YIfhhtgrkPW2vBkoLNHrbj4wZtrQz/y3Ru2AIs78 4Hmg== X-Gm-Message-State: AO0yUKVUZCY8eQG6pxapclKZSAxybAlE+kzS7Clqhurp4VZkS4/bT3JK RiAZkwKWI4LdotmD5sAzgywHtbgiKzHKjxOp X-Google-Smtp-Source: AK7set/cp0uoSOWAACKAvftEFgXaWrS2iEyyLyYb3GCLDYNV+Q1pzhkrkfEo8JM4gw3tIqS1ekDm6A== X-Received: by 2002:a17:90b:4b46:b0:226:3a7c:f248 with SMTP id mi6-20020a17090b4b4600b002263a7cf248mr10997797pjb.24.1675115329745; Mon, 30 Jan 2023 13:48:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 01/36] tcg: Define TCG_TYPE_I128 and related helper macros Date: Mon, 30 Jan 2023 11:48:09 -1000 Message-Id: <20230130214844.1158612-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115635617100001 Begin staging in support for TCGv_i128 with Int128. Define the type enumerator, the typedef, and the helper-head.h macros. This cannot yet be used, because you can't allocate temporaries of this new type. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 7 +++++++ include/tcg/tcg.h | 17 ++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index bc6698b19f..b8d1140dc7 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -26,6 +26,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_i128 i128 #define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 @@ -40,6 +41,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_i128 Int128 #define dh_ctype_f16 uint32_t #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 @@ -71,6 +73,7 @@ #define dh_retvar_decl0_noreturn void #define dh_retvar_decl0_i32 TCGv_i32 retval #define dh_retvar_decl0_i64 TCGv_i64 retval +#define dh_retval_decl0_i128 TCGv_i128 retval #define dh_retvar_decl0_ptr TCGv_ptr retval #define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t)) =20 @@ -78,6 +81,7 @@ #define dh_retvar_decl_noreturn #define dh_retvar_decl_i32 TCGv_i32 retval, #define dh_retvar_decl_i64 TCGv_i64 retval, +#define dh_retvar_decl_i128 TCGv_i128 retval, #define dh_retvar_decl_ptr TCGv_ptr retval, #define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t)) =20 @@ -85,6 +89,7 @@ #define dh_retvar_noreturn NULL #define dh_retvar_i32 tcgv_i32_temp(retval) #define dh_retvar_i64 tcgv_i64_temp(retval) +#define dh_retvar_i128 tcgv_i128_temp(retval) #define dh_retvar_ptr tcgv_ptr_temp(retval) #define dh_retvar(t) glue(dh_retvar_, dh_alias(t)) =20 @@ -95,6 +100,7 @@ #define dh_typecode_i64 4 #define dh_typecode_s64 5 #define dh_typecode_ptr 6 +#define dh_typecode_i128 7 #define dh_typecode_int dh_typecode_s32 #define dh_typecode_f16 dh_typecode_i32 #define dh_typecode_f32 dh_typecode_i32 @@ -104,6 +110,7 @@ =20 #define dh_callflag_i32 0 #define dh_callflag_i64 0 +#define dh_callflag_i128 0 #define dh_callflag_ptr 0 #define dh_callflag_void 0 #define dh_callflag_noreturn TCG_CALL_NO_RETURN diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9a0ae7d20b..8b7e61e7a5 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -270,6 +270,7 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + TCG_TYPE_I128, =20 TCG_TYPE_V64, TCG_TYPE_V128, @@ -351,13 +352,14 @@ typedef tcg_target_ulong TCGArg; in tcg/README. Target CPU front-end code uses these types to deal with TCG variables as it emits TCG code via the tcg_gen_* functions. They come in several flavours: - * TCGv_i32 : 32 bit integer type - * TCGv_i64 : 64 bit integer type - * TCGv_ptr : a host pointer type - * TCGv_vec : a host vector type; the exact size is not exposed - to the CPU front-end code. - * TCGv : an integer type the same size as target_ulong - (an alias for either TCGv_i32 or TCGv_i64) + * TCGv_i32 : 32 bit integer type + * TCGv_i64 : 64 bit integer type + * TCGv_i128 : 128 bit integer type + * TCGv_ptr : a host pointer type + * TCGv_vec : a host vector type; the exact size is not exposed + to the CPU front-end code. + * TCGv : an integer type the same size as target_ulong + (an alias for either TCGv_i32 or TCGv_i64) The compiler's type checking will complain if you mix them up and pass the wrong sized TCGv to a function. =20 @@ -377,6 +379,7 @@ typedef tcg_target_ulong TCGArg; =20 typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; +typedef struct TCGv_i128_d *TCGv_i128; typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115396632142.91274650276387; Mon, 30 Jan 2023 13:49:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1K-0001sD-Jo; Mon, 30 Jan 2023 16:48:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1I-0001rQ-0z for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:48:56 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1G-0005a1-85 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:48:55 -0500 Received: by mail-pj1-x1035.google.com with SMTP id e10-20020a17090a630a00b0022bedd66e6dso16975198pjj.1 for ; Mon, 30 Jan 2023 13:48:53 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:48:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+sAayCS/0n8o12l1+Nu9dY41aCtQpJmApolHzbMbLL8=; b=tUh80N8uFJZClUMRZfqZukluYyq8gN4eLL3YXKy0ksYbFzfXSSN6JNsVEZvmOdMMCV cQpN83guKaTLOJuY1kK0iRrCkwSYXo4xI4mUUsFVl98jo3owyGyGaMrxXKpWJlvIRyEu Cw61FN/+vEWaskhsF6BgeBDUmAFbF7Gha9E+abXamKVM9P8eh1eN0mRXTCv553/P9vB5 rg12Z075FGkG4RBwzT46CoFGP86C22Ih205cC1Tp29P6xLuY3wSPDzVWKHvnWemwFnGQ lkpTNHT4OD2t246oODPkwhpOcGEfGe9QueavKWJGedZiRZYKVITPivuli7T7J6YYdWet bqxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+sAayCS/0n8o12l1+Nu9dY41aCtQpJmApolHzbMbLL8=; b=BDQp6bld6vMazqotZYKyeaFNPu8FpQKkoMoCZg0fzxuEc2oS1AKKoF5IPJKZciNOY9 wip/Pt/5I0viU/xnWdUta5Kk8NSevrC5EaIsNrJQ9fxa4x22fuF8ILklvzqDkWqnCpc+ MRMbvwbe668RTGCUOGc9dnr38Tq8Hqa5c0cDrgHU1tqKgGOMosOUpdCwbAv85p7PV3PQ FTyBzx5mSyXt9LhRZfVt3bakUJbpF+Pb/iCkGz7NmU59pHAD4+DGUbJCfF7x2AIXair9 cJBP/8VCcWFe6GDDhsQIYb+TqF4gkG4ZHlPsYZPQqWgZmfcLVUwNNgsQ3G8xglwq9y5n 0QKA== X-Gm-Message-State: AO0yUKVKMK9tTvR0T8ocZ/1fB0KsNp2+9f0nxtPEbShRF7mRl7/ZhkzE HvotiyOrc9pQauAs7oWB6BsNIw6ief/vYnZH X-Google-Smtp-Source: AK7set+2z9sFpP/yjprCLfrTr/xkreWXP9DdajN4FulmJ+4vdonL2RaJbjG/UNeMtN0OfPqjTV26bQ== X-Received: by 2002:a17:90b:33ce:b0:22b:ec81:c36c with SMTP id lk14-20020a17090b33ce00b0022bec81c36cmr26846711pjb.45.1675115332671; Mon, 30 Jan 2023 13:48:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 02/36] tcg: Handle dh_typecode_i128 with TCG_CALL_{RET, ARG}_NORMAL Date: Mon, 30 Jan 2023 11:48:10 -1000 Message-Id: <20230130214844.1158612-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1675115397540100001 Many hosts pass and return 128-bit quantities like sequential 64-bit quantities. Treat this just like we currently break down 64-bit quantities for a 32-bit host. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg.c | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index d502327be2..ffddda96ed 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -707,11 +707,22 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_s64: info->nr_out =3D 64 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; + assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); + break; + case dh_typecode_i128: + info->nr_out =3D 128 / TCG_TARGET_REG_BITS; + info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ + switch (/* TODO */ TCG_CALL_RET_NORMAL) { + case TCG_CALL_RET_NORMAL: + assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); + break; + default: + qemu_build_not_reached(); + } break; default: g_assert_not_reached(); } - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); =20 /* * Parse and place function arguments. @@ -733,6 +744,9 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_ptr: type =3D TCG_TYPE_PTR; break; + case dh_typecode_i128: + type =3D TCG_TYPE_I128; + break; default: g_assert_not_reached(); } @@ -772,6 +786,19 @@ static void init_call_layout(TCGHelperInfo *info) } break; =20 + case TCG_TYPE_I128: + switch (/* TODO */ TCG_CALL_ARG_NORMAL) { + case TCG_CALL_ARG_EVEN: + layout_arg_even(&cum); + /* fall through */ + case TCG_CALL_ARG_NORMAL: + layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); + break; + default: + qemu_build_not_reached(); + } + break; + default: g_assert_not_reached(); } @@ -1690,11 +1717,13 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) op->args[pi++] =3D temp_arg(ret); break; case 2: + case 4: tcg_debug_assert(ret !=3D NULL); - tcg_debug_assert(ret->base_type =3D=3D ret->type + 1); + tcg_debug_assert(ret->base_type =3D=3D ret->type + ctz32(n)); tcg_debug_assert(ret->temp_subindex =3D=3D 0); - op->args[pi++] =3D temp_arg(ret); - op->args[pi++] =3D temp_arg(ret + 1); + for (i =3D 0; i < n; ++i) { + op->args[pi++] =3D temp_arg(ret + i); + } break; default: g_assert_not_reached(); --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115626; cv=none; d=zohomail.com; s=zohoarc; b=BZAraFUaiZ8WUIXxSDa4dJwkJrkxEZguOndEcjgZBDG5DBMP4nxkSz66BW2bUs0yUlQEt6kCaA666KwVk9xRouTU7sXnDFWtb/EBLgDH8gxu3fa+mhBQnRiVjZIiEe4ONHnjDka7x6uXA3r7JwgWfoIbye2whLb7+wLc00T134w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115626; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tk5ThUejyy0sfkaXylh35ElIxwLbKgRuWHGH5cw50Nk=; b=WHKAaL0RD44WhD4Yevai2mByiIGWKWhO5TqUbAS8OTvLF3m1gbbSphQxv6HJfgDm2ty2gtNCQUh9kksrvQwn3W96k0PF7HnUVtxRg6I7sC5Yo1eoBouCALHrXjLX5jm4oLBmdg2l0ZacuD0CQUxSgOGadsUV7rpM9KcEhKqftLw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16751156263001006.9253721657441; Mon, 30 Jan 2023 13:53:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1L-0001sU-Ax; Mon, 30 Jan 2023 16:48:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1J-0001rg-8T for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:48:57 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1H-0005aI-OE for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:48:57 -0500 Received: by mail-pl1-x635.google.com with SMTP id be8so13091482plb.7 for ; Mon, 30 Jan 2023 13:48:55 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:48:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tk5ThUejyy0sfkaXylh35ElIxwLbKgRuWHGH5cw50Nk=; b=u9OLRC/JmmArh/zf4zkx8bPuUMTF7T5QocQDWCMd7DdsvxQ+OftwgrI/XvPE50+elW ud+EKcih1Yaz9VAct3B+iCPHtDHuwaTyzw/cJfSxSyAq6kfLEujYAYkigwqhx6Q/PJsN 5qSn5G5fOORRMyj1lXrGWPCbw5otaWyEyfqaCKDr8WwsQL4U8fxA6hDb2krRLqndMkrc aLQmLp6QIe2CV7+tf3lBLPeKtxda+ZKGy5TpzueT/QS5a3dNmADfnoKHfDWIISnm60dY Wrf5yvwbPlPp0yxpD79OHGup+zCqEtyojfnPp3P0PhkJwVV9DESv2Lpr33ql/GJwvBNC f/eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tk5ThUejyy0sfkaXylh35ElIxwLbKgRuWHGH5cw50Nk=; b=h9TezddgWh6fkxmznRCnrkr2D2nG8HSOWMgrP+Zb2RJ+hQ5synstAObwDrnCfWtVy6 DyjBjOduRqNNcbrUO/zfs4EZh3QKXYEHq940nIB7sAdPw7LSHU4HajZqlWH27O5XAisY ynn2jd+m/66co73f8+DfkxVGeNjXqb/TTr2HA98CwuAOVyZgr0PF1w/WlbioQXAFTShh opq1ds7HJxIdeONXBN9ocSJGDVWqi2G5PIpjnts+6Pt18ikfLVHTx6bP0XlbfZiprLnn j+8kirj+PTEUOh9CbjQgr5N05tL5SekvR3Pnn6ykj9K3buhFUBWh37jvf0piuTAcLDkD qQOg== X-Gm-Message-State: AFqh2kppNNXgeZ1TnS/0A12ud1C0iMonR4zpQis2PSxBIWSzlYO7GHG8 Mqfryu+dc3Ve3t2Ya6eEaxsQMs5a0nV29+Mf X-Google-Smtp-Source: AMrXdXsVLVqZzjJdrQu9zN2R/H7wHzuaEJbs8WcHCdgASHwNrE10NhSnvqLuKsZvkAyuNUlSNwVjww== X-Received: by 2002:a17:90a:428c:b0:223:b920:28df with SMTP id p12-20020a17090a428c00b00223b92028dfmr53256724pjg.29.1675115334156; Mon, 30 Jan 2023 13:48:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 03/36] tcg: Allocate objects contiguously in temp_allocate_frame Date: Mon, 30 Jan 2023 11:48:11 -1000 Message-Id: <20230130214844.1158612-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115627602100004 When allocating a temp to the stack frame, consider the base type and allocate all parts at once. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index ffddda96ed..25e92ef5d6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3264,11 +3264,12 @@ static bool liveness_pass_2(TCGContext *s) =20 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { - int size =3D tcg_type_size(ts->type); - int align; intptr_t off; + int size, align; =20 - switch (ts->type) { + /* When allocating an object, look at the full type. */ + size =3D tcg_type_size(ts->base_type); + switch (ts->base_type) { case TCG_TYPE_I32: align =3D 4; break; @@ -3299,13 +3300,30 @@ static void temp_allocate_frame(TCGContext *s, TCGT= emp *ts) tcg_raise_tb_overflow(s); } s->current_frame_offset =3D off + size; - - ts->mem_offset =3D off; #if defined(__sparc__) - ts->mem_offset +=3D TCG_TARGET_STACK_BIAS; + off +=3D TCG_TARGET_STACK_BIAS; #endif - ts->mem_base =3D s->frame_temp; - ts->mem_allocated =3D 1; + + /* If the object was subdivided, assign memory to all the parts. */ + if (ts->base_type !=3D ts->type) { + int part_size =3D tcg_type_size(ts->type); + int part_count =3D size / part_size; + + /* + * Each part is allocated sequentially in tcg_temp_new_internal. + * Jump back to the first part by subtracting the current index. + */ + ts -=3D ts->temp_subindex; + for (int i =3D 0; i < part_count; ++i) { + ts[i].mem_offset =3D off + i * part_size; + ts[i].mem_base =3D s->frame_temp; + ts[i].mem_allocated =3D 1; + } + } else { + ts->mem_offset =3D off; + ts->mem_base =3D s->frame_temp; + ts->mem_allocated =3D 1; + } } =20 /* Assign @reg to @ts, and update reg_to_temp[]. */ --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115401; cv=none; d=zohomail.com; s=zohoarc; b=SK6yD3gG/Qn0TmplxvqXQJnzKrcMSSc74Y2qYtwOBuRhWQSvRZmjT/rBLPnyL712NqB6xKfBDqxPYwuZJEqvwV0ECZHZzoWQIr63BW+QWP/l53LkP6xjy92GldVrjnpIvS5Rf091IWNZLQHsvnaWelLiQlevoK9YI0g/wa+kYr4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115401; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GXlXIPtXNt2W+A348dVxlHjgDY0npIwyo0rpVACLYDo=; b=lH5J18mfUzT4JwrG49lKCEfAaCvOL+F15OSrIqkPIvgY3ymQG1RrU68w54fBW7b6xfjMFpNtl/+pSDL3oHAyN5wKD4uPdAQEOwQEhb5RCPtDCZGaq8eM0MCgzXRMfW8y6/uZryDFtccHt/VkFG3C2AAHBu+YlDoRKVGhhqX5ZsA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115401707170.1028739507733; Mon, 30 Jan 2023 13:50:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1M-0001ss-Pq; Mon, 30 Jan 2023 16:49:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1L-0001sS-5w for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:48:59 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1I-0005a1-Iq for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:48:58 -0500 Received: by mail-pj1-x1035.google.com with SMTP id e10-20020a17090a630a00b0022bedd66e6dso16975340pjj.1 for ; Mon, 30 Jan 2023 13:48:56 -0800 (PST) Received: from stoup.. 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Add stubs for all other backends. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 ++ tcg/aarch64/tcg-target.c.inc | 7 +++++++ tcg/arm/tcg-target.c.inc | 20 ++++++++++++++++++++ tcg/i386/tcg-target.c.inc | 8 ++++++++ tcg/loongarch64/tcg-target.c.inc | 7 +++++++ tcg/mips/tcg-target.c.inc | 7 +++++++ tcg/ppc/tcg-target.c.inc | 7 +++++++ tcg/riscv/tcg-target.c.inc | 7 +++++++ tcg/s390x/tcg-target.c.inc | 7 +++++++ tcg/sparc64/tcg-target.c.inc | 7 +++++++ tcg/tci/tcg-target.c.inc | 7 +++++++ 11 files changed, 86 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index 25e92ef5d6..0cedfe316b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -104,6 +104,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g) + __attribute__((unused)); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); static void tcg_out_op(TCGContext *s, TCGOpcode opc, diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 330d26b395..bd6da72678 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1102,6 +1102,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type= , TCGReg rd, tcg_out_insn(s, 3305, LDR, 0, rd); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + /* Define something more legible for general use. */ #define tcg_out_ldst_r tcg_out_insn_3310 =20 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0f5f9f4925..6e9e9b9b3f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2581,6 +2581,26 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi32(s, COND_AL, ret, arg); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + int enc, opc =3D ARITH_ADD; + + /* All of the easiest immediates to encode are positive. */ + if (imm < 0) { + imm =3D -imm; + opc =3D ARITH_SUB; + } + enc =3D encode_imm(imm); + if (enc >=3D 0) { + tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); + tcg_out_dat_reg(s, COND_AL, opc, rd, rs, + TCG_REG_TMP, SHIFT_IMM_LSL(0)); + } +} + /* Type is always V128, with I64 elements. */ static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg r= h) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index c71c3e664d..7b573bd287 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1069,6 +1069,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + tcg_out_modrm_offset(s, OPC_LEA, rd, rs, imm); +} + static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) { if (val =3D=3D (int8_t)val) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index ce4a153887..b6e2ff6213 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -417,6 +417,13 @@ static void tcg_out_addi(TCGContext *s, TCGType type, = TCGReg rd, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_andi(s, ret, arg, 0xff); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 6e000d8e69..d419c4c1fc 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -550,6 +550,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int fla= gs) { /* ret and arg can't be register tmp0 */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 8d6899cf40..85f84fe59e 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1125,6 +1125,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type= , TCGReg ret, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static bool mask_operand(uint32_t c, int *mb, int *me) { uint32_t lsb, test; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 01cb67ef7b..383331025a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -559,6 +559,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, = TCGReg rd, tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 218318feb2..d8fd755ef0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1073,6 +1073,13 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTyp= e type, TCGArg val, return false; } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); +} + static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, int msb, int lsb, int ofs, int z) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index dd406bc065..4b834f3f1e 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -496,6 +496,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, TCGReg a2, int op) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index bc452007c6..33551b43dc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -557,6 +557,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, const TCGHelperInfo *info) { --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.48.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:48:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YYp288Frvbt6OWFjpqbemBc0raem/o/jhP5zjAY/7EY=; b=ncxUI3Kn08Fz9Tx0WF9BdScOFZPaKxk51kpEk++GHhzpLfqFmV1/oY9TiTO8D1uojP voI+tNC14VNm+es1bHffkyNvR3hj8E4SdwQNxLOUrVQbII0LfG1Ap+vzCgETytZtpZUE mLNrEHuoPfS3dKzrojyIdvb6kofFUfmCqFznzvRHrHmJgtBESDeyDGtge965ylVXzVvb T04vhky6AxnrRGpKs9W35GzSNvH3HQl2q3OfP09WyYkgV+7S1Igd+qX3XUTjlu7mcivP u2bDY9oLdoCFOkSNWBSybH/0QtJD8CcaJ5QPGINdJu2jO0sUlOThz3lMI3yeviGDag+Y rRqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YYp288Frvbt6OWFjpqbemBc0raem/o/jhP5zjAY/7EY=; b=gFZSc21nRXKjg9stgimA+O+zsYAJ7WOZKFRN4FJhjx6IAt88OgJM3jqc0gq/NtBJap gHa3TWvyZ45yqACjhlnxpwhDWZB8d6Zv9HUWbQp1vpX65re2H+p8mgxZ9El9jUeh1/dO QnrK9NRcLG4CFH7U10oYzYfgVbZK59WoAtmbOcWlcBoB1VrD+CNQdjI3Lr300xpvCRJb 0tstfUgo6Krrmv8E7rCWVLWJqM8L1Bao9anSWVq1nPn79KxA1/HXTSueaaJ2QBGqdCV6 F7q4w74wJP6e7ZN7H75Jt4bPoTv5P2TuIqOAADc2pZ2etfJl47AiZ/3887u/0Vohrt9c a/kQ== X-Gm-Message-State: AO0yUKUe2oo21ucNJK5QIn5y2nms3UoQQzZhhQD4n2MVHt/b109FPDdr 8lqMASLEFf8V+WreHKsn2PuJsAWyTvccdcrN X-Google-Smtp-Source: AK7set//0G5lyes8HsHIKQIapdzrVLKvr8Iun6hG/Bj+tWQp21OLRxTgzLqhWWjMbPka1/NzmrWIIg== X-Received: by 2002:a17:90b:3907:b0:22c:838:c27d with SMTP id ob7-20020a17090b390700b0022c0838c27dmr10736758pjb.6.1675115337316; Mon, 30 Jan 2023 13:48:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 05/36] tcg: Add TCG_CALL_{RET,ARG}_BY_REF Date: Mon, 30 Jan 2023 11:48:13 -1000 Message-Id: <20230130214844.1158612-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115535210100010 Content-Type: text/plain; charset="utf-8" These will be used by some hosts, both 32 and 64-bit, to pass and return i128. Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg-internal.h | 3 + tcg/tcg.c | 135 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 135 insertions(+), 3 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 6e50aeba3a..2ec1ea01df 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -36,6 +36,7 @@ */ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ + TCG_CALL_RET_BY_REF, /* for i128, by reference */ } TCGCallReturnKind; =20 typedef enum { @@ -44,6 +45,8 @@ typedef enum { TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ + TCG_CALL_ARG_BY_REF, /* for i128, by reference, first */ + TCG_CALL_ARG_BY_REF_N, /* ... by reference, subsequent */ } TCGCallArgumentKind; =20 typedef struct TCGCallArgumentLoc { diff --git a/tcg/tcg.c b/tcg/tcg.c index 0cedfe316b..7db48f3305 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -104,8 +104,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g) - __attribute__((unused)); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); static void tcg_out_op(TCGContext *s, TCGOpcode opc, @@ -683,6 +682,38 @@ static void layout_arg_normal_n(TCGCumulativeArgs *cum, cum->arg_slot +=3D n; } =20 +static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) +{ + TCGCallArgumentLoc *loc =3D &info->in[cum->info_in_idx]; + int n =3D 128 / TCG_TARGET_REG_BITS; + + /* The first subindex carries the pointer. */ + layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); + + /* + * The callee is allowed to clobber memory associated with + * structure pass by-reference. Therefore we must make copies. + * Allocate space from "ref_slot", which will be adjusted to + * follow the parameters on the stack. + */ + loc[0].ref_slot =3D cum->ref_slot; + + /* + * Subsequent words also go into the reference slot, but + * do not accumulate into the regular arguments. + */ + for (int i =3D 1; i < n; ++i) { + loc[i] =3D (TCGCallArgumentLoc){ + .kind =3D TCG_CALL_ARG_BY_REF_N, + .arg_idx =3D cum->arg_idx, + .tmp_subindex =3D i, + .ref_slot =3D cum->ref_slot + i, + }; + } + cum->info_in_idx +=3D n; + cum->ref_slot +=3D n; +} + static void init_call_layout(TCGHelperInfo *info) { int max_reg_slots =3D ARRAY_SIZE(tcg_target_call_iarg_regs); @@ -718,6 +749,14 @@ static void init_call_layout(TCGHelperInfo *info) case TCG_CALL_RET_NORMAL: assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); break; + case TCG_CALL_RET_BY_REF: + /* + * Allocate the first argument to the output. + * We don't need to store this anywhere, just make it + * unavailable for use in the input loop below. + */ + cum.arg_slot =3D 1; + break; default: qemu_build_not_reached(); } @@ -796,6 +835,9 @@ static void init_call_layout(TCGHelperInfo *info) case TCG_CALL_ARG_NORMAL: layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); break; + case TCG_CALL_ARG_BY_REF: + layout_arg_by_ref(&cum, info); + break; default: qemu_build_not_reached(); } @@ -811,7 +853,39 @@ static void init_call_layout(TCGHelperInfo *info) assert(cum.info_in_idx <=3D ARRAY_SIZE(info->in)); /* Validate the backend has enough argument space. */ assert(cum.arg_slot <=3D max_reg_slots + max_stk_slots); - assert(cum.ref_slot <=3D max_stk_slots); + + /* + * Relocate the "ref_slot" area to the end of the parameters. + * Minimizing this stack offset helps code size for x86, + * which has a signed 8-bit offset encoding. + */ + if (cum.ref_slot !=3D 0) { + int ref_base =3D 0; + + if (cum.arg_slot > max_reg_slots) { + int align =3D __alignof(Int128) / sizeof(tcg_target_long); + + ref_base =3D cum.arg_slot - max_reg_slots; + if (align > 1) { + ref_base =3D ROUND_UP(ref_base, align); + } + } + assert(ref_base + cum.ref_slot <=3D max_stk_slots); + + if (ref_base !=3D 0) { + for (int i =3D cum.info_in_idx - 1; i >=3D 0; --i) { + TCGCallArgumentLoc *loc =3D &info->in[i]; + switch (loc->kind) { + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_N: + loc->ref_slot +=3D ref_base; + break; + default: + break; + } + } + } + } } =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; @@ -1738,6 +1812,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) =20 switch (loc->kind) { case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_N: op->args[pi++] =3D temp_arg(ts); break; =20 @@ -4408,6 +4484,27 @@ static void load_arg_normal(TCGContext *s, const TCG= CallArgumentLoc *l, } } =20 +static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base, + intptr_t ref_off, TCGRegSet *allocated_regs) +{ + TCGReg reg; + int stk_slot =3D arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); + + if (stk_slot < 0) { + reg =3D tcg_target_call_iarg_regs[arg_slot]; + tcg_reg_free(s, reg, *allocated_regs); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_regset_set_reg(*allocated_regs, reg); + } else { + reg =3D tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], + *allocated_regs, 0, false); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + stk_slot * sizeof(tcg_target_long)); + } +} + static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs =3D TCGOP_CALLO(op); @@ -4431,6 +4528,16 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) case TCG_CALL_ARG_EXTEND_S: load_arg_normal(s, loc, ts, &allocated_regs); break; + case TCG_CALL_ARG_BY_REF: + load_arg_stk(s, loc->ref_slot, ts, allocated_regs); + load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + loc->ref_slot * sizeof(tcg_target_long), + &allocated_regs); + break; + case TCG_CALL_ARG_BY_REF_N: + load_arg_stk(s, loc->ref_slot, ts, allocated_regs); + break; default: g_assert_not_reached(); } @@ -4462,6 +4569,19 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) save_globals(s, allocated_regs); } =20 + /* + * If the ABI passes a pointer to the returned struct as the first + * argument, load that now. Pass a pointer to the output home slot. + */ + if (info->out_kind =3D=3D TCG_CALL_RET_BY_REF) { + TCGTemp *ts =3D arg_temp(op->args[0]); + + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_r= egs); + } + tcg_out_call(s, tcg_call_func(op), info); =20 /* Assign output registers and emit moves if needed. */ @@ -4478,6 +4598,15 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) ts->mem_coherent =3D 0; } break; + + case TCG_CALL_RET_BY_REF: + /* The callee has performed a write through the reference. */ + for (i =3D 0; i < nb_oargs; i++) { + TCGTemp *ts =3D arg_temp(op->args[i]); + ts->val_type =3D TEMP_VAL_MEM; + } + break; + default: g_assert_not_reached(); } --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115493; cv=none; d=zohomail.com; s=zohoarc; b=GeBsXxoRfTtxzavBQsv3akxQjajFZHUXIsz30OcaaQEe+JJcpsWUI3WvNKyMacDulMWl5IOdADMvmsmMhX0vFM5u37Pg+WymamNhXkM5zB6YjG9sy3v9iMWv6ZVh6UoVh4Ru0P2vM8KI0ESys2eCA+YCHGOovQZstKVuiwAA6eE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115493; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+MGF5fY7CpzMCha1QCJz5b5ZUtyWP+UPCXR4xqFsxtY=; b=Hsz4LtmZutrNwzknnV4jVtFzCiBYz9NrLNm+Mcf3taYbdpSCrTv5GUZEkJa+TE8qtPi/2gYqlTdkOdlZZi3kVDkZm0zMAn5Z2iEOvywYU5WrLtsNMPwM21TCyk9Ob9PyeVRanspqwzMjLzAn1kmBDhz69lX41fdbIu8j/hKLl3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115493880536.5413841936625; Mon, 30 Jan 2023 13:51:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1P-0001u8-S4; Mon, 30 Jan 2023 16:49:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1O-0001tM-K4 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:02 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1M-0005bL-HT for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:02 -0500 Received: by mail-pj1-x1030.google.com with SMTP id cq16-20020a17090af99000b0022c9791ac39so4585562pjb.4 for ; Mon, 30 Jan 2023 13:49:00 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.48.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:48:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+MGF5fY7CpzMCha1QCJz5b5ZUtyWP+UPCXR4xqFsxtY=; b=LySnqB4TkC0+PAm6nils1l05yu3Crs0zHeeXXbOrEV2i7Y8/zsqih5QWqrpWVcxc/5 8QuT14+BxFq7N+tQIKpSS1xqkanBPjOU8Qxii0z90coSDPLwXyTIYD5kQ8lzKdbwKgcC JLvQBN+1alYp8AW5LiF+kqdGlBo4akjM+8R4TDFyqEzu/xWL16OlYld0JzNRJg99/iSC PUkxdRXSkwveipn1q/U4sML4kvp6SkPplTFOCblo+JYgbQjwDD1TFXb7kWJAfSoEWqBe 4B2bVkfuY9psGsgKvmgRIdA66Ao8hh6eZ1dy7c6K1btlwniKlOjLP3QrpTl3XowzSk8x g5jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+MGF5fY7CpzMCha1QCJz5b5ZUtyWP+UPCXR4xqFsxtY=; b=IUJTGL7Y2Kmo+b99f/6J5bHOp4QwKPyqYQKodqLxKJ6BfhPgZdafZe3T42VGX6N/aG MKwtih4TWnnXjIGKwg+5WQXzyRyf9cwbOT2N8aNDWsWU+OpnuJ1DPnO7LxyUBMwIZUKB g+ggCuihtKoYziBx8nr19rHKpkxeRIABbD3aNTZMczbACPftz1ZbUrwtW3WZnXghGx+R ti+ASm6MfTBSk9+xWQ2pyYSIb8WMzwXnSUotk96nqYQR/sdQV6CKPa+pkrVtX5IWBVoX 5neWgk/GtNH9n26TVyPv8M/qH1RH/m9bIbRnOJpEKvjvELju7TSjTHGuq1SM6O7X960T tg2Q== X-Gm-Message-State: AFqh2krbtPYJ37krj2e3qXoAiqYYq/gJ9dC50AiSVXzqsJ308b09BqJh VrsOsmmXgoEfQ0m2f3NgJUcsgFZqlo0q31Ep X-Google-Smtp-Source: AMrXdXv1zzl2AhH99tHxXgGasowtNXaApnO2INZne2xHFZYUEeTbRMDuw3z0B7axotQf/jKJvIH0uQ== X-Received: by 2002:a17:90a:b798:b0:229:d641:9ef2 with SMTP id m24-20020a17090ab79800b00229d6419ef2mr45754229pjr.40.1675115339009; Mon, 30 Jan 2023 13:48:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v6 06/36] tcg: Introduce tcg_target_call_oarg_reg Date: Mon, 30 Jan 2023 11:48:14 -1000 Message-Id: <20230130214844.1158612-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115495265100003 Replace the flat array tcg_target_call_oarg_regs[] with a function call including the TCGCallReturnKind. Extend the set of registers for ARM to r0-r3 to match the ABI: https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#result= -return Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/tcg.c | 9 ++++++--- tcg/aarch64/tcg-target.c.inc | 10 +++++++--- tcg/arm/tcg-target.c.inc | 10 +++++++--- tcg/i386/tcg-target.c.inc | 16 ++++++++++------ tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- tcg/mips/tcg-target.c.inc | 10 ++++++---- tcg/ppc/tcg-target.c.inc | 10 ++++++---- tcg/riscv/tcg-target.c.inc | 10 ++++++---- tcg/s390x/tcg-target.c.inc | 9 ++++++--- tcg/sparc64/tcg-target.c.inc | 12 ++++++------ tcg/tci/tcg-target.c.inc | 12 ++++++------ 11 files changed, 72 insertions(+), 46 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 7db48f3305..5d321e7e82 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -151,6 +151,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TC= GArg val, TCGReg base, intptr_t ofs); static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, const TCGHelperInfo *info); +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); @@ -740,14 +741,16 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_s64: info->nr_out =3D 64 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); + /* Query the last register now to trigger any assert early. */ + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; case dh_typecode_i128: info->nr_out =3D 128 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ switch (/* TODO */ TCG_CALL_RET_NORMAL) { case TCG_CALL_RET_NORMAL: - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); + /* Query the last register now to trigger any assert early. */ + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; case TCG_CALL_RET_BY_REF: /* @@ -4589,7 +4592,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) case TCG_CALL_RET_NORMAL: for (i =3D 0; i < nb_oargs; i++) { TCGTemp *ts =3D arg_temp(op->args[i]); - TCGReg reg =3D tcg_target_call_oarg_regs[i]; + TCGReg reg =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i= ); =20 /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index bd6da72678..fde3b30ad1 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -63,9 +63,13 @@ static const int tcg_target_call_iarg_regs[8] =3D { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 }; -static const int tcg_target_call_oarg_regs[1] =3D { - TCG_REG_X0 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_X0 + slot; +} =20 #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 6e9e9b9b3f..d06ac60c15 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -79,9 +79,13 @@ static const int tcg_target_reg_alloc_order[] =3D { static const int tcg_target_call_iarg_regs[4] =3D { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 }; -static const int tcg_target_call_oarg_regs[2] =3D { - TCG_REG_R0, TCG_REG_R1 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_R0 + slot; +} =20 #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 7b573bd287..2f0a9521bf 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -109,12 +109,16 @@ static const int tcg_target_call_iarg_regs[] =3D { #endif }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_EAX, -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_REG_EDX -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + switch (kind) { + case TCG_CALL_RET_NORMAL: + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return slot ? TCG_REG_EDX : TCG_REG_EAX; + default: + g_assert_not_reached(); + } +} =20 /* Constants we accept. */ #define TCG_CT_CONST_S32 0x100 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index b6e2ff6213..c5f55afd68 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -114,10 +114,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_A0 + slot; +} =20 #ifndef CONFIG_SOFTMMU #define USE_GUEST_BASE (guest_base !=3D 0) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d419c4c1fc..80748d892e 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -136,10 +136,12 @@ static const TCGReg tcg_target_call_iarg_regs[] =3D { #endif }; =20 -static const TCGReg tcg_target_call_oarg_regs[2] =3D { - TCG_REG_V0, - TCG_REG_V1 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_V0 + slot; +} =20 static const tcg_insn_unit *tb_ret_addr; static const tcg_insn_unit *bswap32_addr; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 85f84fe59e..f3fec14118 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -186,10 +186,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R10 }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R3, - TCG_REG_R4 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_R3 + slot; +} =20 static const int tcg_target_callee_save_regs[] =3D { #ifdef _CALL_DARWIN diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 383331025a..558de127ef 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,10 +113,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_A0 + slot; +} =20 #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d8fd755ef0..844532156b 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -402,9 +402,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R6, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R2, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot =3D=3D 0); + return TCG_REG_R2; +} =20 #define S390_CC_EQ 8 #define S390_CC_LT 4 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 4b834f3f1e..ccc4144f7c 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -132,12 +132,12 @@ static const int tcg_target_call_iarg_regs[6] =3D { TCG_REG_O5, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_O0 + slot; +} =20 #define INSN_OP(x) ((x) << 30) #define INSN_OP2(x) ((x) << 22) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 33551b43dc..e3b0ff303f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -200,12 +200,12 @@ static const int tcg_target_reg_alloc_order[] =3D { /* No call arguments via registers. All will be stored on the "stack". */ static const int tcg_target_call_iarg_regs[] =3D { }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R0, -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_REG_R1 -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot < 64 / TCG_TARGET_REG_BITS); + return TCG_REG_R0 + slot; +} =20 #ifdef CONFIG_DEBUG_TCG static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115542; cv=none; d=zohomail.com; s=zohoarc; b=jaAZKhR92GwTI4yu/ilPzmtBv7DN31PXcVPNlfPUvdj5nwYzK9CmH0xD1SjC4qYJJ2f0xpIq48SQMCAu1o/qt0/FBPRs58BoqNHOjlfzh4Cw66YrIJTjNHXmq86W4CBIHDj612qWKfDO4588wO0hRU/fIkQ7eg2LDu8NBspkUOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115542; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=enoyLDYZPbuMXIEMCUDcqm9A2zJNeFfelrYBMwbxjgg=; b=m7CqhWaJ3h1BQwkYdILU9wj5ueHnhXptjDvoxuY6zYuJy5ApLGByKq8dgN2C406fq6Ypl6F0hsgfKxf6Fia13K1yISQp5jcJ+CD7r3oOF6P3+pBq8yytzPBOAKRBD6MreZC44vHiS3ScEJfWkSrHXiYaLCCYWd88BNh2UcO7P78= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115542185705.9942791955701; Mon, 30 Jan 2023 13:52:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1R-0001uP-Eq; Mon, 30 Jan 2023 16:49:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1P-0001tx-Ji for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:03 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1O-0005bg-0l for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:03 -0500 Received: by mail-pl1-x633.google.com with SMTP id d3so13065851plr.10 for ; Mon, 30 Jan 2023 13:49:01 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=enoyLDYZPbuMXIEMCUDcqm9A2zJNeFfelrYBMwbxjgg=; b=LLTWegc1BbfoHUYPNNwxJ2Uvu2MWoeWnB9wizPJaEsCWp65nrehFFDn9pKL/P5Soy9 r6KHa/iF8Vs0351KWptqt2XONkR1+XFhbCdQuiQ0Q39ajKIG9+/eeZBCOHBmG9j1iC+C 2L18UMTy/o3faGmMxDh8MFou5nFl/nXNOopuQadgMKLwjpnNJHS9QSBG4UhECh14Nh44 8U9i/F7S+4x8mzce+aXzOEjAVeBZph2jqUM7E9Iy9wO16Xmo7Y7dgjku0bjw9YwOMXpQ Gr2sevzw+ejZdLdhpAQYokvSFVdeYIftoT5Jw2y8s4U1BpHYWIrfElJjjbsvuRlrONth 7Lwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=enoyLDYZPbuMXIEMCUDcqm9A2zJNeFfelrYBMwbxjgg=; b=aYLIQukvp3HXkwZqz/xJRZceaAoHhq4kMv0sGRfATuglYZRyvahwJBy38D5WMXkcYm mF//7LozN/nQLQd2xhAAbbgU9r6WPcChIap4PRllndtioBStJcP55bPqopQxFm0qzlax kEzXL35ZQSXajpTJgL8tS0YW69/zgM7bbTtsuqD8kLhacjDiD+Cqb+rk00hJdKXKJibZ NbzAJSMw+MpmCHYE8PAciZCv27iqD5qtlG1JTPS5ndtWjlnEg/DfuNFmokwDQwnuqDdk ho/IqPNF0gLVpUuKvhRK9Z8eJL9PvpyM+X2TPE6wIlEzpQwxHAgzEGKDSMQ+SWgvTp+W u0dw== X-Gm-Message-State: AO0yUKUTJc2Q6IP8zdYpVQOwoKPJxjoun1Axx61t1qCmV2MTqHSx7xwd tnTGg5iPsI+pSiGWBzGlGfTy4doViuBWzVjH X-Google-Smtp-Source: AK7set8VRjT2n9wKipKMz8L9a81jMMVO06Y1noFzhjWb/uhpHorUYWpS2xTFOFwvGUheWa7hRJB7Sw== X-Received: by 2002:a17:90b:1b4a:b0:22b:f93b:b5c0 with SMTP id nv10-20020a17090b1b4a00b0022bf93bb5c0mr25283475pjb.44.1675115340513; Mon, 30 Jan 2023 13:49:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 07/36] tcg: Add TCG_CALL_RET_BY_VEC Date: Mon, 30 Jan 2023 11:48:15 -1000 Message-Id: <20230130214844.1158612-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115543255100007 This will be used by _WIN64 to return i128. Not yet used, because allocation is not yet enabled. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 1 + tcg/tcg.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2ec1ea01df..33f1d8b411 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -37,6 +37,7 @@ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ TCG_CALL_RET_BY_REF, /* for i128, by reference */ + TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ } TCGCallReturnKind; =20 typedef enum { diff --git a/tcg/tcg.c b/tcg/tcg.c index 5d321e7e82..edc6185bf4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -752,6 +752,10 @@ static void init_call_layout(TCGHelperInfo *info) /* Query the last register now to trigger any assert early. */ tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; + case TCG_CALL_RET_BY_VEC: + /* Query the single register now to trigger any assert early. = */ + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); + break; case TCG_CALL_RET_BY_REF: /* * Allocate the first argument to the output. @@ -4602,6 +4606,21 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) } break; =20 + case TCG_CALL_RET_BY_VEC: + { + TCGTemp *ts =3D arg_temp(op->args[0]); + + tcg_debug_assert(ts->base_type =3D=3D TCG_TYPE_I128); + tcg_debug_assert(ts->temp_subindex =3D=3D 0); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + tcg_out_st(s, TCG_TYPE_V128, + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), + ts->mem_base->reg, ts->mem_offset); + } + /* fall through to mark all parts in memory */ + case TCG_CALL_RET_BY_REF: /* The callee has performed a write through the reference. */ for (i =3D 0; i < nb_oargs; i++) { --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115383; cv=none; d=zohomail.com; s=zohoarc; b=aqjrIb7zvkhEmiOKdKwV5ktgDXYlImcxKkSh13/iIK7oMmH0uGk+tXdgyNy22JNYqia0Xx3l6scmF1NTUzmtFkhG+XP5uLoVNhMCFRHrsLBjZ6WWgqQmRmOPtg71o4m0XVlQi6T2Sx7dCBANELn4T6iFM6L0ipEyaW1n2kMKgoY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115383; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LLPIf7qXwEodLjL1V+df+mpIrgJgFYuNvN+PgAflmco=; b=IN9rpt5lc0Gae5KD9moEnhWDkUeONwpfaWW01tk5UpRKNsYXpoepdQjehWtCisxQJwA0GTVHoe/9xhJtoWW0GIiKn5BE5mRH+i6WIXUAIp2M41T4QkmSBKOm6VoSrhbad/5XPwXNDW5/l0yvEpRysMavMSyq3zrJoXzokYndBNg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115383325759.3433841700759; Mon, 30 Jan 2023 13:49:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1T-0001vX-42; Mon, 30 Jan 2023 16:49:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1R-0001uJ-8a for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:05 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1P-0005bs-Fu for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:05 -0500 Received: by mail-pl1-x62d.google.com with SMTP id e6so4874699plg.12 for ; Mon, 30 Jan 2023 13:49:03 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LLPIf7qXwEodLjL1V+df+mpIrgJgFYuNvN+PgAflmco=; b=RZQgOwN4N/hpDsPELDszNPgZaPtn5MjHCVp9TIwftxV9ib7Lkho77oWtFqUMK0gk9J 3TAWapps7RA20yCBy2R/p4qGVCITL70C1UooOOO3QAXyXFTd6k6BDVb173Z2LIZMPTBj nRyVtwSuU6zAeKdiDZTDf077y4RW7awyYFVlAnxU3pEq6LIsgjeHW+YgNy9hl5RZmqAC ofPLE9xbTFp2xOxWUBXNgbimBGOCztI019UDu0BUc22ssfzDafRMyIROYPfrq9uL4a0h cO0Xcjv3SCTV1c4OlLca3FIWqhGuk1OUUN2oNiT9p2b/IJfT9JKLw7gmHk8PjtGIO6/y 3jLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LLPIf7qXwEodLjL1V+df+mpIrgJgFYuNvN+PgAflmco=; b=A8T8YRu+BdMQBX49D2DB4i7Bj32+tLh7pMN0s1P+0TNJxY4kh96ObxZ38vVAUPbsyh 6Jedfj0BBqssOmPC0a3b+mOXyZCXSrLJN+FaNaEJlj1B0JCaFq6IpLL7QVfHG3HEGEyE OC4reIRElVdrXW+dQ6pAHmp8595Qrhr7UZWv0C04uRoPTwrMs+UEHmdJD8Zg0/jtHOxT +3+YNn9uDEk67SrnRFIFcvqlFZlBRzLygyTStKR/M3QL5jFEd6xH1kiBlLH7LI2Jy5lC SD19AekawovX1ALebWJK2xk7t0QbkzPtFvshP5sy6qoEfLHqsB4MwrCBWr9s8kNl3Dga Dvzw== X-Gm-Message-State: AO0yUKVf9ApFR+T0/HNzJHxhJX+CsZE5Az3IfSLzDlWCoMsnVB5/kM9N c6BsF4hyBAfpW61gAR9AUxwUSpzjRHwL/9K2 X-Google-Smtp-Source: AK7set+w1ILayoUIdcps0XpCic81O37+0LVVSkxBRhm06a2uf1QjK41nGVUSD5VVzDO4J0G2Uv7S5w== X-Received: by 2002:a17:90b:20a:b0:22c:147d:137f with SMTP id fy10-20020a17090b020a00b0022c147d137fmr21146649pjb.17.1675115342052; Mon, 30 Jan 2023 13:49:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 08/36] include/qemu/int128: Use Int128 structure for TCI Date: Mon, 30 Jan 2023 11:48:16 -1000 Message-Id: <20230130214844.1158612-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115385353100003 We are about to allow passing Int128 to/from tcg helper functions, but libffi doesn't support __int128_t, so use the structure. In order for atomic128.h to continue working, we must provide a mechanism to frob between real __int128_t and the structure. Provide a new union, Int128Alias, for this. We cannot modify Int128 itself, as any changed alignment would also break libffi. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/qemu/atomic128.h | 29 +++++++++++++++++++++------ include/qemu/int128.h | 25 +++++++++++++++++++++--- util/int128.c | 42 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+), 9 deletions(-) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index adb9a1a260..d0ba0b9c65 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -44,13 +44,23 @@ #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return qatomic_cmpxchg__nocheck(ptr, cmp, new); + Int128Alias r, c, n; + + c.s =3D cmp; + n.s =3D new; + r.i =3D qatomic_cmpxchg__nocheck((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(CONFIG_CMPXCHG128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return __sync_val_compare_and_swap_16(ptr, cmp, new); + Int128Alias r, c, n; + + c.s =3D cmp; + n.s =3D new; + r.i =3D __sync_val_compare_and_swap_16((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(__aarch64__) @@ -89,12 +99,18 @@ Int128 QEMU_ERROR("unsupported atomic") #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_read(Int128 *ptr) { - return qatomic_read__nocheck(ptr); + Int128Alias r; + + r.i =3D qatomic_read__nocheck((__int128_t *)ptr); + return r.s; } =20 static inline void atomic16_set(Int128 *ptr, Int128 val) { - qatomic_set__nocheck(ptr, val); + Int128Alias v; + + v.s =3D val; + qatomic_set__nocheck((__int128_t *)ptr, v.i); } =20 # define HAVE_ATOMIC128 1 @@ -132,7 +148,8 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) static inline Int128 atomic16_read(Int128 *ptr) { /* Maybe replace 0 with 0, returning the old value. */ - return atomic16_cmpxchg(ptr, 0, 0); + Int128 z =3D int128_make64(0); + return atomic16_cmpxchg(ptr, z, z); } =20 static inline void atomic16_set(Int128 *ptr, Int128 val) @@ -141,7 +158,7 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) do { cmp =3D old; old =3D atomic16_cmpxchg(ptr, cmp, val); - } while (old !=3D cmp); + } while (int128_ne(old, cmp)); } =20 # define HAVE_ATOMIC128 1 diff --git a/include/qemu/int128.h b/include/qemu/int128.h index d2b76ca6ac..f62a46b48c 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -3,7 +3,12 @@ =20 #include "qemu/bswap.h" =20 -#ifdef CONFIG_INT128 +/* + * With TCI, we need to use libffi for interfacing with TCG helpers. + * But libffi does not support __int128_t, and therefore cannot pass + * or return values of this type, force use of the Int128 struct. + */ +#if defined(CONFIG_INT128) && !defined(CONFIG_TCG_INTERPRETER) typedef __int128_t Int128; =20 static inline Int128 int128_make64(uint64_t a) @@ -460,8 +465,7 @@ Int128 int128_divu(Int128, Int128); Int128 int128_remu(Int128, Int128); Int128 int128_divs(Int128, Int128); Int128 int128_rems(Int128, Int128); - -#endif /* CONFIG_INT128 */ +#endif /* CONFIG_INT128 && !CONFIG_TCG_INTERPRETER */ =20 static inline void bswap128s(Int128 *s) { @@ -472,4 +476,19 @@ static inline void bswap128s(Int128 *s) #define INT128_MAX int128_make128(UINT64_MAX, INT64_MAX) #define INT128_MIN int128_make128(0, INT64_MIN) =20 +/* + * When compiler supports a 128-bit type, define a combination of + * a possible structure and the native types. Ease parameter passing + * via use of the transparent union extension. + */ +#ifdef CONFIG_INT128 +typedef union { + Int128 s; + __int128_t i; + __uint128_t u; +} Int128Alias __attribute__((transparent_union)); +#else +typedef Int128 Int128Alias; +#endif /* CONFIG_INT128 */ + #endif /* INT128_H */ diff --git a/util/int128.c b/util/int128.c index ed8f25fef1..df6c6331bd 100644 --- a/util/int128.c +++ b/util/int128.c @@ -144,4 +144,46 @@ Int128 int128_rems(Int128 a, Int128 b) return r; } =20 +#elif defined(CONFIG_TCG_INTERPRETER) + +Int128 int128_divu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.u =3D a.u / b.u; + return r.s; +} + +Int128 int128_remu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.u =3D a.u % b.u; + return r.s; +} + +Int128 int128_divs(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.i =3D a.i / b.i; + return r.s; +} + +Int128 int128_rems(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.i =3D a.i % b.i; + return r.s; +} + #endif --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115370; cv=none; d=zohomail.com; s=zohoarc; b=jYB9/Sn6IOzGJA2ygBSm1fURFeD6fiUIeKCqy0X07jy072V3vC1TIP7WjVkSmHAsuNmyykyprcXPqsJP6GFFEF9sEByxb1afE5pcSd8r+Dtne2hfaZAbToZz3mCH6yRkbrq+VE+F/25EQ9JOnBJciq3T5cFsuRe6duLDRhDiSMA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115370; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=C/L7rpu7pR8QgddFOconCzyTsPMIEKIuZwLXecbYJWA=; b=JheSWltGC9RaHh5yHufxhSdzSBr3ujedlxD8g5j5Y3yR7TQYSxYPvDQbWUR80XYjOefoIy6Ory2VE4I1lEN+iS4xL8nJclP42CR+IinkDG/HdCmahycS2cP0DrqR+/URrUbPpUuloPvLpfjbekzNv8mgoRcWuhr1mFiTjYQQ5fc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115370354797.1136401912726; Mon, 30 Jan 2023 13:49:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1T-0001vq-P9; Mon, 30 Jan 2023 16:49:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1S-0001ux-El for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:06 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1Q-0005cH-RI for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:06 -0500 Received: by mail-pj1-x102e.google.com with SMTP id b10so12406048pjo.1 for ; Mon, 30 Jan 2023 13:49:04 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C/L7rpu7pR8QgddFOconCzyTsPMIEKIuZwLXecbYJWA=; b=j6EtLzuLDO9FfSPxe/kh40iMUp4UPIC3XYJI9YuakAqSiTE3F3Z7s4fjcsnsK9UD0e AYuvEfunP+IV0SF7z9kp542gbj1LKnWNEHC55XMZHCxzSAqBQAFKO/Oe/hj9+5mQvGdN tvYGRO0deVjYS+EgwPJinrIOv1R7H1VDFGezMZXbcaKQhyz0hyXDn+PWXbIXlRMe/K7g S+mQZVE8VJU5T1XkLBsxV/iW/2kZS8apJg7bUL+jocRqCL3aSisGv4qtoVLRvoh+0Tpn JVrWvEYaIjjimOrLL1NRWPBsV/H36C0USu+Usoqf8rd9DwNDFUxnwj+a2NjWKfeYVvgm CwLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C/L7rpu7pR8QgddFOconCzyTsPMIEKIuZwLXecbYJWA=; b=I3UOuxAWzAPbvmmtdmjsPfHvqAhDw5v/TbbmDsSZYW6A1kZWEldNRxSNhJpW+sqydb B9cBw1Uk3xLIReE2wX5k5I7WPaUd1ZpiTnOMKtHfkdfeRdPZJqSR4YSnouz5LNXPB9/E kLFNOSy3Ef1GxYuX9zlEWdIkd3cDrCgZgcm6vDH0D1s9QdwXfHulIS0TZryjKYKYLAyd yCM+wUOgQ7T/yG21LO0Hgo1ZS4bVZcEreROCjq0pBaRVWN74aFrrqLvaF1d8+9urGz7p yfWtUPAc3PfG9/ToE1xzqhWYq2IgbWvFLwTJy4rjxKBdThqRQkG7mAiVxqeINBe1IbKu 3hUg== X-Gm-Message-State: AO0yUKUchfiCC1gpx6OyCo7KosmPd6E0qq35DoJ+Br/29aIfCyuwSphu LAsxFpWFKdSWByaZsaxLkox7Tqb/EOEFJmTE X-Google-Smtp-Source: AK7set8Z+VBNw3Bex1cn13btQqGeCMJn1v0M5C04s1nBSS/soErx8N4hnWWC4pexKfg2tDkZSNIRpQ== X-Received: by 2002:a17:90b:4f43:b0:22c:9591:ce7e with SMTP id pj3-20020a17090b4f4300b0022c9591ce7emr6319868pjb.31.1675115343504; Mon, 30 Jan 2023 13:49:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 09/36] tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Mon, 30 Jan 2023 11:48:17 -1000 Message-Id: <20230130214844.1158612-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115371389100001 Fill in the parameters for the host ABI for Int128. Adjust tcg_target_call_oarg_reg for _WIN64, and tcg_out_call for i386 sysv. Allow TCG_TYPE_V128 stores without AVX enabled. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 10 ++++++++++ tcg/i386/tcg-target.c.inc | 30 +++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 5797a55ea0..d4f2a6f8c2 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -100,6 +100,16 @@ typedef enum { #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#if defined(_WIN64) +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC +#elif TCG_TARGET_REG_BITS =3D=3D 64 +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL +#else +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF +#endif =20 extern bool have_bmi1; extern bool have_popcnt; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 2f0a9521bf..883ced8168 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -115,6 +115,11 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) case TCG_CALL_RET_NORMAL: tcg_debug_assert(slot >=3D 0 && slot <=3D 1); return slot ? TCG_REG_EDX : TCG_REG_EAX; +#ifdef _WIN64 + case TCG_CALL_RET_BY_VEC: + tcg_debug_assert(slot =3D=3D 0); + return TCG_REG_XMM0; +#endif default: g_assert_not_reached(); } @@ -1188,9 +1193,16 @@ static void tcg_out_st(TCGContext *s, TCGType type, = TCGReg arg, * The gvec infrastructure is asserts that v128 vector loads * and stores use a 16-byte aligned offset. Validate that the * final pointer is aligned by using an insn that will SIGSEGV. + * + * This specific instance is also used by TCG_CALL_RET_BY_VEC, + * for _WIN64, which must have SSE2 but may not have AVX. */ tcg_debug_assert(arg >=3D 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); + if (have_avx1) { + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg= 2); + } else { + tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); + } break; case TCG_TYPE_V256: /* @@ -1677,6 +1689,22 @@ static void tcg_out_call(TCGContext *s, const tcg_in= sn_unit *dest, const TCGHelperInfo *info) { tcg_out_branch(s, 1, dest); + +#ifndef _WIN32 + if (TCG_TARGET_REG_BITS =3D=3D 32 && info->out_kind =3D=3D TCG_CALL_RE= T_BY_REF) { + /* + * The sysv i386 abi for struct return places a reference as the + * first argument of the stack, and pops that argument with the + * return statement. Since we want to retain the aligned stack + * pointer for the callee, we do not want to actually push that + * argument before the call but rely on the normal store to the + * stack slot. But we do need to compensate for the pop in order + * to reset our correct stack pointer value. + * Pushing a garbage value back onto the stack is quickest. + */ + tcg_out_push(s, TCG_REG_EAX); + } +#endif } =20 static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115474; cv=none; d=zohomail.com; s=zohoarc; b=UHcuFyjgcZM869ZQrMDu22dRb9WqFFH6uifBhq15Rche958HFL1Y0O6tW53z8SpzFZZelk3OgErfW5pxBJkbGo5OIMOPThESZf1QjkmT5nV/DwcbmMsC5jMHMAq5R0xAC1b45wN6E9CT+J+vRrM2IGzeOpz0wMbvCKlYq3x+oew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115474; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8hloccov+e7J/dBzNCn3XTem8GBlJxxzB07CqfLWqlQ=; b=QQz7kZD5KEBrCcoOrdQUw5Ot3r7n9msoxJ4r1xjSt5u1jUZuND+Rz1+L7U51RZbh+DXRehK2lIJLM/bN3MVZPnNjhusKvxXx/KwfRwL+zcy/3bn1Dqsm/YhOUSduU15+FgVuw7F8bkljVvS1vClESQV3aBbeFOCl4MEPLiRFvkk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115474660276.93523319977226; Mon, 30 Jan 2023 13:51:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1V-0001wT-Bs; Mon, 30 Jan 2023 16:49:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1U-0001w3-5O for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:08 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1S-0005cc-Hv for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:07 -0500 Received: by mail-pj1-x1031.google.com with SMTP id rm7-20020a17090b3ec700b0022c05558d22so12467436pjb.5 for ; Mon, 30 Jan 2023 13:49:06 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8hloccov+e7J/dBzNCn3XTem8GBlJxxzB07CqfLWqlQ=; b=gxbiZ5gy5RaJOwJ+LKygsjJZF8Ra940PSMHSapHMNcoW8eZrUbboZKwvRWnVtkCHNV q2x4Y+oH3wJi5j8SEMsNYto7HP/V1paLeTOsQQtQrwX7G8RHqzLu+Wp0qjzDNdJGsUsU qpe1Tw7Ru9lkDuuigWOxQtjRM3v1PvqHC1x2HsOKhiGKEOO4f9GB+O1jje11kUOZARwS vkjffd11paFqJpyrcHV/4x2bnVQkzHLyQYUGbIkzAzd0J+5APmfFfH5miE0CpeWTIle2 LKPh2b631CyCa0pibLsyN98UyjKgMrAJLKDdCSjqbjBIZXvN5OldtgV/84sLfv0/GMaY nEOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8hloccov+e7J/dBzNCn3XTem8GBlJxxzB07CqfLWqlQ=; b=66ktCfrWGHHzc1Mvph6dOqLwjT8DnPfcbQcASUa3OVeSFXIv47FSIQf4/PEPcOF1cu yXdchWLId9M3ECdo9DFyEFSix9bquHIVF+djwuXxpFM6qg+Dro8g3wJY1FECkxEAm8P+ NT4wsYOEqbAEUBD501MvYk4JKVF8VH8shi/600xPJ3chuISSIjna3ZJ7NboMlEBsVsMm MsGz+64XFviGADN47iiERsiSd3DXzPm2+riYsDYKkVAjZ+2J3oiO58Vxca7ctjd6J05x Gt1S7zN4E/SDyppHF4GexeIoqTClJrLuNVQJADBv1peo52jioY4qe8vew5s+Pu5hB8eF 6aBQ== X-Gm-Message-State: AO0yUKVsnApkWt78+dS4Yg4JY54h4zciAo8t1dIUdWh/3drSBMgLgwNe hqAyaiFbSUwTenZSN+rwCx0Wbk1WtRoNanI3 X-Google-Smtp-Source: AK7set9oAhkYWKzqQMAQhANNS9nm1KNKgpAXfPN+Zi5/Xbi7+g1ZDNK3DIP2U1eM9m3osOz0/U4Atg== X-Received: by 2002:a17:90a:1a15:b0:22c:912:b80d with SMTP id 21-20020a17090a1a1500b0022c0912b80dmr22987327pjk.33.1675115345096; Mon, 30 Jan 2023 13:49:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 10/36] tcg/tci: Fix big-endian return register ordering Date: Mon, 30 Jan 2023 11:48:18 -1000 Message-Id: <20230130214844.1158612-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115476661100003 We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We were forcing R0 to contain the low part for calls. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 05a24163d3..eeccdde8bc 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -520,27 +520,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, ffi_call(pptr[1], pptr[0], stack, call_slots); } =20 - /* Any result winds up "left-aligned" in the stack[0] slot. */ switch (len) { case 0: /* void */ break; case 1: /* uint32_t */ /* + * The result winds up "left-aligned" in the stack[0] slot. * Note that libffi has an odd special case in that it will * always widen an integral result to ffi_arg. */ - if (sizeof(ffi_arg) =3D=3D 4) { - regs[TCG_REG_R0] =3D *(uint32_t *)stack; - break; - } - /* fall through */ - case 2: /* uint64_t */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]= ); + if (sizeof(ffi_arg) =3D=3D 8) { + regs[TCG_REG_R0] =3D (uint32_t)stack[0]; } else { - regs[TCG_REG_R0] =3D stack[0]; + regs[TCG_REG_R0] =3D *(uint32_t *)stack; } break; + case 2: /* uint64_t */ + /* + * For TCG_TARGET_REG_BITS =3D=3D 32, the register pair + * must stay in host memory order. + */ + memcpy(®s[TCG_REG_R0], stack, 8); + break; default: g_assert_not_reached(); } --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115400; cv=none; d=zohomail.com; s=zohoarc; b=Z1iZjlAHD8FbjJEOm0U+MK0hM6Nj6E/oHqZjLh/1DoS+rHrZEfFhTnRUKOFc0F54ZwptLHy88XKmzn3X+rF8xlDH7c6fmdOjtFSe+fAz43OWYPLoiakMx4Rjtb8vqjHn2e+jANxEa1amBkf6IYiFTI0dyhO+v/V5Ys1WH7BhN8c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115400; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d/VaqdvyZanWttEJ3248OXSPTZwbXJrxyYFWhISw3Lc=; b=loL8tCTbCpjbxd9C5C05n3DKdF9Jd8kTfm1bo3K888OAYUhv9bSgG3+FNXFV2YPwkWXRiIDyGH0mwDN8fOua8PXBEGIpz2hs2/AV6YbR8w2aK4Wg9O6ISOY9H9g8p73FzhN86p508nPC/buqoq32K8ZeJSO6dx7JXNPlbGnyLgE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115400617414.37022733787; Mon, 30 Jan 2023 13:50:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1W-0001wd-Oe; Mon, 30 Jan 2023 16:49:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1V-0001wS-90 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:09 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1T-0005ZD-FB for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:09 -0500 Received: by mail-pj1-x1032.google.com with SMTP id on9-20020a17090b1d0900b002300a96b358so1096623pjb.1 for ; Mon, 30 Jan 2023 13:49:07 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d/VaqdvyZanWttEJ3248OXSPTZwbXJrxyYFWhISw3Lc=; b=Pnpu+NeYSfflk2/uS35/5KA7hdSiTsPug2q2gR+3oLHBL1fq+HbGedzOsBe2lx3I7R 74laWPid4oGjAjt1q7774F3CS7wSOMchjN4itDJIfnmqSt70xm9a5aa3rGaWr3c+Hi4S oEZY4iNggFnJSlmcIwIzvU36MjtBpmdx+kbPYjcx4pUGsaQRxaMYN1GYFqBLtl1NaYfG hT3BUnTDn8q1Pffmft0qRJJ4LqF/YF9c5xM4Utq5OC6CfxMzUjkE4z+m7PZ7vPbyXM7Q pfsjRaNBwVQTIFEDPETtkRvBMh4p8DuIGv6dk3JzN/ZZ2iBGx67JlkzTY+PBTY2jykdI WYhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d/VaqdvyZanWttEJ3248OXSPTZwbXJrxyYFWhISw3Lc=; b=hGWukw80xoyhnOVECMhP3Mzo3EFmk0miaXGKswuzDshfIzadJJ+Olx/apdZZ/Q/Kqu 1a+6XpfkC6ZNvK5sanPOe8p2DjFDMHwEqr1ZWa3Izy2bRJP4pfSW3mujsrnDLBqnYoNT qhlCl52ykLGDMjzMl9ffkPwnm/DwC/sts5U/oGf7xmdyULBBtx3RbleP465DCy+EjIgs VOkcXT9x0ay12MkhpE+EWTjAhrUhY4AMsPfpZIZZfP/5IQM0V1mvQe5YgaIvHHYgTVeU TkwamqhH0BgoA4/1Jbs8hySuR6no4pTEDYK4sLEhFEqMyR10zpSx2MGFBymIB1zZPMNV 9Qdw== X-Gm-Message-State: AFqh2krhL0MBJoONEM6yq//a/9JFv3N2Osf75osKfYHrqC5N7adaVnpa 5NsNxMtlREFZQea8kYfy98Lu0a2On4dnePIp X-Google-Smtp-Source: AMrXdXv6CKX4+Akk/Rj5GjLs3h+rdAKyCLQSfOLsD5b/t4jlj50i5uevKRpbCxjxgDwQqqsZbWxqxQ== X-Received: by 2002:a17:90a:b798:b0:229:d641:9ef2 with SMTP id m24-20020a17090ab79800b00229d6419ef2mr45754474pjr.40.1675115346647; Mon, 30 Jan 2023 13:49:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 11/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Mon, 30 Jan 2023 11:48:19 -1000 Message-Id: <20230130214844.1158612-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115401469100001 Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value length. Call parameters are no longer all the same size, so we cannot reuse the same call_slots array for every function. Compute it each time now, but only fill in slots required for the call we're about to make. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 3 +++ tcg/tcg.c | 19 +++++++++++++++++ tcg/tci.c | 44 ++++++++++++++++++++-------------------- tcg/tci/tcg-target.c.inc | 10 ++++----- 4 files changed, 49 insertions(+), 27 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1414ab4d5b..7140a76a73 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -160,10 +160,13 @@ typedef enum { #if TCG_TARGET_REG_BITS =3D=3D 32 # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 #define HAVE_TCG_QEMU_TB_EXEC #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg.c b/tcg/tcg.c index edc6185bf4..5792d72e08 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -570,6 +570,22 @@ static GHashTable *helper_table; #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { + /* + * libffi does not support __int128_t, so we have forced Int128 + * to use the structure definition instead of the builtin type. + */ + static ffi_type *ffi_type_i128_elements[3] =3D { + &ffi_type_uint64, + &ffi_type_uint64, + NULL + }; + static ffi_type ffi_type_i128 =3D { + .size =3D 16, + .alignment =3D __alignof__(Int128), + .type =3D FFI_TYPE_STRUCT, + .elements =3D ffi_type_i128_elements, + }; + switch (argmask) { case dh_typecode_void: return &ffi_type_void; @@ -583,6 +599,8 @@ static ffi_type *typecode_to_ffi(int argmask) return &ffi_type_sint64; case dh_typecode_ptr: return &ffi_type_pointer; + case dh_typecode_i128: + return &ffi_type_i128; } g_assert_not_reached(); } @@ -613,6 +631,7 @@ static void init_ffi_layouts(void) /* Ignoring the return type, find the last non-zero field. */ nargs =3D 32 - clz32(typemask >> 3); nargs =3D DIV_ROUND_UP(nargs, 3); + assert(nargs <=3D MAX_CALL_IARGS); =20 ca =3D g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); ca->cif.rtype =3D typecode_to_ffi(typemask & 7); diff --git a/tcg/tci.c b/tcg/tci.c index eeccdde8bc..022fe9d0f8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -470,12 +470,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; - void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; - /* Other call_slots entries initialized at first use (see below). */ - call_slots[0] =3D NULL; tci_assert(tb_ptr); =20 for (;;) { @@ -498,26 +495,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - /* - * Set up the ffi_avalue array once, delayed until now - * because many TB's do not make any calls. In tcg_gen_callN, - * we arranged for every real argument to be "left-aligned" - * in each 64-bit slot. - */ - if (unlikely(call_slots[0] =3D=3D NULL)) { - for (int i =3D 0; i < ARRAY_SIZE(call_slots); ++i) { - call_slots[i] =3D &stack[i]; - } - } - - tci_args_nl(insn, tb_ptr, &len, &ptr); - - /* Helper functions may need to access the "return address" */ - tci_tb_ptr =3D (uintptr_t)tb_ptr; - { - void **pptr =3D ptr; - ffi_call(pptr[1], pptr[0], stack, call_slots); + void *call_slots[MAX_CALL_IARGS]; + ffi_cif *cif; + void *func; + unsigned i, s, n; + + tci_args_nl(insn, tb_ptr, &len, &ptr); + func =3D ((void **)ptr)[0]; + cif =3D ((void **)ptr)[1]; + + n =3D cif->nargs; + for (i =3D s =3D 0; i < n; ++i) { + ffi_type *t =3D cif->arg_types[i]; + call_slots[i] =3D &stack[s]; + s +=3D DIV_ROUND_UP(t->size, 8); + } + + /* Helper functions may need to access the "return address= " */ + tci_tb_ptr =3D (uintptr_t)tb_ptr; + ffi_call(cif, func, stack, call_slots); } =20 switch (len) { @@ -542,6 +539,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, */ memcpy(®s[TCG_REG_R0], stack, 8); break; + case 3: /* Int128 */ + memcpy(®s[TCG_REG_R0], stack, 16); + break; default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e3b0ff303f..c1d34d7bd1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -203,7 +203,7 @@ static const int tcg_target_call_iarg_regs[] =3D { }; static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) { tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); - tcg_debug_assert(slot >=3D 0 && slot < 64 / TCG_TARGET_REG_BITS); + tcg_debug_assert(slot >=3D 0 && slot < 128 / TCG_TARGET_REG_BITS); return TCG_REG_R0 + slot; } =20 @@ -573,11 +573,11 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *func, =20 if (cif->rtype =3D=3D &ffi_type_void) { which =3D 0; - } else if (cif->rtype->size =3D=3D 4) { - which =3D 1; } else { - tcg_debug_assert(cif->rtype->size =3D=3D 8); - which =3D 2; + tcg_debug_assert(cif->rtype->size =3D=3D 4 || + cif->rtype->size =3D=3D 8 || + cif->rtype->size =3D=3D 16); + which =3D ctz32(cif->rtype->size) - 1; } new_pool_l2(s, 20, s->code_ptr, 0, (uintptr_t)func, (uintptr_t)cif); insn =3D deposit32(insn, 0, 8, INDEX_op_call); --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115481; cv=none; d=zohomail.com; s=zohoarc; b=kGyv3e1UC1GKZ0lIfFZBsWVAj6ZgnwKa1h3Xx32Z1r/sYc96L9hrLXV4cqqs8LHYVa2iC0ZnrOCjjNQfg7sbiA+7E/nZkhoqVRJF9caoCbPUqDNcBt1Xs0rTWjjrysyGG2/KhSzzEsrSjJd10GN0t3A/orf57yXlDLKNLyc8/BY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115481; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S6SvEHx78kS2KADmPPjCHAzl8COWQD557fy1pkfTl6o=; b=aVjN2+tWxvu5GxrUhr1tDOlOH4m6nb+adg8DIwrpYAXbws4JVB0xmg6g1mlv11Y3YvDnveb0ZgDH8zzpW0mALkYEYM4hKoF5Z5YjONAwp66LUbSJzCqZzxXZKHnRB6/5iopwXuuBfVJh4epxIz62fEeGQNaN4T8umY9XtnDyG4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115481913737.0389940502223; Mon, 30 Jan 2023 13:51:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1Y-0001xD-PY; Mon, 30 Jan 2023 16:49:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1X-0001wv-JV for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:11 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1V-0005d3-Mc for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:11 -0500 Received: by mail-pl1-x636.google.com with SMTP id h9so4498746plf.9 for ; Mon, 30 Jan 2023 13:49:09 -0800 (PST) Received: from stoup.. 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Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 3 +++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tcg.c | 6 +++--- tcg/ppc/tcg-target.c.inc | 3 +++ 9 files changed, 21 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 8d244292aa..c0b0f614ba 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -54,6 +54,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 91b8954804..def2a189e6 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -91,6 +91,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF =20 /* optional instructions */ #define TCG_TARGET_HAS_ext8s_i32 1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 8b151e7f6f..17b8193aa5 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -92,6 +92,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 7bc8e15293..68b11e4d48 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -89,6 +89,8 @@ typedef enum { # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >=3D 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 1337bc1f1e..0deb33701f 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -85,9 +85,12 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS =3D=3D 32 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index e597e47e60..a05b473117 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -169,6 +169,8 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_CALL_STACK_OFFSET 160 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 1d6a5c8b07..ffe22b1d21 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -73,6 +73,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 #if defined(__VIS__) && __VIS__ >=3D 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 5792d72e08..0a4ad99a12 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -765,8 +765,8 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i128: info->nr_out =3D 128 / TCG_TARGET_REG_BITS; - info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ - switch (/* TODO */ TCG_CALL_RET_NORMAL) { + info->out_kind =3D TCG_TARGET_CALL_RET_I128; + switch (TCG_TARGET_CALL_RET_I128) { case TCG_CALL_RET_NORMAL: /* Query the last register now to trigger any assert early. */ tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); @@ -854,7 +854,7 @@ static void init_call_layout(TCGHelperInfo *info) break; =20 case TCG_TYPE_I128: - switch (/* TODO */ TCG_CALL_ARG_NORMAL) { + switch (TCG_TARGET_CALL_ARG_I128) { case TCG_CALL_ARG_EVEN: layout_arg_even(&cum); /* fall through */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index f3fec14118..afadf9a1e3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -54,6 +54,9 @@ #else # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif +/* Note sysv arg alignment applies only to 2-word types, not more. */ +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* For some memory operations, we need a scratch that isn't R0. For the A= IX calling convention, we can re-use the TOC register since we'll be reloa= ding --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115531; cv=none; d=zohomail.com; s=zohoarc; b=JY8qK88RhYO7Bjz/VZeYLu4Ah/L1dYglHvXKpaSP2vxgVZsPI2zb8bn33OjsG7jKvPPH1iiMZXO/eVVdmLFL0ZMNQUXQwH9a3OvZCDrqYFtf+/tVlMqBLY9+RwIjj3H42a7R/0zAS2Cu9/16xkSlzSRa8s02WmdDiHuWS95pq7Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115531; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CJH1k0t5A6W0zvw0UVl/f2Kw3cu3hBI6bpM0JqIs/cA=; b=eqec6UChz7Wcxxq9BXTXEPdEkxWjUdBSnNLUJOnYIaDKctHGkANmjLodC/JgaqTtxXN82mD5M06q+s6wrrCdABgvax+LWDiIr48nfmGc7M+D0iKHvwJT6QjU4NXytmsf6O523mWnPqo+eihvnPy/JdolLVOi0EEYxON6H42o7nY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115531073515.737782580568; Mon, 30 Jan 2023 13:52:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1a-0001xf-Jt; Mon, 30 Jan 2023 16:49:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1Y-0001xF-Rm for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:12 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1X-0005dH-6D for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:12 -0500 Received: by mail-pl1-x62e.google.com with SMTP id k13so13158152plg.0 for ; Mon, 30 Jan 2023 13:49:10 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CJH1k0t5A6W0zvw0UVl/f2Kw3cu3hBI6bpM0JqIs/cA=; b=dQlgfuPxHJo0Vz0jZwmpyXTN+I0LjNLda+hdl4zNwIkj4YdEMTjy01QOGt5MqrryC9 s67tZOeijGeCRm94R75TwoPCXGG7phj2GbYNOtMWuAs4+3/aA+2nb6IWacbVlJVo4nyo 2QM5+/6thoEvyo1eyswwtSvSjnACuQJCjWrk5+ba/z7ewNyE+oXpuy+1L5X818QuPred aofDtFEubs49jr251Zjwe18HR3JHUAjlah/ogoKafmYKRSTtpAmwBoAHMV9WqegouYTF NJpLBZT+oUedV/uJla3zd7CKaj3YvBKFS6WItSqhb1SC9stdZQt2pldWeRUMiViT8fAJ vybw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CJH1k0t5A6W0zvw0UVl/f2Kw3cu3hBI6bpM0JqIs/cA=; b=uELo6hk/I7DmTVrR8+n8uJ0Xqoe55MR1nqQ8Tf3VVM52q4k3HhiB7vhl/mcqgX+aa8 teTY8A8tHd6Vi+NG9KwFZYL8fTktRZyEShKx79kjGntyGSGHh2+8so518c+/op6x4suH tdz/KIW44bhOW6L8T9ncGZKc2fVvOGIYu31x0r/ECFU/iuvMKOOas1At4gvtFD4hPDOl GPwA/+sMEzndsZAtfVywZpJkdk4HTDQq9Zt+KvoiCdaVoaDI/4osfHu5sKBDy2OSYxMv SXT+99pX5xO78o5Oi7bRVictq9DpFUESPfAQCjUsnN63Puq1ZhkfEKIvJwAYY4zzPZEt GCrA== X-Gm-Message-State: AO0yUKUbIpU0A590xxvEZH5tuYlhOZzshigzZTwR0puq1whRD6A5cpb7 5kcIP/mfHy5T97DUMGtAPkz0856vbk7OWHjQ X-Google-Smtp-Source: AK7set+2D0oxyWaJJ/zHWrfX2JUGsOkuJ2ber5/I/1zt6+TrgBj+glRYTjpzVbT1zkMgk2vepHM5fg== X-Received: by 2002:a17:90a:19c8:b0:228:a39c:8d11 with SMTP id 8-20020a17090a19c800b00228a39c8d11mr11944527pjj.1.1675115349838; Mon, 30 Jan 2023 13:49:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 13/36] tcg: Add temp allocation for TCGv_i128 Date: Mon, 30 Jan 2023 11:48:21 -1000 Message-Id: <20230130214844.1158612-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115533171100005 This enables allocation of i128. The type is not yet usable, as we have not yet added data movement ops. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/tcg/tcg.h | 32 +++++++++++++++++++++++++ tcg/tcg.c | 60 +++++++++++++++++++++++++++++++++-------------- 2 files changed, 74 insertions(+), 18 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 8b7e61e7a5..7a8e4bbdd7 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -685,6 +685,11 @@ static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) return tcgv_i32_temp((TCGv_i32)v); } =20 +static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) +{ + return tcgv_i32_temp((TCGv_i32)v); +} + static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) { return tcgv_i32_temp((TCGv_i32)v); @@ -705,6 +710,11 @@ static inline TCGArg tcgv_i64_arg(TCGv_i64 v) return temp_arg(tcgv_i64_temp(v)); } =20 +static inline TCGArg tcgv_i128_arg(TCGv_i128 v) +{ + return temp_arg(tcgv_i128_temp(v)); +} + static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) { return temp_arg(tcgv_ptr_temp(v)); @@ -726,6 +736,11 @@ static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) return (TCGv_i64)temp_tcgv_i32(t); } =20 +static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) +{ + return (TCGv_i128)temp_tcgv_i32(t); +} + static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) { return (TCGv_ptr)temp_tcgv_i32(t); @@ -851,6 +866,11 @@ static inline void tcg_temp_free_i64(TCGv_i64 arg) tcg_temp_free_internal(tcgv_i64_temp(arg)); } =20 +static inline void tcg_temp_free_i128(TCGv_i128 arg) +{ + tcg_temp_free_internal(tcgv_i128_temp(arg)); +} + static inline void tcg_temp_free_ptr(TCGv_ptr arg) { tcg_temp_free_internal(tcgv_ptr_temp(arg)); @@ -899,6 +919,18 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return temp_tcgv_i64(t); } =20 +static inline TCGv_i128 tcg_temp_new_i128(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, false); + return temp_tcgv_i128(t); +} + +static inline TCGv_i128 tcg_temp_local_new_i128(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, true); + return temp_tcgv_i128(t); +} + static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offse= t, const char *name) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 0a4ad99a12..fee96b3d9c 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1273,26 +1273,45 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool t= emp_local) tcg_debug_assert(ts->base_type =3D=3D type); tcg_debug_assert(ts->kind =3D=3D kind); } else { + int i, n; + + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + n =3D 1; + break; + case TCG_TYPE_I64: + n =3D 64 / TCG_TARGET_REG_BITS; + break; + case TCG_TYPE_I128: + n =3D 128 / TCG_TARGET_REG_BITS; + break; + default: + g_assert_not_reached(); + } + ts =3D tcg_temp_alloc(s); - if (TCG_TARGET_REG_BITS =3D=3D 32 && type =3D=3D TCG_TYPE_I64) { - TCGTemp *ts2 =3D tcg_temp_alloc(s); + ts->base_type =3D type; + ts->temp_allocated =3D 1; + ts->kind =3D kind; =20 - ts->base_type =3D type; - ts->type =3D TCG_TYPE_I32; - ts->temp_allocated =3D 1; - ts->kind =3D kind; - - tcg_debug_assert(ts2 =3D=3D ts + 1); - ts2->base_type =3D TCG_TYPE_I64; - ts2->type =3D TCG_TYPE_I32; - ts2->temp_allocated =3D 1; - ts2->temp_subindex =3D 1; - ts2->kind =3D kind; - } else { - ts->base_type =3D type; + if (n =3D=3D 1) { ts->type =3D type; - ts->temp_allocated =3D 1; - ts->kind =3D kind; + } else { + ts->type =3D TCG_TYPE_REG; + + for (i =3D 1; i < n; ++i) { + TCGTemp *ts2 =3D tcg_temp_alloc(s); + + tcg_debug_assert(ts2 =3D=3D ts + i); + ts2->base_type =3D type; + ts2->type =3D TCG_TYPE_REG; + ts2->temp_allocated =3D 1; + ts2->temp_subindex =3D i; + ts2->kind =3D kind; + } } } =20 @@ -3381,9 +3400,14 @@ static void temp_allocate_frame(TCGContext *s, TCGTe= mp *ts) case TCG_TYPE_V64: align =3D 8; break; + case TCG_TYPE_I128: case TCG_TYPE_V128: case TCG_TYPE_V256: - /* Note that we do not require aligned storage for V256. */ + /* + * Note that we do not require aligned storage for V256, + * and that we provide alignment for I128 to match V128, + * even if that's above what the host ABI requires. + */ align =3D 16; break; default: --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+teQY6hM374j7zI9pNklyKGVfwDlTPag7AVypMwhnZU=; b=y7NyaXLE+G7OQa/WDOnjFUEL1HnvpbwoygfX0uFhQ4B/l8eFabDxqOocdEnOTMQCMQ v5DTvOnPFmAq9ofXqo/1Ooc8btgckD+YceAgOjEA+Se6xRUDw5gJ3bjal8BA6dQO4RiO /Edf5kliaylfE8+XVgKIS40kFmq1jpAB4vBUWx25y8sCytUIkfQVCyFKWtsEYY1KRJKU uT2IR48DBb/a9qAb+QNhbQaMoIaIhXTf6EkJ1EccG1qifT+r76VADyGedfEsB0gMM/t9 IGThWzOHkyQkc2/hNy9/dn6uUtguxmU+N8Zt2SEGk31BQ3MRK2yjon+i8rNaoPBewddm ZPBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+teQY6hM374j7zI9pNklyKGVfwDlTPag7AVypMwhnZU=; b=SfvJNggj+4At/wM0flkHfUKi/BNh7q2/TLe2QzQlYFdgC9KuMfd5twx4QtfqmMXkpJ f9UPGoh0x5uoBlfsTgiaaJqU0mWqUHTdVwXzfdB6dD98yg8gyss9dteKWMRnYpIjqaeF fiZCd6YGojcSMgziZfn/TuBzi8v6MAje6Rom4nwCx71yL5wi2wZg+e3KlgVZKInphHR0 RfwBbi7FMLJi6vkw46BoZ7L/U0Ncpun77j+91JpqKhKNMsaKIhqXWArNOls8ZWd81+iH 8xs7xexFcmzxc3vktSBiDHn058yFNsh6xLl+x5/o7iLNSLpJEdApTZ8ESth5YK0LJZ7D fLqg== X-Gm-Message-State: AO0yUKXYKU/JEPl1IkbtgqyhFVXIqsY3ki9jiBV7Ijr2u2Rid/QaxO2H 4mYIN9zDmEvVQWQakwRoxnsjXXjh8VvbP+WI X-Google-Smtp-Source: AK7set8a7XP4MiUae1XiT8I+J6+T8XFD90PjfNzcERnJz+CaimKMb7h6oVbuMnJ8RAkvoLe/bM0aeQ== X-Received: by 2002:a17:90a:1984:b0:229:f4ba:e3e4 with SMTP id 4-20020a17090a198400b00229f4bae3e4mr11254270pji.13.1675115351351; Mon, 30 Jan 2023 13:49:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 14/36] tcg: Add basic data movement for TCGv_i128 Date: Mon, 30 Jan 2023 11:48:22 -1000 Message-Id: <20230130214844.1158612-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115565361100006 Add code generation functions for data movement between TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract). Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 ++++ tcg/tcg-internal.h | 13 +++++++++++++ tcg/tcg-op.c | 20 ++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 79b1cf786f..c4276767d1 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -712,6 +712,10 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); =20 +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); + static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i6= 4 hi) { tcg_gen_deposit_i64(ret, lo, hi, 32, 32); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 33f1d8b411..e542a4e9b7 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -117,4 +117,17 @@ extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit = code path is reachable"); extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reacha= ble"); #endif =20 +static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) +{ + /* For 32-bit, offset by 2, which may then have TCGV_{LOW,HIGH} applie= d. */ + int o =3D HOST_BIG_ENDIAN ? 64 / TCG_TARGET_REG_BITS : 0; + return temp_tcgv_i64(tcgv_i128_temp(t) + o); +} + +static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) +{ + int o =3D HOST_BIG_ENDIAN ? 0 : 64 / TCG_TARGET_REG_BITS; + return temp_tcgv_i64(tcgv_i128_temp(t) + o); +} + #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 326a9180ef..cb83d2375d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2747,6 +2747,26 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TC= Gv_i64 arg) tcg_gen_shri_i64(hi, arg, 32); } =20 +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg) +{ + tcg_gen_mov_i64(lo, TCGV128_LOW(arg)); + tcg_gen_mov_i64(hi, TCGV128_HIGH(arg)); +} + +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi) +{ + tcg_gen_mov_i64(TCGV128_LOW(ret), lo); + tcg_gen_mov_i64(TCGV128_HIGH(ret), hi); +} + +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src) +{ + if (dst !=3D src) { + tcg_gen_mov_i64(TCGV128_LOW(dst), TCGV128_LOW(src)); + tcg_gen_mov_i64(TCGV128_HIGH(dst), TCGV128_HIGH(src)); + } +} + /* QEMU specific operations. */ =20 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115372; cv=none; d=zohomail.com; s=zohoarc; b=Wz7JrMqvfFET+zufFd4iZYP/p7UDFA5aXWnMpGVvMVOlll1CkVLGSiA2H6GR9UKwWC98f1KDPIRm+bBQ6Ekr+oSyHCujZa98aRVEGKit7RjwS6/liTo2MHETvmCqr8XOUOO4dUKsoiVG36Wf51XnThqDcQwVvbugQkaiwkLxcyc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115372; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kn2QKpGVCxbEOA7DjmMQr+70sBzJpA0LnU+n2IBTsJE=; b=VJ/0sqpcJAq30HYT4tqy5C8jS9Rs5K5Mq/eLObF/rDKgcw/EZf2nyxnOzDbj1gVMaSKRcKZZsyT5y1PYqsLq2Pxl/9de15l87DVJSnGfCybnNnVLtXiZwE6H10Q5mVXQlDwAN09DsndDfUEbFIBwUocaD86FWE054AQmOOtjM74= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115372395358.5371678725579; Mon, 30 Jan 2023 13:49:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1d-0001yk-VI; Mon, 30 Jan 2023 16:49:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1c-0001y2-Lk for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:16 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1a-0005df-Bq for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:16 -0500 Received: by mail-pj1-x1029.google.com with SMTP id nn18-20020a17090b38d200b0022bfb584987so12502884pjb.2 for ; Mon, 30 Jan 2023 13:49:13 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kn2QKpGVCxbEOA7DjmMQr+70sBzJpA0LnU+n2IBTsJE=; b=YWmAxH2K0A9Ts6FRQ809a9d130sZ+eDznUIxoLBsn/WChaxB9hCdpjPNZk2S7cGxvV dyOmfXRVrOSDGvotzQL3w6jZMZmoN3LfbUNErHHk3UFQy2JrnGQDSH797BnnYE7+1ps6 DmnT/m8ps6rLnlYFg90uGNp9Q7/A0dnZfupFDP3jZuHC3PdRZ9aGXCFJuCh9c1/9/4Qe FNI2c5YCW2jhLsgNteBkLiqjLUNcoCT1wOguK31BY53moTzgIY1N50Q23KFQbbH7V1kZ LJBoEGqHiBGXoK0tFy7VTN4j1jyCPLYhhZOcduxRxHWPn2pGH03IqJzEwxWu4fXFEKgI 4Cfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kn2QKpGVCxbEOA7DjmMQr+70sBzJpA0LnU+n2IBTsJE=; b=fYBFkM7oh12Mu5cXXeHVl9LGxU5le0FdPanpuQy9xKNvxcNlETymgzo6SRTVrG8ZJB ME+Gr4g/xwAk4t2ocFSCuHJmt8VkebD29H704h8dFRP+cGyZnOyt1fem/N/R2ojYGcP3 g4fHzNYPFlWdhmGOqdwDH3xx092c4ClWVxtuD+30UnTbwQ1c0pLkM7dffOC+zrArLOAX su2Rfp4jfOk7P6ojXG6L7na5J7A/Zusm9GFHH7y/uXl9aT7SbQBf532/bJKw/5lun3dw Ar1CqyXkShrQoNcBSUh2Tia0sfGTekOT3pbCAWi0s5J3BD61vo4bQRrSRmk81NyN3fSd p8wA== X-Gm-Message-State: AO0yUKVKHat7WqPndXRRSzxiKsrVHddfnw6STNk0bPDI3KjDCOl5QOeh zelYDVWlDsFvE+/7Ua0jHUpi65mp25+Yzr1t X-Google-Smtp-Source: AK7set/qyQufAnl/yY8mKKm7Hsxsbt/HukYd5Jad+dPsyhMpqyc3PuIOurHBwg7OF7tqfc6AK/SQrQ== X-Received: by 2002:a17:90a:1a0b:b0:22c:816f:cec0 with SMTP id 11-20020a17090a1a0b00b0022c816fcec0mr8385824pjk.21.1675115352810; Mon, 30 Jan 2023 13:49:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 15/36] tcg: Add guest load/store primitives for TCGv_i128 Date: Mon, 30 Jan 2023 11:48:23 -1000 Message-Id: <20230130214844.1158612-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115373274100009 Content-Type: text/plain; charset="utf-8" These are not yet considering atomicity of the 16-byte value; this is a direct replacement for the current target code which uses a pair of 8-byte operations. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/exec/cpu_ldst.h | 10 +++ include/tcg/tcg-op.h | 2 + accel/tcg/cputlb.c | 112 +++++++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 66 ++++++++++++++++++++ tcg/tcg-op.c | 134 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 324 insertions(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d0c7c0d5fe..09b55cc0ee 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -220,6 +220,11 @@ uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra); =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); + void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, MemOpIdx oi, uintptr_t ra); void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, @@ -235,6 +240,11 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, ui= nt32_t val, void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, MemOpIdx oi, uintptr_t ra); =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); + uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index c4276767d1..e5f5b63c37 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -845,6 +845,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp); =20 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4e040a1cb9..e3604ad313 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2187,6 +2187,64 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr a= ddr, return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu); } =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + uint64_t h, l; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_BE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + h =3D helper_be_ldq_mmu(env, addr, new_oi, ra); + l =3D helper_be_ldq_mmu(env, addr + 8, new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return int128_make128(l, h); +} + +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + uint64_t h, l; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_LE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + l =3D helper_le_ldq_mmu(env, addr, new_oi, ra); + h =3D helper_le_ldq_mmu(env, addr + 8, new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return int128_make128(l, h); +} + /* * Store Helpers */ @@ -2541,6 +2599,60 @@ void cpu_stq_le_mmu(CPUArchState *env, target_ulong = addr, uint64_t val, cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu); } =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_BE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + helper_be_stq_mmu(env, addr, int128_gethi(val), new_oi, ra); + helper_be_stq_mmu(env, addr + 8, int128_getlo(val), new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_LE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + helper_le_stq_mmu(env, addr, int128_getlo(val), new_oi, ra); + helper_le_stq_mmu(env, addr + 8, int128_gethi(val), new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + #include "ldst_common.c.inc" =20 /* diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a8eb63ab96..ae67d84638 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1031,6 +1031,42 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr a= ddr, return ret; } =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + Int128 ret; + + validate_memop(oi, MO_128 | MO_BE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + memcpy(&ret, haddr, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + + if (!HOST_BIG_ENDIAN) { + ret =3D bswap128(ret); + } + return ret; +} + +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + Int128 ret; + + validate_memop(oi, MO_128 | MO_LE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + memcpy(&ret, haddr, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + + if (HOST_BIG_ENDIAN) { + ret =3D bswap128(ret); + } + return ret; +} + void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, MemOpIdx oi, uintptr_t ra) { @@ -1115,6 +1151,36 @@ void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr,= uint64_t val, qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + + validate_memop(oi, MO_128 | MO_BE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + if (!HOST_BIG_ENDIAN) { + val =3D bswap128(val); + } + memcpy(haddr, &val, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + + validate_memop(oi, MO_128 | MO_LE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + if (HOST_BIG_ENDIAN) { + val =3D bswap128(val); + } + memcpy(haddr, &val, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) { uint32_t ret; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cb83d2375d..33ef325f6e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3109,6 +3109,140 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, T= CGArg idx, MemOp memop) } } =20 +static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig) +{ + MemOp mop_1 =3D orig, mop_2; + + tcg_debug_assert((orig & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((orig & MO_SIGN) =3D=3D 0); + + /* Use a memory ordering implemented by the host. */ + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (orig & MO_BSWAP)) { + mop_1 &=3D ~MO_BSWAP; + } + + /* Reduce the size to 64-bit. */ + mop_1 =3D (mop_1 & ~MO_SIZE) | MO_64; + + /* Retain the alignment constraints of the original. */ + switch (orig & MO_AMASK) { + case MO_UNALN: + case MO_ALIGN_2: + case MO_ALIGN_4: + mop_2 =3D mop_1; + break; + case MO_ALIGN_8: + /* Prefer MO_ALIGN+MO_64 to MO_ALIGN_8+MO_64. */ + mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; + mop_2 =3D mop_1; + break; + case MO_ALIGN: + /* Second has 8-byte alignment; first has 16-byte alignment. */ + mop_2 =3D mop_1; + mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN_16; + break; + case MO_ALIGN_16: + case MO_ALIGN_32: + case MO_ALIGN_64: + /* Second has 8-byte alignment; first retains original. */ + mop_2 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; + break; + default: + g_assert_not_reached(); + } + ret[0] =3D mop_1; + ret[1] =3D mop_2; +} + +void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +{ + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + addr =3D plugin_prep_mem_callbacks(addr); + + /* TODO: respect atomicity of the operation. */ + /* TODO: allow the tcg backend to see the whole operation. */ + + /* + * Since there are no global TCGv_i128, there is no visible state + * changed if the second load faults. Load directly into the two + * subwords. + */ + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(x, x); + } + + addr_p8 =3D tcg_temp_new(); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); + tcg_temp_free(addr_p8); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(y, y); + } + + plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), + QEMU_PLUGIN_MEM_R); +} + +void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +{ + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); + addr =3D plugin_prep_mem_callbacks(addr); + + /* TODO: respect atomicity of the operation. */ + /* TODO: allow the tcg backend to see the whole operation. */ + + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + addr_p8 =3D tcg_temp_new(); + if ((mop[0] ^ memop) & MO_BSWAP) { + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_bswap64_i64(t, x); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); + tcg_gen_bswap64_i64(t, y); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); + tcg_temp_free_i64(t); + } else { + gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); + } + tcg_temp_free(addr_p8); + + plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), + QEMU_PLUGIN_MEM_W); +} + static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) { switch (opc & MO_SSIZE) { --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115588; cv=none; d=zohomail.com; s=zohoarc; b=IawgAYmODSMhf/dUTenMOVlhj1GPfZmoib4FV8C28pwfqiTgnsprMj46pUXh7OPLzzvft1/T2vUYH3zm2mMAeCa2D736H6zVCSmPHd8m9MrWOB8om94bD1U0/fbAOIxKZYp8S15mUdXVNNVYhAL2iofPabNHaBW5Qy7UWyr4ZKU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115588; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b8Vdz7avFq4oj2Z1iCchXlp/g7e7DbTcC83+zNbX15Y=; b=PQP+/Niu0cb/zJMSBRRVS+dpG9bMyDN22+FTCDwIQI5oIkBtBOgzA2lZGRgbYoHiF/QtxGHkibX+gfNM5+LwckBSHRt2YzlX8gg1PCLXVgGsG0BrWT9B+VQMEo94fedI6JCSmym8KyHbt9GpNhoYDLcAOERwWcZsD45bQg1SH78= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115588823276.40071751736514; Mon, 30 Jan 2023 13:53:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1e-0001zE-Jl; Mon, 30 Jan 2023 16:49:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1d-0001yP-40 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:17 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1b-0005d3-77 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:16 -0500 Received: by mail-pl1-x636.google.com with SMTP id h9so4499124plf.9 for ; Mon, 30 Jan 2023 13:49:14 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b8Vdz7avFq4oj2Z1iCchXlp/g7e7DbTcC83+zNbX15Y=; b=xyBuRwCMV7q44sLcXxf06jtZ1TeO7EShOTm22UN6EXLqgGgZkFJ6gtKTnpsgHBtNYD aQCe+KrjCGtXwlNCiuzz0nE6GzH1aCxft3x2XNy2xdj90NilX9464Io/ef6Y+69hwYb9 Dlev7Sxg5akAA2NTnMNtU+sZKLBlQ3My5/DqgX5hRPU+eEyWKH3vbLyg9zGNV0eul5uL KRrULms/QPeBqbY53MwTD0iwlEBFmFB0/LK5NJnazE9nEyxvb2VT76LcGk2MixA9URgf kKL2QnGLcpMBw5XAYqxHbNAdAIt4Cq3w9iS+B6NrfXe9ZcyfcLFYUC0DgN7OfVvcBAya OcwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b8Vdz7avFq4oj2Z1iCchXlp/g7e7DbTcC83+zNbX15Y=; b=A27rNBpuJ5+YIZq9NktCj2W9fn3dgQnHTeUY+c22qptUm9HHH0nevaLXXbT79A8N4H QvPyMLbFEgPc6n42bRYDKW/n9QNKP6ADtSi4XPsqJxqczx2uxjA+OE+5xg3QY/4S+5tg dg4Zs4nKnLU0kWvAGPZZdDTQEcJGRooS/5AgJI+/V/tvAbx7kXtZJYVQo6P7BuR9OZdm MOt+/gRHMLkIZTLcZmGIXRaLZ/F4XZ/JyUSUjkia6UmYgNUPMgbFavi++c3LM6gAMlXZ FfDhtUIsQzWPZvPHrL1fRlAeTm81ENBIhOTR+yo/N6wxEgkYRlihVHAwwtThrFTzQdAO VDRw== X-Gm-Message-State: AO0yUKXRddwBp0Df9sIaoc2mshu4rftDXLuftZ2xKjrKarzafe0y5qQg n/XvEPFbgzDr8RtYWSs4iEdt0RsWUcenOXQ5 X-Google-Smtp-Source: AK7set8p14L/x4U0a5vJXWCSfsiJ4OdFiHtObb0dWCQ3ZAK2vhS1x43iWAjJ+YeFDNBnEsjRUoPpfA== X-Received: by 2002:a17:90b:4a0a:b0:22b:f24d:e83a with SMTP id kk10-20020a17090b4a0a00b0022bf24de83amr11258335pjb.12.1675115354360; Mon, 30 Jan 2023 13:49:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 16/36] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 Date: Mon, 30 Jan 2023 11:48:24 -1000 Message-Id: <20230130214844.1158612-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115589488100003 This will allow targets to avoid rolling their own. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/tcg-runtime.h | 11 +++++ include/tcg/tcg-op.h | 5 +++ tcg/tcg-op.c | 85 +++++++++++++++++++++++++++++++++++ accel/tcg/atomic_common.c.inc | 45 +++++++++++++++++++ 4 files changed, 146 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 37cbd722bf..e141a6ab24 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -55,6 +55,17 @@ DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64, i32) #endif +#ifdef CONFIG_CMPXCHG128 +DEF_HELPER_FLAGS_5(atomic_cmpxchgo_be, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgo_le, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +#endif + +DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_be, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_le, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) =20 #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(NAME) \ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index e5f5b63c37..31bf3d287e 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -907,6 +907,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i= 32, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, + TCGArg, MemOp); + +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, + TCGArg, MemOp); =20 void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 33ef325f6e..5811ecd3e7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3295,6 +3295,8 @@ typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env,= TCGv, TCGv_i32, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64, TCGv_i64, TCGv_i32); +typedef void (*gen_atomic_cx_i128)(TCGv_i128, TCGv_env, TCGv, + TCGv_i128, TCGv_i128, TCGv_i32); typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, @@ -3305,6 +3307,11 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env= , TCGv, #else # define WITH_ATOMIC64(X) #endif +#ifdef CONFIG_CMPXCHG128 +# define WITH_ATOMIC128(X) X, +#else +# define WITH_ATOMIC128(X) +#endif =20 static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_8] =3D gen_helper_atomic_cmpxchgb, @@ -3314,6 +3321,8 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP= ) + 1] =3D { [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le) WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be) + WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_cmpxchgo_le) + WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) }; =20 void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, @@ -3412,6 +3421,82 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv = addr, TCGv_i64 cmpv, } } =20 +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 c= mpv, + TCGv_i128 newv, TCGArg idx, MemOp memo= p) +{ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Inline expansion below is simply too large for 32-bit hosts. */ + gen_atomic_cx_i128 gen =3D ((memop & MO_BSWAP) =3D=3D MO_LE + ? gen_helper_nonatomic_cmpxchgo_le=20 + : gen_helper_nonatomic_cmpxchgo_be); + MemOpIdx oi =3D make_memop_idx(memop, idx); + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + } else { + TCGv_i128 oldv =3D tcg_temp_new_i128(); + TCGv_i128 tmpv =3D tcg_temp_new_i128(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); + + tcg_gen_qemu_ld_i128(oldv, addr, idx, memop); + + /* Compare i128 */ + tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); + tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); + tcg_gen_or_i64(t0, t0, t1); + + /* tmpv =3D equal ? newv : oldv */ + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, + TCGV128_LOW(newv), TCGV128_LOW(oldv)); + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, + TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); + + /* Unconditional writeback. */ + tcg_gen_qemu_st_i128(tmpv, addr, idx, memop); + tcg_gen_mov_i128(retv, oldv); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i128(tmpv); + tcg_temp_free_i128(oldv); + } +} + +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, + TCGv_i128 newv, TCGArg idx, MemOp memop) +{ + gen_atomic_cx_i128 gen; + + if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { + tcg_gen_nonatomic_cmpxchg_i128(retv, addr, cmpv, newv, idx, memop); + return; + } + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } + + gen_helper_exit_atomic(cpu_env); + + /* + * Produce a result for a well-formed opcode stream. This satisfies + * liveness for set before used, which happens before this dead code + * is removed. + */ + tcg_gen_movi_i64(TCGV128_LOW(retv), 0); + tcg_gen_movi_i64(TCGV128_HIGH(retv), 0); +} + static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop, bool new_val, void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 6602d7689f..8f2ce43ee6 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -55,8 +55,53 @@ CMPXCHG_HELPER(cmpxchgq_be, uint64_t) CMPXCHG_HELPER(cmpxchgq_le, uint64_t) #endif =20 +#ifdef CONFIG_CMPXCHG128 +CMPXCHG_HELPER(cmpxchgo_be, Int128) +CMPXCHG_HELPER(cmpxchgo_le, Int128) +#endif + #undef CMPXCHG_HELPER =20 +Int128 HELPER(nonatomic_cmpxchgo_be)(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, uint32_t oi) +{ +#if TCG_TARGET_REG_BITS =3D=3D 32 + uintptr_t ra =3D GETPC(); + Int128 oldv; + + oldv =3D cpu_ld16_be_mmu(env, addr, oi, ra); + if (int128_eq(oldv, cmpv)) { + cpu_st16_be_mmu(env, addr, newv, oi, ra); + } else { + /* Even with comparison failure, still need a write cycle. */ + probe_write(env, addr, 16, get_mmuidx(oi), ra); + } + return oldv; +#else + g_assert_not_reached(); +#endif +} + +Int128 HELPER(nonatomic_cmpxchgo_le)(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, uint32_t oi) +{ +#if TCG_TARGET_REG_BITS =3D=3D 32 + uintptr_t ra =3D GETPC(); + Int128 oldv; + + oldv =3D cpu_ld16_le_mmu(env, addr, oi, ra); + if (int128_eq(oldv, cmpv)) { + cpu_st16_le_mmu(env, addr, newv, oi, ra); + } else { + /* Even with comparison failure, still need a write cycle. */ + probe_write(env, addr, 16, get_mmuidx(oi), ra); + } + return oldv; +#else + g_assert_not_reached(); +#endif +} + #define ATOMIC_HELPER(OP, TYPE) \ TYPE HELPER(glue(atomic_,OP))(CPUArchState *env, target_ulong addr, \ TYPE val, uint32_t oi) \ --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115484; cv=none; d=zohomail.com; s=zohoarc; b=F0JWH3zhGfP7DxRD0ONEJkf1HTlTF5hwnNa/9D4AdJsx8zVdEpKF3vx2eHH0+SrX0FKX/DxvRH/zLp3OqksMvej1s4X1KIEhqii1Dh4jX0chmzMMET+T/awx3+xRgn6lXjAaDjke5BBy9yHfCCWR0fWo/uR5VhLDty1j9MIOXmQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115484; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a0WrnpFv1Nw89i7DTl3h+lKdWz/K7go9+e+qOQj+GaM=; b=K+NWfb943EREOO3LPX/y17gySoSfO0zUkOZBZFIX5bnbRMVgorBNS+vKe5B1L2Ic5Ilp4e1CJ/Nr9lSvDniBjDPpc7kNDpiwuE+stEigW47j6OS3Dm59FhlkXbjUri9P88koNSOMImdWAxGWsV5OMNzhneYvZHpcagukZ4hnXLA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167511548460330.14425593667511; Mon, 30 Jan 2023 13:51:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1g-0001zP-44; Mon, 30 Jan 2023 16:49:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1f-0001zG-19 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:19 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1d-0005e5-8z for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:18 -0500 Received: by mail-pl1-x630.google.com with SMTP id m2so8099802plg.4 for ; Mon, 30 Jan 2023 13:49:16 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a0WrnpFv1Nw89i7DTl3h+lKdWz/K7go9+e+qOQj+GaM=; b=xWw2NWxGtf7sNPr+vmtYSzXe95vtjJnTVEMcUx2h8hR6VdJ4br7nAq4Ddb8GY15qTE Y4VG7t75COsGijCMAc4dMcVSQGyZPuNMJr9iYMqWc3Ru1pBRM7sctH/r4jeAdDhtWqWm DO8azadDYW54o8GbEVQO8Fb8TMOdPKscl0KqT1OY4o3AaIOInmq5T6auwQOLvJ6gRpv7 0zRqyd99Z4DNmSdmNJx9aQ79l062hAYxeYDPiimgtKxoWZXG1rrjq5OmUAoHP1MyOopk WvR46QkF6hOtOeu1Nu/f1Ci6CuKZ7Z9HFVIVhfS4b37WJvCbrVP224xhA/U0KTOqBZM2 ZBAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a0WrnpFv1Nw89i7DTl3h+lKdWz/K7go9+e+qOQj+GaM=; b=sPQW6ho2Z/oLB0sH68xEfaFb2UEwNg3BuzcZOP8dVj4YC1qD0xfMasqARnW7ThLj8Z S9mrnzaZ+eo4qi6N/YYhz3A1cQe1/33HzOzSsalIN//kV8sFLNs28BBdV+LFSzxvHF5x N3pJiP3FqsBq0Alii2MImh3pvmqOC6zG2Rz2auWug36cnBS2Y/2YxJFAuF/uzWtjnGnI DkB4vkAmOZc0lNZJ4T9J89fwGSBN2qmYzB7Fk4/sdqxVyGi2iKalopgEXDFytJIYHVVM O+NiohzljbSR9mNyv3GOMSkcFX03Yy9jgxPXMtcfmfOw+grNlAjnwZ4/LjzESFrxFpFu jiaA== X-Gm-Message-State: AFqh2kpjI3ko/BdDQIGRf2AqclNU1GnuLBWwUWhB9hc0OXZvqu57kdlE HWTd83J/yRujaetkWifS8H6XJRmt89QsJyBP X-Google-Smtp-Source: AMrXdXuUc6KZ4Ueo6Fu30TsHnU3qi1P0NXWJAaDAnnoWDHqqcVaPNO7Ziygp0gh/npN3fcxRRjIp1A== X-Received: by 2002:a17:90a:77c6:b0:226:3f8:5b78 with SMTP id e6-20020a17090a77c600b0022603f85b78mr53463765pjs.13.1675115355941; Mon, 30 Jan 2023 13:49:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 17/36] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} Date: Mon, 30 Jan 2023 11:48:25 -1000 Message-Id: <20230130214844.1158612-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115486721100011 Content-Type: text/plain; charset="utf-8" Normally this is automatically handled by the CF_PARALLEL checks with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special case of !PREFIX_LOCK where it always wants the non-atomic version. Split these out so that x86 does not have to roll its own. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/tcg/tcg-op.h | 4 ++ tcg/tcg-op.c | 154 +++++++++++++++++++++++++++---------------- 2 files changed, 101 insertions(+), 57 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 31bf3d287e..839d91c0c7 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -910,6 +910,10 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i= 64, TCGv_i64, void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, TCGArg, MemOp); =20 +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, + TCGArg, MemOp); +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, + TCGArg, MemOp); void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, TCGArg, MemOp); =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 5811ecd3e7..c581ae77c4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3325,82 +3325,122 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BS= WAP) + 1] =3D { WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) }; =20 +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, + TCGv_i32 newv, TCGArg idx, MemOp memop) +{ + TCGv_i32 t1 =3D tcg_temp_new_i32(); + TCGv_i32 t2 =3D tcg_temp_new_i32(); + + tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i32(t2, addr, idx, memop); + tcg_temp_free_i32(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, t1, memop); + } else { + tcg_gen_mov_i32(retv, t1); + } + tcg_temp_free_i32(t1); +} + void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, TCGv_i32 newv, TCGArg idx, MemOp memop) { - memop =3D tcg_canonicalize_memop(memop, 0, 0); + gen_atomic_cx_i32 gen; + MemOpIdx oi; =20 if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - TCGv_i32 t1 =3D tcg_temp_new_i32(); - TCGv_i32 t2 =3D tcg_temp_new_i32(); - - tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i32(t2, addr, idx, memop); - tcg_temp_free_i32(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, t1, memop); - } else { - tcg_gen_mov_i32(retv, t1); - } - tcg_temp_free_i32(t1); - } else { - gen_atomic_cx_i32 gen; - MemOpIdx oi; - - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); - - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, retv, memop); - } + tcg_gen_nonatomic_cmpxchg_i32(retv, addr, cmpv, newv, idx, memop); + return; } + + memop =3D tcg_canonicalize_memop(memop, 0, 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); + + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, retv, memop); + } +} + +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, + TCGv_i64 newv, TCGArg idx, MemOp memop) +{ + TCGv_i64 t1, t2; + + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { + tcg_gen_nonatomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } + return; + } + + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + + tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i64(t2, addr, idx, memop); + tcg_temp_free_i64(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i64(retv, t1, memop); + } else { + tcg_gen_mov_i64(retv, t1); + } + tcg_temp_free_i64(t1); } =20 void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, TCGv_i64 newv, TCGArg idx, MemOp memop) { - memop =3D tcg_canonicalize_memop(memop, 1, 0); - if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - TCGv_i64 t1 =3D tcg_temp_new_i64(); - TCGv_i64 t2 =3D tcg_temp_new_i64(); + tcg_gen_nonatomic_cmpxchg_i64(retv, addr, cmpv, newv, idx, memop); + return; + } =20 - tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i64(t2, addr, idx, memop); - tcg_temp_free_i64(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i64(retv, t1, memop); - } else { - tcg_gen_mov_i64(retv, t1); - } - tcg_temp_free_i64(t1); - } else if ((memop & MO_SIZE) =3D=3D MO_64) { -#ifdef CONFIG_ATOMIC64 + if ((memop & MO_SIZE) =3D=3D MO_64) { gen_atomic_cx_i64 gen; - MemOpIdx oi; =20 + memop =3D tcg_canonicalize_memop(memop, 1, 0); gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } =20 - oi =3D make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); -#else gen_helper_exit_atomic(cpu_env); - /* Produce a result, so that we have a well-formed opcode stream - with respect to uses of the result in the (dead) code following= . */ + + /* + * Produce a result for a well-formed opcode stream. This satisfi= es + * liveness for set before used, which happens before this dead co= de + * is removed. + */ tcg_gen_movi_i64(retv, 0); -#endif /* CONFIG_ATOMIC64 */ + return; + } + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_gen_atomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } } else { TCGv_i32 c32 =3D tcg_temp_new_i32(); TCGv_i32 n32 =3D tcg_temp_new_i32(); --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115539; cv=none; d=zohomail.com; s=zohoarc; b=mOVBptmXEAsE+1kLhIEP5nybW2sSmepFGLKlfEaukaTJM/lCZ0lnfpAijFTs+8gMOn/BFN8lUDtQ9lCyWBjcClVxc2s/6D45x33NJqfs0OLlAtRJC8r4rAiS2rLpep1HZcSZ18dJglp8DSj/aaLhXxWfZz0QaoKEFvfnQaSOdHQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115539; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/YmjqRjimF5pBKzTT9PtXE7Qwz8sieC4JwIiThrHTeM=; b=QI2vWGR4bZ/PklfIPUsMNb2VRojZ1e+vdo7jU8fH2hxgVrPLgFR8925hzrr4OkNtoXwYa38OkKvLtvdVAZ8xlL4x84F/4soOXJCGyTJvLCW1rvOJ12n+TIJduP7zl8VCPwfST7YIRCz7UHaVIL3Y0TBr5BPtnuO7JR53ChfMxFI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115539875120.59044370303832; Mon, 30 Jan 2023 13:52:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1i-00020V-To; Mon, 30 Jan 2023 16:49:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1g-0001ze-Gl for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:20 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1e-0005cc-Ew for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:20 -0500 Received: by mail-pj1-x1031.google.com with SMTP id rm7-20020a17090b3ec700b0022c05558d22so12468018pjb.5 for ; Mon, 30 Jan 2023 13:49:17 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115541198100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-2-richard.henderson@linaro.org> --- target/arm/helper-a64.h | 6 --- target/arm/helper-a64.c | 104 ------------------------------------- target/arm/translate-a64.c | 60 ++++++++++++--------- 3 files changed, 35 insertions(+), 135 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7b706571bb..94065d1917 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -50,12 +50,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16= , ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, - i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, - i64, env, i64, i64, i64) DEF_HELPER_5(casp_le_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_5(casp_be_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 77a8502b6b..7dbdb2c233 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -505,110 +505,6 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val= , uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); - Int128 newv =3D int128_make128(new_lo, new_hi); - Int128 oldv; - uintptr_t ra =3D GETPC(); - uint64_t o0, o1; - bool success; - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi0 =3D make_memop_idx(MO_LEUQ | MO_ALIGN_16, mem_idx); - MemOpIdx oi1 =3D make_memop_idx(MO_LEUQ, mem_idx); - - o0 =3D cpu_ldq_le_mmu(env, addr + 0, oi0, ra); - o1 =3D cpu_ldq_le_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - cpu_stq_le_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - cpu_stq_le_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); - } - - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - bool success; - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); - - success =3D int128_eq(oldv, cmpv); - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - /* - * High and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - Int128 cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val= ); - Int128 newv =3D int128_make128(new_hi, new_lo); - Int128 oldv; - uintptr_t ra =3D GETPC(); - uint64_t o0, o1; - bool success; - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi0 =3D make_memop_idx(MO_BEUQ | MO_ALIGN_16, mem_idx); - MemOpIdx oi1 =3D make_memop_idx(MO_BEUQ, mem_idx); - - o1 =3D cpu_ldq_be_mmu(env, addr + 0, oi0, ra); - o0 =3D cpu_ldq_be_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - cpu_stq_be_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - cpu_stq_be_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); - } - - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - bool success; - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_BE | MO_128 | MO_ALIGN, mem_idx); - - /* - * High and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); - newv =3D int128_make128(new_hi, new_lo); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - - success =3D int128_eq(oldv, cmpv); - return !success; -} - /* Writes back the old data into Rs. */ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_lo, uint64_t new_hi) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 52b1b8a1f0..bd97666ddc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2586,32 +2586,42 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (!HAVE_CMPXCHG128) { - gen_helper_exit_atomic(cpu_env); - /* - * Produce a result so we have a well-formed opcode - * stream when the following (dead) code uses 'tmp'. - * TCG will remove the dead ops for us. - */ - tcg_gen_movi_i64(tmp, 0); - } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, - cpu_exclusive_addr, - cpu_reg(s, rt), - cpu_reg(s, rt2)); - } else { - gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, - cpu_exclusive_addr, - cpu_reg(s, rt), - cpu_reg(s, rt2)); - } - } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_add= r, - cpu_reg(s, rt), cpu_reg(s, rt2)= ); } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_add= r, - cpu_reg(s, rt), cpu_reg(s, rt2)= ); + TCGv_i128 t16 =3D tcg_temp_new_i128(); + TCGv_i128 c16 =3D tcg_temp_new_i128(); + TCGv_i64 a, b; + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt), cpu_reg(s, rt= 2)); + tcg_gen_concat_i64_i128(c16, cpu_exclusive_val, + cpu_exclusive_high); + } else { + tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt2), cpu_reg(s, r= t)); + tcg_gen_concat_i64_i128(c16, cpu_exclusive_high, + cpu_exclusive_val); + } + + tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16, + get_mem_index(s), + MO_128 | MO_ALIGN | s->be_data); + tcg_temp_free_i128(c16); + + a =3D tcg_temp_new_i64(); + b =3D tcg_temp_new_i64(); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(a, b, t16); + } else { + tcg_gen_extr_i128_i64(b, a, t16); + } + + tcg_gen_xor_i64(a, a, cpu_exclusive_val); + tcg_gen_xor_i64(b, b, cpu_exclusive_high); + tcg_gen_or_i64(tmp, a, b); + tcg_temp_free_i64(a); + tcg_temp_free_i64(b); + tcg_temp_free_i128(t16); + + tcg_gen_setcondi_i64(TCG_COND_NE, tmp, tmp, 0); } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115579; cv=none; d=zohomail.com; s=zohoarc; b=UjIM0rssXY/2416pQkhhU4frzxKUIU8+PwJdT3iPjm33yM96GnJD4/CKafhZIZujOiExX85P+59hgzpibouQ4QFeMgYsPNgy/AmI8SEFUBPovPBp6ak9ef5/7W2TQ55chQ4cWVyPZ08fZSlyh7jy2xXq/gb9+z0XmgI4WSdyujU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115581407100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-3-richard.henderson@linaro.org> --- target/arm/helper-a64.h | 2 -- target/arm/helper-a64.c | 43 --------------------------- target/arm/translate-a64.c | 61 +++++++++++--------------------------- 3 files changed, 18 insertions(+), 88 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 94065d1917..ff56807247 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -50,8 +50,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16,= ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) -DEF_HELPER_5(casp_le_parallel, void, env, i32, i64, i64, i64) -DEF_HELPER_5(casp_be_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7dbdb2c233..0972a4bdd0 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -505,49 +505,6 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val,= uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Writes back the old data into Rs. */ -void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); - - env->xregs[rs] =3D int128_getlo(oldv); - env->xregs[rs + 1] =3D int128_gethi(oldv); -} - -void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, - uint64_t new_hi, uint64_t new_lo) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - - env->xregs[rs + 1] =3D int128_getlo(oldv); - env->xregs[rs] =3D int128_gethi(oldv); -} - /* * AdvSIMD half-precision */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bd97666ddc..6678894ec7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2694,53 +2694,28 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, tcg_gen_extr32_i64(s2, s1, cmp); } tcg_temp_free_i64(cmp); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (HAVE_CMPXCHG128) { - TCGv_i32 tcg_rs =3D tcg_constant_i32(rs); - if (s->be_data =3D=3D MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, - clean_addr, t1, t2); - } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, - clean_addr, t1, t2); - } - } else { - gen_helper_exit_atomic(cpu_env); - s->base.is_jmp =3D DISAS_NORETURN; - } } else { - TCGv_i64 d1 =3D tcg_temp_new_i64(); - TCGv_i64 d2 =3D tcg_temp_new_i64(); - TCGv_i64 a2 =3D tcg_temp_new_i64(); - TCGv_i64 c1 =3D tcg_temp_new_i64(); - TCGv_i64 c2 =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_constant_i64(0); + TCGv_i128 cmp =3D tcg_temp_new_i128(); + TCGv_i128 val =3D tcg_temp_new_i128(); =20 - /* Load the two words, in memory order. */ - tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, - MO_64 | MO_ALIGN_16 | s->be_data); - tcg_gen_addi_i64(a2, clean_addr, 8); - tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(val, t1, t2); + tcg_gen_concat_i64_i128(cmp, s1, s2); + } else { + tcg_gen_concat_i64_i128(val, t2, t1); + tcg_gen_concat_i64_i128(cmp, s2, s1); + } =20 - /* Compare the two words, also in memory order. */ - tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); - tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); - tcg_gen_and_i64(c2, c2, c1); + tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, + MO_128 | MO_ALIGN | s->be_data); + tcg_temp_free_i128(val); =20 - /* If compare equal, write back new data, else write back old data= . */ - tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); - tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); - tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); - tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); - tcg_temp_free_i64(a2); - tcg_temp_free_i64(c1); - tcg_temp_free_i64(c2); - - /* Write back the data from memory to Rs. */ - tcg_gen_mov_i64(s1, d1); - tcg_gen_mov_i64(s2, d2); - tcg_temp_free_i64(d1); - tcg_temp_free_i64(d2); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(s1, s2, cmp); + } else { + tcg_gen_extr_i128_i64(s2, s1, cmp); + } + tcg_temp_free_i128(cmp); } } =20 --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NtJttwUEQyaD1SfJG+fgMdQwRfXm20UeXRRXlRvUEX4=; b=ysqGjM9UhOPkSY9P5dWM4jN28xr3d6/azjuKCFLdKsSoT1iCXRxhCDERfgZeyG2hOG xeFwHiHhK7CxZRYToCuoXUrR8AZCY6Zlk6kMOsbg3y1v/Du5QWaFQTn38wLXN9fGA9hb Q/XhYsKSfdS6mg8sGP2LEFV0dfP/unV22Vs+GZbiSARiPappOLwuFa4Vogf5D1kqsyXP OhiNRGmMVPymxkjaw9jOhM4xKTDmswLTgBB2lusIKAv+VzBbENJ0fUxTh5JEs7JtenGM xOGAsOrVwSafIFuG2gpkaFS0GyYLO9bm+XRJJi9Ay4maSTO+FxSV1EyhvSQpqakqlNdG Y6lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NtJttwUEQyaD1SfJG+fgMdQwRfXm20UeXRRXlRvUEX4=; b=UuHhRLA0DILm3V5gVu8chp+A+oeTs4foTHTlfZNurAzpRv7kDJtQ3lyu6DCBMRtuhu llzJmLLr2WJnWsTnzGGI7vj3vg9NhSFOnH35MADgnO36QgonmX+yatLtrrWIW8H9bWjD J+WITOQHW3vMf3232CFJfdQcfD2uq23OziAtINWBln3ydC/Y6dQ3+qmVGq6zFbgW3T7j 7VmHfdGinlIh8qm4xRQCEabA8qpKnE8NF8iT7TpZVqtqOVH4jlTu0VFt5vzwqG9sjFYJ oEkP+bLwlgHdvix8qPbWNAWxH3bXh5FLfpWhh73eROh010rtnbG+zujyPLWk3NTCJUlE fyOQ== X-Gm-Message-State: AFqh2koiIW/y4d6mMIlXF+2R5UavA5bnTHfzpLraTua1midG3ax0hta0 /KNXGjZ3Z2wH2R2ebxyaOKj2rq0VWB6sIfGO X-Google-Smtp-Source: AMrXdXtVGvm9vS9Jy0OOlgE2tyDhKEkeBlKDJiZ3Y1dVk9mmriEa/ZWTn2G5+mMyZtftu0nZX+QRkQ== X-Received: by 2002:a17:90a:384f:b0:227:b29:ae56 with SMTP id l15-20020a17090a384f00b002270b29ae56mr54727560pjf.1.1675115360823; Mon, 30 Jan 2023 13:49:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v6 20/36] target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX Date: Mon, 30 Jan 2023 11:48:28 -1000 Message-Id: <20230130214844.1158612-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115377354100001 Content-Type: text/plain; charset="utf-8" Note that the previous direct reference to reserve_val, - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))); was incorrect because all references should have gone through cpu_reserve_val. Create a cpu_reserve_val2 tcg temp to fix this. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Message-Id: <20221112061122.2720163-2-richard.henderson@linaro.org> --- target/ppc/helper.h | 2 - target/ppc/mem_helper.c | 44 ----------------- target/ppc/translate.c | 102 ++++++++++++++++++---------------------- 3 files changed, 47 insertions(+), 101 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 8dd22a35e4..0beaca5c7a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -818,6 +818,4 @@ DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) -DEF_HELPER_5(stqcx_le_parallel, i32, env, tl, i64, i64, i32) -DEF_HELPER_5(stqcx_be_parallel, i32, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index d1163f316c..1578887a8f 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -413,50 +413,6 @@ void helper_stq_be_parallel(CPUPPCState *env, target_u= long addr, val =3D int128_make128(lo, hi); cpu_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } - -uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, - uint64_t new_lo, uint64_t new_hi, - uint32_t opidx) -{ - bool success =3D false; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_CMPXCHG128); - - if (likely(addr =3D=3D env->reserve_addr)) { - Int128 oldv, cmpv, newv; - - cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, - opidx, GETPC()); - success =3D int128_eq(oldv, cmpv); - } - env->reserve_addr =3D -1; - return env->so + success * CRF_EQ_BIT; -} - -uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, - uint64_t new_lo, uint64_t new_hi, - uint32_t opidx) -{ - bool success =3D false; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_CMPXCHG128); - - if (likely(addr =3D=3D env->reserve_addr)) { - Int128 oldv, cmpv, newv; - - cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, - opidx, GETPC()); - success =3D int128_eq(oldv, cmpv); - } - env->reserve_addr =3D -1; - return env->so + success * CRF_EQ_BIT; -} #endif =20 /*************************************************************************= ****/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index edb3daa9b5..1c17d5a558 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -72,6 +72,7 @@ static TCGv cpu_cfar; static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; static TCGv cpu_reserve_val; +static TCGv cpu_reserve_val2; static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; =20 @@ -141,8 +142,11 @@ void ppc_translate_init(void) offsetof(CPUPPCState, reserve_addr), "reserve_addr"); cpu_reserve_val =3D tcg_global_mem_new(cpu_env, - offsetof(CPUPPCState, reserve_val), - "reserve_val"); + offsetof(CPUPPCState, reserve_val= ), + "reserve_val"); + cpu_reserve_val2 =3D tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, reserve_va= l2), + "reserve_val2"); =20 cpu_fpscr =3D tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, fpscr), "fpscr"); @@ -3998,78 +4002,66 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { + TCGLabel *lab_fail, *lab_over; int rs =3D rS(ctx->opcode); - TCGv EA, hi, lo; + TCGv EA, t0, t1; + TCGv_i128 cmp, val; =20 if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } =20 + lab_fail =3D gen_new_label(); + lab_over =3D gen_new_label(); + gen_set_access_type(ctx, ACCESS_RES); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); =20 + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); + tcg_temp_free(EA); + + cmp =3D tcg_temp_new_i128(); + val =3D tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); + /* Note that the low part is always in RS+1, even in LE mode. */ - lo =3D cpu_gpr[rs + 1]; - hi =3D cpu_gpr[rs]; + tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); =20 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - if (HAVE_CMPXCHG128) { - TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); - if (ctx->le_mode) { - gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, - EA, lo, hi, oi); - } else { - gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, - EA, lo, hi, oi); - } - tcg_temp_free_i32(oi); - } else { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } - tcg_temp_free(EA); - } else { - TCGLabel *lab_fail =3D gen_new_label(); - TCGLabel *lab_over =3D gen_new_label(); - TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new_i64(); + tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + tcg_temp_free_i128(cmp); =20 - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); - tcg_temp_free(EA); + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + tcg_gen_extr_i128_i64(t1, t0, val); + tcg_temp_free_i128(val); =20 - gen_qemu_ld64_i64(ctx, t0, cpu_reserve); - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))= ); - tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); + tcg_gen_xor_tl(t0, t0, cpu_reserve_val); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); =20 - tcg_gen_addi_i64(t0, cpu_reserve, 8); - gen_qemu_ld64_i64(ctx, t0, t0); - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val) - : offsetof(CPUPPCState, reserve_val2)= )); - tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(t0, t0, cpu_so); + tcg_gen_trunc_tl_i32(cpu_crf[0], t0); + tcg_temp_free(t0); =20 - /* Success */ - gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); - tcg_gen_addi_i64(t0, cpu_reserve, 8); - gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); + tcg_gen_br(lab_over); + gen_set_label(lab_fail); =20 - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); - tcg_gen_br(lab_over); + /* + * Address mismatch implies failure. But we still need to provide + * the memory barrier semantics of the instruction. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); =20 - gen_set_label(lab_fail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - - gen_set_label(lab_over); - tcg_gen_movi_tl(cpu_reserve, -1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } + gen_set_label(lab_over); + tcg_gen_movi_tl(cpu_reserve, -1); } #endif /* defined(TARGET_PPC64) */ =20 --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115510; cv=none; d=zohomail.com; s=zohoarc; b=EgPxz4eTxWh0Q44JQUm+MlHoey0YKlCUubw5lVlHNmfdNRv1e/FshWrzCSN8F1g+SHyz1IeKbu8rueMMctBifF+IzWO8q5za8VVJY2yovwatUlJrzu6lxBow/itgc/Z6nZFSN5jvZWY6WOLKs+ZvgKevZ8x6potiOIADT1LM/hg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115510; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=dINMSb0y4OFETixaK0FmFDWTRvnR7Cd/Xl2N+pHlPS9WEkG3IdlCYEzw6m/LBKWoJ1BwF/CcfLcq9p1wyxtkuINvdpBYGyBkZZO/pjd6x1jf3bcEPjDuP//DHWQl+JhqwPSMQ6IjQl7DQIBPgGFMNQ+jZPJRecSCpUriRgTWolg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115510563508.1584718101474; Mon, 30 Jan 2023 13:51:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1m-00023K-If; Mon, 30 Jan 2023 16:49:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1k-00022E-Qj for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:24 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1j-0005cH-9h for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:24 -0500 Received: by mail-pj1-x102e.google.com with SMTP id b10so12406652pjo.1 for ; Mon, 30 Jan 2023 13:49:22 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=a/mKnFWkFkrsMDSXNIUz1YXZmxG6PFzNAWl/Rh37uU7OD3ZrgaducTv2SSvr3uu3a8 AA59FOktECBjvPn8RTETU2qgkXzo7LUWjVDcuaChmIHHi/LcN0a96Q9+38Hcqjpw/ZhH CTx3xhDpYtwpVscfV+OuwhYpFr6X8SlqbsF3gCrAH8BBrUZHj6lqgKBY0Jj5QWVxgfMj OU+XH5XPPWy0V4rEr2ABx1b0FZkkwN5AkZi4IqWIAqx1SQni6VfaKgmNt3F6baUyfmW8 s0Q6ZKdna4BA0Xk/xJDYTyPFPJlhDjZEpFrdX9JOyAOAZaUd3/ldN9M+J1D/OTwFR1DV A9/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=hlKxc7vGD/nKRs5y1/AXf2es8hJ3aWRXmf68RS9Mcxaojj6SuHsxUNALDwoAnhVSN6 pn3DiaPKq2xDmWlI6KryhIekre/ETg/6kDiZzGtCDPOTHBapcugD76hoXPtW4cPSVkOG HE6chJx1v20vPxufr5Hei25ErR+ZCZLWAkP9o12aWzXPpd4iqjzYQrk/naY/wXQ86ML6 UxG/3rflLuDbMvmGSiinmruYJAMp8vIOb1z6Op9GE50HvPhgxFXkRLjLfaGR18OGC1Zj sX+BYpeZCne3T9ecJ9tjrDr/YQGXN/l6nT8hVdw4d9Gl97ia0mZm9dfPWLGExKPbwd6y yeqg== X-Gm-Message-State: AO0yUKX94eBQEVLuB3oNSPbRpjeY1jNeznVKLGFcA2b99TZ7+fn80pTJ +5r3tkhqCniVeMnRpFiMjiwr9QMxio8eB+uv X-Google-Smtp-Source: AK7set/8klT1lPW9ZPjK8HOCDXvNMpi8SSikJzhiejkCA9jIIG10t2kbGBw0v35191Skfwttxa+Jpw== X-Received: by 2002:a17:90b:1d11:b0:22c:944b:3724 with SMTP id on17-20020a17090b1d1100b0022c944b3724mr6656943pjb.8.1675115362526; Mon, 30 Jan 2023 13:49:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, Ilya Leoshkevich Subject: [PATCH v6 21/36] tests/tcg/s390x: Add div.c Date: Mon, 30 Jan 2023 11:48:29 -1000 Message-Id: <20230130214844.1158612-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115511023100001 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221101111300.2539919-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/div.c | 40 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 41 insertions(+) create mode 100644 tests/tcg/s390x/div.c diff --git a/tests/tcg/s390x/div.c b/tests/tcg/s390x/div.c new file mode 100644 index 0000000000..5807295614 --- /dev/null +++ b/tests/tcg/s390x/div.c @@ -0,0 +1,40 @@ +#include +#include + +static void test_dr(void) +{ + register int32_t r0 asm("r0") =3D -1; + register int32_t r1 asm("r1") =3D -4241; + int32_t b =3D 101, q, r; + + asm("dr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D -41); + assert(r =3D=3D -100); +} + +static void test_dlr(void) +{ + register uint32_t r0 asm("r0") =3D 0; + register uint32_t r1 asm("r1") =3D 4243; + uint32_t b =3D 101, q, r; + + asm("dlr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D 42); + assert(r =3D=3D 1); +} + +int main(void) +{ + test_dr(); + test_dlr(); +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index 07fcc6d0ce..ab7a3bcfb2 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -24,6 +24,7 @@ TESTS+=3Dtrap TESTS+=3Dsignals-s390x TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec +TESTS+=3Ddiv =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115483; cv=none; d=zohomail.com; s=zohoarc; b=X6t6RUWsjT9vSjbynjFVBD1yWJ4ZXCB1rstjDp7ehi/2U+aLCxjv5BFfMlyIcnEhz1qp7yQIyF+1WBVm8kwXrnWYmkA53L7raGYtp1oYrhMYIo8U6RkHzhMQEg5LUPlLuLptPfI4TEx7tIwe6CHi35HCVfSyV0mOL0oYe/kd5+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115483; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=ExRgLVlcKyH8vYW58tQGmZE0xHn0rvU3MHHUDV4aYZNpIASpLlYUrLAXvN3dtxyv8bbIFjEK72pv10gM44Xby8tKkvuxgzx63RQYN19jz7LQviMbPZVhUR8ZeAM58GcXltkL9PnqwFKFWBBvyZ2PW73f82uEuzMl0Fi0Z93AlJ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115483304772.4114521210545; Mon, 30 Jan 2023 13:51:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1p-00026I-4e; Mon, 30 Jan 2023 16:49:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1n-00023V-6S for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:27 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1l-0005h4-KG for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:26 -0500 Received: by mail-pl1-x631.google.com with SMTP id b5so5848803plz.5 for ; Mon, 30 Jan 2023 13:49:25 -0800 (PST) Received: from stoup.. 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Signed-off-by: Ilya Leoshkevich Message-Id: <20221025213008.2209006-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/clst.c | 82 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 83 insertions(+) create mode 100644 tests/tcg/s390x/clst.c diff --git a/tests/tcg/s390x/clst.c b/tests/tcg/s390x/clst.c new file mode 100644 index 0000000000..ed2fe7326c --- /dev/null +++ b/tests/tcg/s390x/clst.c @@ -0,0 +1,82 @@ +#define _GNU_SOURCE +#include +#include + +static int clst(char sep, const char **s1, const char **s2) +{ + const char *r1 =3D *s1; + const char *r2 =3D *s2; + int cc; + + do { + register int r0 asm("r0") =3D sep; + + asm("clst %[r1],%[r2]\n" + "ipm %[cc]\n" + "srl %[cc],28" + : [r1] "+r" (r1), [r2] "+r" (r2), "+r" (r0), [cc] "=3Dr" (cc) + : + : "cc"); + *s1 =3D r1; + *s2 =3D r2; + } while (cc =3D=3D 3); + + return cc; +} + +static const struct test { + const char *name; + char sep; + const char *s1; + const char *s2; + int exp_cc; + int exp_off; +} tests[] =3D { + { + .name =3D "cc0", + .sep =3D 0, + .s1 =3D "aa", + .s2 =3D "aa", + .exp_cc =3D 0, + .exp_off =3D 0, + }, + { + .name =3D "cc1", + .sep =3D 1, + .s1 =3D "a\x01", + .s2 =3D "aa\x01", + .exp_cc =3D 1, + .exp_off =3D 1, + }, + { + .name =3D "cc2", + .sep =3D 2, + .s1 =3D "abc\x02", + .s2 =3D "abb\x02", + .exp_cc =3D 2, + .exp_off =3D 2, + }, +}; + +int main(void) +{ + const struct test *t; + const char *s1, *s2; + size_t i; + int cc; + + for (i =3D 0; i < sizeof(tests) / sizeof(tests[0]); i++) { + t =3D &tests[i]; + s1 =3D t->s1; + s2 =3D t->s2; + cc =3D clst(t->sep, &s1, &s2); + if (cc !=3D t->exp_cc || + s1 !=3D t->s1 + t->exp_off || + s2 !=3D t->s2 + t->exp_off) { + fprintf(stderr, "%s\n", t->name); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index ab7a3bcfb2..79250f31dd 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -25,6 +25,7 @@ TESTS+=3Dsignals-s390x TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec TESTS+=3Ddiv +TESTS+=3Dclst =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115464; cv=none; d=zohomail.com; s=zohoarc; b=al+dhvA86XAGRaWKTpnkh3MUIMhzRJEUOhSEwJvcOoxZuQujSufexQbnW4TI0wkTsidzYFLcF7rjM1KaYxR/uT+c50eLQ2Hy4CZh62UItsv24DkQxomglU6xg4/UVtKa2sEe0sovhSO5V0NVIzn216XTqpnrBCbvLixfML23M/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115464; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wHZLFNNm0ZFp31ulDF75QeL44+XwFwYbg39T7b6YDuI=; b=i/w6Eob/jyCOqwrPm3XIp6xH/sqcLqD+W6S9CvN8LsROH3NHDx2rwU5ISP6/xX5Nz3igOIdVv/b6DQ+oeWi3VCId469646ANHuLJ/6rAVKZ+CRYclbE8snqUkscN3d5tah998hgAlg9Jr21z8dXb0V8bFeiCykm/X+GtcUmzGdI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115464411534.7728719458687; Mon, 30 Jan 2023 13:51:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1q-0002Al-Np; Mon, 30 Jan 2023 16:49:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1p-000261-06 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:29 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1n-0005hE-F4 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:28 -0500 Received: by mail-pj1-x1033.google.com with SMTP id n20-20020a17090aab9400b00229ca6a4636so17013105pjq.0 for ; Mon, 30 Jan 2023 13:49:26 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115466664100003 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tests/tcg/s390x/long-double.c | 24 ++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 25 insertions(+) create mode 100644 tests/tcg/s390x/long-double.c diff --git a/tests/tcg/s390x/long-double.c b/tests/tcg/s390x/long-double.c new file mode 100644 index 0000000000..757a6262fd --- /dev/null +++ b/tests/tcg/s390x/long-double.c @@ -0,0 +1,24 @@ +/* + * Perform some basic arithmetic with long double, as a sanity check. + * With small integral numbers, we can cross-check with integers. + */ + +#include + +int main() +{ + int i, j; + + for (i =3D 1; i < 5; i++) { + for (j =3D 1; j < 5; j++) { + long double la =3D (long double)i + j; + long double lm =3D (long double)i * j; + long double ls =3D (long double)i - j; + + assert(la =3D=3D i + j); + assert(lm =3D=3D i * j); + assert(ls =3D=3D i - j); + } + } + return 0; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index 79250f31dd..1d454270c0 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -26,6 +26,7 @@ TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec TESTS+=3Ddiv TESTS+=3Dclst +TESTS+=3Dlong-double =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/flZifrbzQQQmxJpuLpAQCV8xYiiduPjwGp5rxcesSA=; b=eOxk8OBvRMhVRPokuRn1E4jQzI1bVOFEZtePbdTNNahSHMrSrJW/hYyH5oeh8PYotD QQqb3wLZch5ikfy6thgzh+hsmfRuOiSRK+tWZGsOJ1HT2YUqbOcxg/ihNqh92+byKQsI Gp0OMh6iQduT6V1/pYOSIhMNq4CSt7WFDZBFTob11BWzvM5/PAO+Je6HInn47eeTD6Wz O9fik2brkixUMSEFZ8yczIumvU3G18VPFMQd4aaZDR03nXl2Kf/YJrc/AHY7faoKdaeQ zH4qhnoMMiKE6tdN1hVHRFUHGLJethsb4TZvO3Xg7kz/rKjCNNBXTCcWxniS3De/VFkw AWNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/flZifrbzQQQmxJpuLpAQCV8xYiiduPjwGp5rxcesSA=; b=mxwSlqIof8gA41IRKhlqACaQ8HBX6GEIcjYiJMmZZstaKi1KPdKEqSezCm4FF4XM4P NfSXaR6f7MdQJgzSctLnaZrKLLj4ng8xZ447A+V6NdnB7fRkKrk7ozuVgiQub0AC7nxv 7ANBITYEaQ+EZpUp4FDDJ/hVAmm0Ht8ExcqotXLG/a07EECsWMLHiciLAVNDC+qS85hE DikXs287GsGIqqA0Rk+caosD89bA1QcQFx/by0eLP5odSd/4vGJxEAGzeZ5GKBLasMKS rZLxwt/1lp8fPREs8uIol66NKkDmtM4t9OD4cH0ytZYqzZl5aM3t2UFe7KgqbUTM0uit cThQ== X-Gm-Message-State: AO0yUKVk3gtIN3vyRpiegVqHPUJ0IqPGD5kiXvITzgCLW8eyGYoSdEai nmevvO3WqmCtNDe+ojEWMQ1bxDon+9tX28sV X-Google-Smtp-Source: AK7set8V+y/n7lxVY3ikkJVy/3pLve4TyCdxhlo0egl3F/ZrIXnS2sGJSsAlfeILKfr4ZV8s4KCDqw== X-Received: by 2002:a17:90b:2250:b0:22c:36a6:71a6 with SMTP id hk16-20020a17090b225000b0022c36a671a6mr17190856pjb.41.1675115367438; Mon, 30 Jan 2023 13:49:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, David Hildenbrand Subject: [PATCH v6 24/36] target/s390x: Use a single return for helper_divs32/u32 Date: Mon, 30 Jan 2023 11:48:32 -1000 Message-Id: <20230130214844.1158612-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115603554100003 Pack the quotient and remainder into a single uint64_t. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Fix operand ordering; use tcg_extr32_i64. --- target/s390x/helper.h | 2 +- target/s390x/tcg/int_helper.c | 26 +++++++++++++------------- target/s390x/tcg/translate.c | 8 ++++---- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 93923ca153..bc828d976b 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -10,7 +10,7 @@ DEF_HELPER_FLAGS_4(clc, TCG_CALL_NO_WG, i32, env, i32, i6= 4, i64) DEF_HELPER_3(mvcl, i32, env, i32, i32) DEF_HELPER_3(clcl, i32, env, i32, i32) DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64) -DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, s64, env, s64, s64) +DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, i64, env, s64, s64) DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64) diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 954542388a..7260583cf2 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -34,45 +34,45 @@ #endif =20 /* 64/32 -> 32 signed division */ -int64_t HELPER(divs32)(CPUS390XState *env, int64_t a, int64_t b64) +uint64_t HELPER(divs32)(CPUS390XState *env, int64_t a, int64_t b64) { - int32_t ret, b =3D b64; - int64_t q; + int32_t b =3D b64; + int64_t q, r; =20 if (b =3D=3D 0) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - ret =3D q =3D a / b; - env->retxl =3D a % b; + q =3D a / b; + r =3D a % b; =20 /* Catch non-representable quotient. */ - if (ret !=3D q) { + if (q !=3D (int32_t)q) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - return ret; + return deposit64(q, 32, 32, r); } =20 /* 64/32 -> 32 unsigned division */ uint64_t HELPER(divu32)(CPUS390XState *env, uint64_t a, uint64_t b64) { - uint32_t ret, b =3D b64; - uint64_t q; + uint32_t b =3D b64; + uint64_t q, r; =20 if (b =3D=3D 0) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - ret =3D q =3D a / b; - env->retxl =3D a % b; + q =3D a / b; + r =3D a % b; =20 /* Catch non-representable quotient. */ - if (ret !=3D q) { + if (q !=3D (uint32_t)q) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - return ret; + return deposit64(q, 32, 32, r); } =20 /* 64/64 -> 64 signed division */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a339b277e9..169f7ee1b2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2395,15 +2395,15 @@ static DisasJumpType op_diag(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_divs32(DisasContext *s, DisasOps *o) { - gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + gen_helper_divs32(o->out, cpu_env, o->in1, o->in2); + tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } =20 static DisasJumpType op_divu32(DisasContext *s, DisasOps *o) { - gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + gen_helper_divu32(o->out, cpu_env, o->in1, o->in2); + tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } =20 --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115389; cv=none; d=zohomail.com; s=zohoarc; b=WvwabR00FLPwyxOjvidSl/31W3i9qmuAeBFIqZhleJzIT/w2PU3q59ESOT8KgrImGfMapKdyMzTmYMpEpjqmWUIfbnLpCH79BfbVVszvCM3Gujvgj8M0a1sPYiv+OdDN0a8xDksAeifQIJg5zAWl3nNxUlRDKow/jZ90c8c6V7I= ARC-Message-Signature: i=1; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zggxelJn7xEGVyzBGDuJjR27fAkYzw0xoPZGZDzp+DI=; b=H9i60m4yspr8D6e3U3yUmecbobusHsdOl1+nXPWzGaWLvFWRENL2jQ+p3Z+nRzDmbD Fhvn/z9lJrgDOFO3nE/8/uQ54fESwuHZi1ML2bKE7daimlmka+HVbzdvo5HABUuOG4EU 0avy8JHHBrAhFEIqIhsjvXd2T9nbImgko2736tnIHxt+7ywANw0e6YkaDrzyiVkmSegj BJ1xqvvmhnN26crAKP3wlcVSgFkX/9YiN4aOVg2okIHwgeof102YdGzUYVX3KTv4Lsgl gGVwWtxZACAk/ODH+hylA/Vwid3oJRicvGAr4Ew4D5Fwuc6HVBaq+lOc3TUrWvRsroEx HLIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zggxelJn7xEGVyzBGDuJjR27fAkYzw0xoPZGZDzp+DI=; b=jDgxR6qnXX+b33cV2rn8m40YbZqFc1jh7Kx5nkBhz54JlDaRomFUEPKeGvngm/BM14 5Dijfp7ROEHF2c+zj7v0P7YNOd7w7NOuIgl2qVcn3M34fZbkBh1EHF2prEp3o6ngALIZ lcrG/gIHCF51Qiwl61eMoyEPAzUujb7mJivNRC+cFQEYaRCl71Mn0JSUFKZV8rt+CZWb 3LWr4FIqWoo+eqGkyR8hxvRbz1oJHVZ1a3Lhwf7MgevcK3AlFshVVuGI6Lpr1/eZ6c2n PgOEs3bqgw/t45F1WJa4quCM6pp98QmrMMISzT+mXaX4ucjAwjDUu+c3KXoL2zSQukgI O3mQ== X-Gm-Message-State: AO0yUKV7L4ehBxBemfbcCS7ogBaEHh5mFAjoNnVI4RlAimXu5hMw0xLr lfBnzjf603gsYX8aiBWT777AeAKhD4ds8+dB X-Google-Smtp-Source: AK7set+1qGBIGEH7OzlJYZemqB1YgKEQoQIqZagBxy03haW6/AhxiWhiTnEpL9zUFQp11tQhQwE57g== X-Received: by 2002:a17:90a:354:b0:22b:f763:78d6 with SMTP id 20-20020a17090a035400b0022bf76378d6mr25098249pjf.38.1675115368983; Mon, 30 Jan 2023 13:49:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, Ilya Leoshkevich Subject: [PATCH v6 25/36] target/s390x: Use a single return for helper_divs64/u64 Date: Mon, 30 Jan 2023 11:48:33 -1000 Message-Id: <20230130214844.1158612-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115389423100001 Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- v2: Extended div test case to cover these insns. --- target/s390x/helper.h | 4 ++-- target/s390x/tcg/int_helper.c | 38 +++++++++-------------------------- target/s390x/tcg/translate.c | 14 +++++++++---- tests/tcg/s390x/div.c | 35 ++++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 35 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bc828d976b..593f3c8bee 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -12,8 +12,8 @@ DEF_HELPER_3(clcl, i32, env, i32, i32) DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64) DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, i64, env, s64, s64) DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) -DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, i128, env, s64, s64) +DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_3(srst, void, env, i32, i32) DEF_HELPER_3(srstu, void, env, i32, i32) DEF_HELPER_4(clst, i64, env, i64, i64, i64) diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 7260583cf2..eb8e6dd1b5 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -76,46 +76,26 @@ uint64_t HELPER(divu32)(CPUS390XState *env, uint64_t a,= uint64_t b64) } =20 /* 64/64 -> 64 signed division */ -int64_t HELPER(divs64)(CPUS390XState *env, int64_t a, int64_t b) +Int128 HELPER(divs64)(CPUS390XState *env, int64_t a, int64_t b) { /* Catch divide by zero, and non-representable quotient (MIN / -1). */ if (b =3D=3D 0 || (b =3D=3D -1 && a =3D=3D (1ll << 63))) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } - env->retxl =3D a % b; - return a / b; + return int128_make128(a / b, a % b); } =20 /* 128 -> 64/64 unsigned division */ -uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t b) +Int128 HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64= _t b) { - uint64_t ret; - /* Signal divide by zero. */ - if (b =3D=3D 0) { - tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); - } - if (ah =3D=3D 0) { - /* 64 -> 64/64 case */ - env->retxl =3D al % b; - ret =3D al / b; - } else { - /* ??? Move i386 idivq helper to host-utils. */ -#ifdef CONFIG_INT128 - __uint128_t a =3D ((__uint128_t)ah << 64) | al; - __uint128_t q =3D a / b; - env->retxl =3D a % b; - ret =3D q; - if (ret !=3D q) { - tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); + if (b !=3D 0) { + uint64_t r =3D divu128(&al, &ah, b); + if (ah =3D=3D 0) { + return int128_make128(al, r); } -#else - /* 32-bit hosts would need special wrapper functionality - just ab= ort if - we encounter such a case; it's very unlikely anyways. */ - cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n"); -#endif } - return ret; + /* divide by zero or overflow */ + tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 uint64_t HELPER(cvd)(int32_t reg) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 169f7ee1b2..6953b81de7 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2409,15 +2409,21 @@ static DisasJumpType op_divu32(DisasContext *s, Dis= asOps *o) =20 static DisasJumpType op_divs64(DisasContext *s, DisasOps *o) { - gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + TCGv_i128 t =3D tcg_temp_new_i128(); + + gen_helper_divs64(t, cpu_env, o->in1, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, t); + tcg_temp_free_i128(t); return DISAS_NEXT; } =20 static DisasJumpType op_divu64(DisasContext *s, DisasOps *o) { - gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out); + TCGv_i128 t =3D tcg_temp_new_i128(); + + gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, t); + tcg_temp_free_i128(t); return DISAS_NEXT; } =20 diff --git a/tests/tcg/s390x/div.c b/tests/tcg/s390x/div.c index 5807295614..6ad9900e08 100644 --- a/tests/tcg/s390x/div.c +++ b/tests/tcg/s390x/div.c @@ -33,8 +33,43 @@ static void test_dlr(void) assert(r =3D=3D 1); } =20 +static void test_dsgr(void) +{ + register int64_t r0 asm("r0") =3D -1; + register int64_t r1 asm("r1") =3D -4241; + int64_t b =3D 101, q, r; + + asm("dsgr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D -41); + assert(r =3D=3D -100); +} + +static void test_dlgr(void) +{ + register uint64_t r0 asm("r0") =3D 0; + register uint64_t r1 asm("r1") =3D 4243; + uint64_t b =3D 101, q, r; + + asm("dlgr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D 42); + assert(r =3D=3D 1); +} + int main(void) { test_dr(); test_dlr(); + test_dsgr(); + test_dlgr(); + return 0; } --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115501; cv=none; d=zohomail.com; s=zohoarc; b=P9N6yX1NkaQsYwtcXg7O+fLB1cM0r+iFG+s6ub7Yu7Fc6Vzf8Cbd4/6+K6VNDSTtrM9EI+1gK4o1ZA4R1xwuTkf68fCUhUGUQNQ9/fUp0/f19BpUcc+2orWmjx3Iw72B7mRiGm4nXbaU7vXqY6d36ObkdY4KpPxVZlkdQewiZLs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115501; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SzDpq4p4TZ0OiGc3bd/AjIVDg1qF6XupmGP3awuLITw=; b=YlK82SYhaUZV/8JU7AE11qUTPyihl9VeMsQaOErjEKXlljJTZe7k4Ek2Cz8ZfjMVB/7iKTc8o9SUEZhsekpKOydu5IuCwcZoW6D87bKz6o3n2aBLY47fv/Tf4qSBkaIoV0sZVsQPSVSIA8VeVlfOjAmBz0tsTNCzFKuPtJrndnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115501983673.3772521161601; Mon, 30 Jan 2023 13:51:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1z-0002YY-HP; Mon, 30 Jan 2023 16:49:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1w-0002IJ-CI for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:36 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1r-0005hv-VX for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:33 -0500 Received: by mail-pj1-x1030.google.com with SMTP id mi9so3238512pjb.4 for ; Mon, 30 Jan 2023 13:49:31 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115503085100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 11 ++++------- target/s390x/tcg/translate.c | 8 ++++++-- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 593f3c8bee..25c2dd0b3c 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -16,7 +16,7 @@ DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, i128, env, s64= , s64) DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_3(srst, void, env, i32, i32) DEF_HELPER_3(srstu, void, env, i32, i32) -DEF_HELPER_4(clst, i64, env, i64, i64, i64) +DEF_HELPER_4(clst, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvpg, TCG_CALL_NO_WG, i32, env, i64, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index cb82cd1c1d..9be42851d8 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -886,7 +886,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) } =20 /* unsigned string compare (c is string terminator) */ -uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_= t s2) +Int128 HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t = s2) { uintptr_t ra =3D GETPC(); uint32_t len; @@ -904,23 +904,20 @@ uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c,= uint64_t s1, uint64_t s2) if (v1 =3D=3D c) { /* Equal. CC=3D0, and don't advance the registers. */ env->cc_op =3D 0; - env->retxl =3D s2; - return s1; + return int128_make128(s2, s1); } } else { /* Unequal. CC=3D{1,2}, and advance the registers. Note that the terminator need not be zero, but the string that contai= ns the terminator is by definition "low". */ env->cc_op =3D (v1 =3D=3D c ? 1 : v2 =3D=3D c ? 2 : v1 < v2 ? = 1 : 2); - env->retxl =3D s2 + len; - return s1 + len; + return int128_make128(s2 + len, s1 + len); } } =20 /* CPU-determined bytes equal; advance the registers. */ env->cc_op =3D 3; - env->retxl =3D s2 + len; - return s1 + len; + return int128_make128(s2 + len, s1 + len); } =20 /* move page */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 6953b81de7..8397fe2bd8 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2164,9 +2164,13 @@ static DisasJumpType op_clm(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_clst(DisasContext *s, DisasOps *o) { - gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2); + TCGv_i128 pair =3D tcg_temp_new_i128(); + + gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2); + tcg_gen_extr_i128_i64(o->in2, o->in1, pair); + tcg_temp_free_i128(pair); + set_cc_static(s); - return_low128(o->in2); return DISAS_NEXT; } =20 --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115457; cv=none; d=zohomail.com; s=zohoarc; b=AcX2ims/AvkBGaEkpep/0jDh0DuBlYI9CjVgRV55NHNabsAQyFOP2k4PN7IYZ1okRDBsmiLQ/ASgoodQQOuvez2nZpAg6JZv9+J6j3P0QLttrUigGVhyMdXsFPkt6cXXTPjXrs43MsFvHRHSVLcAszEi5hEKbouZziaO/lXaqbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115457; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eH8QC2IFkRWe6pofdb+MHZgnEhO+cdUQERbeKdouJGM=; b=lW3KmN9UgyxZg++H2N5bgRDgho9KcNP22urhE184mGQ/j9TEn2nRHWIiG43MEq1i95MfhBURUfxBIN9SmN/MzgV4UU40ls2/Ujd4vWT2pG1Odmp9VWp9lXb0F/uO3QhPyVzaOqJcK4FYLqyV3NCMYiyqoXmRWtB/5FQIiu2tOUw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115457192275.22198453824114; Mon, 30 Jan 2023 13:50:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc1x-0002Sq-QN; Mon, 30 Jan 2023 16:49:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1w-0002IR-2r for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:36 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1s-0005cc-Ul for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:34 -0500 Received: by mail-pj1-x1031.google.com with SMTP id rm7-20020a17090b3ec700b0022c05558d22so12468533pjb.5 for ; Mon, 30 Jan 2023 13:49:32 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eH8QC2IFkRWe6pofdb+MHZgnEhO+cdUQERbeKdouJGM=; b=U+RYInGRnKhiGrwmwkzKYvFXOZoLAXm0yBpx42FZY1xEh8/9H5B8h1kyX5HOWlLy3W 6+Z/hdEpofVXyln/TuAQRhmtc2C+/xoMBbvpPneLiYPxIp8qMzJ0RBznFvSk1FqZEq1c 1BQj1HTytFI6MQjRI8VUe4ykR3bUMzDzfzUPs8UYNEKFJ2baQ80IeQE0+c7cmepqLYmI x90SbZ2Feg39zwPIiJ3eIAPOj4pSRZM6fVkwl/iONjI5PH6muVs+9YCtEsoX3Ya550a1 KA8gncqPFgCyeFCZ+fqdLGUEhfaOGvZZ3LMcECmBu0gU2Gmbw5hQDSiz6vcSCP70imZI 4n5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eH8QC2IFkRWe6pofdb+MHZgnEhO+cdUQERbeKdouJGM=; b=ztSspTeM6IpX5y1lJcpux5CjlzbVgEIh+HAPPIyp7nOJjod0e4aHkbzzUNsyWeSB9P SE0i73pQ0GUhZiX7lkPQWevRKj9pPFOrEe1iPPaNJPuBA+6noSH8etqF/gB/cXPFYbuH tPdS5mEZ18Kush3Qh9acAG52aB8itqMWikkCBFiwdjyT5kZbxqwFDuWCia/Zatihe4pA Fi/d5UxAlZAORVRoDZASGJmpwjgHrLn6Xy0xtxxHjolWw6ErY6OorSbHLIEtx9dqoByh /XZePcDDqdqfsunLa6o6rHp1B7B8TjpMENO86LqVlRwTUPrEZ/QyEXAnBk00OOcPQ2PR zGRw== X-Gm-Message-State: AO0yUKUBLhrTWtyg8JF3rVfYe8MxvWuMCs0tEoZvbXz9YEY9r/Iuip1W zD+uN2ArYXpSu7naryF/Io0h+NSN3IDqYKYb X-Google-Smtp-Source: AK7set+7VvJWzEUZwfgIIQM1e6DpZaMIX/meA46nuHe6zzCdjcSnDlkRW7QEn3IPsWNoCZWZjv7j9w== X-Received: by 2002:a17:90b:1b4f:b0:22c:28c6:74fb with SMTP id nv15-20020a17090b1b4f00b0022c28c674fbmr17700259pjb.19.1675115372169; Mon, 30 Jan 2023 13:49:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, Ilya Leoshkevich Subject: [PATCH v6 27/36] target/s390x: Use Int128 for return from CKSM Date: Mon, 30 Jan 2023 11:48:35 -1000 Message-Id: <20230130214844.1158612-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115458562100001 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++---- target/s390x/tcg/translate.c | 6 ++++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 25c2dd0b3c..03b29efa3e 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -103,7 +103,7 @@ DEF_HELPER_4(tre, i64, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) -DEF_HELPER_4(cksm, i64, env, i64, i64, i64) +DEF_HELPER_4(cksm, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i= 64) DEF_HELPER_FLAGS_2(sfpc, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 9be42851d8..b0b403e23a 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1350,8 +1350,8 @@ uint32_t HELPER(clclu)(CPUS390XState *env, uint32_t r= 1, uint64_t a2, } =20 /* checksum */ -uint64_t HELPER(cksm)(CPUS390XState *env, uint64_t r1, - uint64_t src, uint64_t src_len) +Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, + uint64_t src, uint64_t src_len) { uintptr_t ra =3D GETPC(); uint64_t max_len, len; @@ -1392,8 +1392,7 @@ uint64_t HELPER(cksm)(CPUS390XState *env, uint64_t r1, env->cc_op =3D (len =3D=3D src_len ? 0 : 3); =20 /* Return both cksm and processed length. */ - env->retxl =3D cksm; - return len; + return int128_make128(cksm, len); } =20 void HELPER(pack)(CPUS390XState *env, uint32_t len, uint64_t dest, uint64_= t src) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8397fe2bd8..1a7aa9e4ae 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2041,11 +2041,13 @@ static DisasJumpType op_cxlgb(DisasContext *s, Disa= sOps *o) static DisasJumpType op_cksm(DisasContext *s, DisasOps *o) { int r2 =3D get_field(s, r2); + TCGv_i128 pair =3D tcg_temp_new_i128(); TCGv_i64 len =3D tcg_temp_new_i64(); =20 - gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]); + gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]); set_cc_static(s); - return_low128(o->out); + tcg_gen_extr_i128_i64(o->out, len, pair); + tcg_temp_free_i128(pair); =20 tcg_gen_add_i64(regs[r2], regs[r2], len); tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len); --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115557; cv=none; d=zohomail.com; s=zohoarc; b=DHnO2B497nL8lH5stwhMUr28X9RxJQeEYNfiY0xoXQllWHmRAU0wxl0Tpt7bANx7BFxjF2Dzw3iLxrLWiQ5RTdsJDLTDV/dP60hwJY2UryDA+fX3RgFtRH1MGtvsXhkFjffUHy7gpqkvKpwFafdvWjbyCBpdQBu0xSTMc3s/0wo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115557; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U/HSkpGEvHbItuZnMKBTZy7j63PzLUxQ950pxrJaTtQ=; b=WQRhnk/PYQhrDT1likBqyUjFM5WkK67wSB0RZCl0AiP6nTfnGNxbeB2h8FrHH64o+fFuWMQhQtH7UR2Ue2TqPPojhAzjdEGvfWAW+RJYvnV3DmHQ/jONfvs8t7JIqVGjQsAoPg4v7IexqFK7klwumaua4hJ8tAcnWuA4wXEDyMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115556994169.17359579673143; Mon, 30 Jan 2023 13:52:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc20-0002b6-Cg; Mon, 30 Jan 2023 16:49:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc1x-0002SX-Hj for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:37 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc1v-0005iO-Qd for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:37 -0500 Received: by mail-pj1-x102e.google.com with SMTP id cl23-20020a17090af69700b0022c745bfdc3so5893870pjb.3 for ; Mon, 30 Jan 2023 13:49:34 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115559286100002 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++---- target/s390x/tcg/translate.c | 7 +++++-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 03b29efa3e..b4170a4256 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -99,7 +99,7 @@ DEF_HELPER_FLAGS_4(unpka, TCG_CALL_NO_WG, i32, env, i64, = i32, i64) DEF_HELPER_FLAGS_4(unpku, TCG_CALL_NO_WG, i32, env, i64, i32, i64) DEF_HELPER_FLAGS_3(tp, TCG_CALL_NO_WG, i32, env, i64, i32) DEF_HELPER_FLAGS_4(tr, TCG_CALL_NO_WG, void, env, i32, i64, i64) -DEF_HELPER_4(tre, i64, env, i64, i64, i64) +DEF_HELPER_4(tre, i128, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index b0b403e23a..49969abda7 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1632,8 +1632,8 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uin= t64_t array, do_helper_tr(env, len, array, trans, GETPC()); } =20 -uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, - uint64_t len, uint64_t trans) +Int128 HELPER(tre)(CPUS390XState *env, uint64_t array, + uint64_t len, uint64_t trans) { uintptr_t ra =3D GETPC(); uint8_t end =3D env->regs[0] & 0xff; @@ -1668,8 +1668,7 @@ uint64_t HELPER(tre)(CPUS390XState *env, uint64_t arr= ay, } =20 env->cc_op =3D cc; - env->retxl =3D len - i; - return array + i; + return int128_make128(len - i, array + i); } =20 static inline uint32_t do_helper_trt(CPUS390XState *env, int len, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 1a7aa9e4ae..f3e4b70ed9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -4905,8 +4905,11 @@ static DisasJumpType op_tr(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_tre(DisasContext *s, DisasOps *o) { - gen_helper_tre(o->out, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out2); + TCGv_i128 pair =3D tcg_temp_new_i128(); + + gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, pair); + tcg_temp_free_i128(pair); set_cc_static(s); return DISAS_NEXT; } --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115617; cv=none; d=zohomail.com; s=zohoarc; b=Yu8D8OCeEgAjUoCNQlhuaglkEhEJtbRZyOmSYDuBERxQcHeUTxGYtLSwsFsQypV9WXIOsyWcOFBgHAej9nOGBHZwsW3+vl5HlJnbNnU1y2Xjpm6cFO95bKDCFqFJk7PFjvONXpM7/Wwvb4VcOCatOfFFK12UnCn3a8hmEugBQew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115617; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+jhW1VfMMjd/T4xu5tAsEJqCQwclAn0GfVV3GJNGabg=; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+jhW1VfMMjd/T4xu5tAsEJqCQwclAn0GfVV3GJNGabg=; b=HwKET3Vb1qJPQ+FHgP4nyXgjA1CyDShpprs1RA+gTUFiLn9VCl1dskM+ujYO922kac jyqyEdGV7I+lPtR4bGij822dviSpgzQPEPuXWGyf1MQ3qv0tPOz5wSkWyjIhimIxCK8I BPZC7/9rlvV7Ka7mzUKJR7VVc0S/VaiP/4UrUzJ0shHAjExilGwiEva4xcdd9FMTHuvB kXLf2qiE/osKJDvECOuCSmVVml3CdSRaMvDk92jT37sazeV+yuQbK3ThSJKwrBTx6BLG XWA0/q4wWfAHhg8Hrs623Nx820G8Gms84KwwBh6u9IcsAnG5jOSAdejHoV0Xp9T5Z9P3 zGSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+jhW1VfMMjd/T4xu5tAsEJqCQwclAn0GfVV3GJNGabg=; b=fxEaFG6Rqb1nxZaPVTg33RH/TmA10HmHEWPTnu6VX9GhMJrl29kyRo8V4d8tldY/d9 yn4akfwKOxx6EPU6uI0JaB14qWk4yWmaNzSuNfLIQ8IujFfamRHTlptRwk1t+CQDLryh 0l9K1ips6Q3tI+/26wkYhaUmJa/JhVXWc4hetV7UhDFjMm00Wl5D+5Zae2J59zPC9Ox2 Mqpfpx+YDfTyMPYqICnmSXwWMrBt2Vb+6zpUGvf39v1mZsG0Av7CDTEmmul0OOU5GMJs SfQ6aVfvOSgsyBs1g19rYCCqs+ulYBdjCBsfdc18C3PBGgXdgnLdhPNsb3X1dZmrLdlE 0ZlQ== X-Gm-Message-State: AO0yUKXHFh5NO5gWd5YkcI40Nnhy092wbA+tUtYnKzii4rUwi8EpqhFn 9/6Jd0prThMjm76nNmwDR911n30GnW6A9WQ5 X-Google-Smtp-Source: AK7set8pypnNHuQ8voSnVjgnwcUwjn7u6QrcDxAS6HEZkuA6d0+NKnA+iTsU9InzA1W5V20b+1WAfQ== X-Received: by 2002:a17:90b:4a04:b0:22c:afa2:4783 with SMTP id kk4-20020a17090b4a0400b0022cafa24783mr4578518pjb.39.1675115375431; Mon, 30 Jan 2023 13:49:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, Ilya Leoshkevich Subject: [PATCH v6 29/36] target/s390x: Copy wout_x1 to wout_x1_P Date: Mon, 30 Jan 2023 11:48:37 -1000 Message-Id: <20230130214844.1158612-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115617551100003 Content-Type: text/plain; charset="utf-8" Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/s390x/tcg/insn-data.h.inc | 12 ++++++------ target/s390x/tcg/translate.c | 8 ++++++++ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 79c6ab509a..d0814cb218 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -422,7 +422,7 @@ F(0x3800, LER, RR_a, Z, 0, e2, 0, cond_e1e2, mov2, 0, IF_AFP1 |= IF_AFP2) F(0x7800, LE, RX_a, Z, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1) F(0xed64, LEY, RXY_a, LD, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1) - F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1, movx, 0, IF_AFP1) + F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1_P, movx, 0, IF_AFP1) /* LOAD IMMEDIATE */ C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0) /* LOAD RELATIVE LONG */ @@ -461,7 +461,7 @@ C(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64) F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP) F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP) - F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1, movx, f128, IF_BFP) + F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1_P, movx, f128, IF_BFP) /* LOAD AND TRAP */ C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0) C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0) @@ -483,7 +483,7 @@ C(0xb913, LCGFR, RRE, Z, 0, r2_32s, r1, 0, neg, neg64) F(0xb303, LCEBR, RRE, Z, 0, e2, new, e1, negf32, f32, IF_BFP) F(0xb313, LCDBR, RRE, Z, 0, f2, new, f1, negf64, f64, IF_BFP) - F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1, negf128, f128, IF_= BFP) + F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1_P, negf128, f128, I= F_BFP) F(0xb373, LCDFR, RRE, FPSSH, 0, f2, new, f1, negf64, 0, IF_AFP1 | = IF_AFP2) /* LOAD COUNT TO BLOCK BOUNDARY */ C(0xe727, LCBB, RXE, V, la2, 0, r1, 0, lcbb, 0) @@ -552,7 +552,7 @@ C(0xb911, LNGFR, RRE, Z, 0, r2_32s, r1, 0, nabs, nabs64) F(0xb301, LNEBR, RRE, Z, 0, e2, new, e1, nabsf32, f32, IF_BFP) F(0xb311, LNDBR, RRE, Z, 0, f2, new, f1, nabsf64, f64, IF_BFP) - F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1, nabsf128, f128, IF= _BFP) + F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1_P, nabsf128, f128, = IF_BFP) F(0xb371, LNDFR, RRE, FPSSH, 0, f2, new, f1, nabsf64, 0, IF_AFP1 |= IF_AFP2) /* LOAD ON CONDITION */ C(0xb9f2, LOCR, RRF_c, LOC, r1, r2, new, r1_32, loc, 0) @@ -577,7 +577,7 @@ C(0xb910, LPGFR, RRE, Z, 0, r2_32s, r1, 0, abs, abs64) F(0xb300, LPEBR, RRE, Z, 0, e2, new, e1, absf32, f32, IF_BFP) F(0xb310, LPDBR, RRE, Z, 0, f2, new, f1, absf64, f64, IF_BFP) - F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1, absf128, f128, IF_= BFP) + F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1_P, absf128, f128, I= F_BFP) F(0xb370, LPDFR, RRE, FPSSH, 0, f2, new, f1, absf64, 0, IF_AFP1 | = IF_AFP2) /* LOAD REVERSED */ C(0xb91f, LRVR, RRE, Z, 0, r2_32u, new, r1_32, rev32, 0) @@ -588,7 +588,7 @@ /* LOAD ZERO */ F(0xb374, LZER, RRE, Z, 0, 0, 0, e1, zero, 0, IF_AFP1) F(0xb375, LZDR, RRE, Z, 0, 0, 0, f1, zero, 0, IF_AFP1) - F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1, zero2, 0, IF_AFP1) + F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1_P, zero2, 0, IF_AFP1) =20 /* LOAD FPC */ F(0xb29d, LFPC, S, Z, 0, m2_32u, 0, 0, sfpc, 0, IF_BFP) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f3e4b70ed9..d25b6f3c03 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5518,6 +5518,14 @@ static void wout_x1(DisasContext *s, DisasOps *o) } #define SPEC_wout_x1 SPEC_r1_f128 =20 +static void wout_x1_P(DisasContext *s, DisasOps *o) +{ + int f1 =3D get_field(s, r1); + store_freg(f1, o->out); + store_freg(f1 + 2, o->out2); +} +#define SPEC_wout_x1_P SPEC_r1_f128 + static void wout_cond_r1r2_32(DisasContext *s, DisasOps *o) { if (get_field(s, r1) !=3D get_field(s, r2)) { --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115584; cv=none; d=zohomail.com; s=zohoarc; b=gs6rM/S14GSjWFaXaQQSfih1odleX5/pVh/fdfewUfSvEXoqBVnmVYyQ5Gg8G5ronVE2AVbUbOyRDZJftB0htwA+lNRV7+O0K0JPx5u9R7SqdXBu0u3ArsLDv5oadrYmAMWTxcsDWhuFm9QKjZlctzw+9ySmI3oLnzk2atD0wOk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115584; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Subject: [PATCH v6 30/36] target/s390x: Use Int128 for returning float128 Date: Mon, 30 Jan 2023 11:48:38 -1000 Message-Id: <20230130214844.1158612-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115585429100003 Acked-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- v2: Remove extraneous return_low128. --- target/s390x/helper.h | 22 +++++++------- target/s390x/tcg/insn-data.h.inc | 20 ++++++------- target/s390x/tcg/fpu_helper.c | 29 +++++++++--------- target/s390x/tcg/translate.c | 51 +++++++++++++++++--------------- 4 files changed, 63 insertions(+), 59 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index b4170a4256..d40aeb471f 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -31,32 +31,32 @@ DEF_HELPER_4(clcle, i32, env, i32, i64, i32) DEF_HELPER_4(clclu, i32, env, i32, i64, i32) DEF_HELPER_3(cegb, i64, env, s64, i32) DEF_HELPER_3(cdgb, i64, env, s64, i32) -DEF_HELPER_3(cxgb, i64, env, s64, i32) +DEF_HELPER_3(cxgb, i128, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) -DEF_HELPER_3(cxlgb, i64, env, i64, i32) +DEF_HELPER_3(cxlgb, i128, env, i64, i32) DEF_HELPER_4(cdsg, void, env, i64, i32, i32) DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(seb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(sdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) -DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_2(ldeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_4(ldxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) -DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i128, env, i64) +DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_3(ledb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_4(lexb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) @@ -79,7 +79,7 @@ DEF_HELPER_3(clfdb, i64, env, i64, i32) DEF_HELPER_4(clfxb, i64, env, i64, i64, i32) DEF_HELPER_FLAGS_3(fieb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(fidb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i128, env, i64, i64, i32) DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) @@ -89,7 +89,7 @@ DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i6= 4, i64) DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64) DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i128, env, i64, i64) DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32) DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index d0814cb218..517a4500ae 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -306,10 +306,10 @@ /* CONVERT FROM FIXED */ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP) F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP) - F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_P, x1, cxgb, 0, IF_BFP) + F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_x, x1, cxgb, 0, IF_BFP) F(0xb3a4, CEGBR, RRF_e, Z, 0, r2_o, new, e1, cegb, 0, IF_BFP) F(0xb3a5, CDGBR, RRF_e, Z, 0, r2_o, new, f1, cdgb, 0, IF_BFP) - F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_P, x1, cxgb, 0, IF_BFP) + F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_x, x1, cxgb, 0, IF_BFP) /* CONVERT TO LOGICAL */ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP) F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP) @@ -320,10 +320,10 @@ /* CONVERT FROM LOGICAL */ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP) F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP) - F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_P, x1, cxlgb, 0, IF_BFP) + F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_x, x1, cxlgb, 0, IF_BFP) F(0xb3a0, CELGBR, RRF_e, FPE, 0, r2_o, new, e1, celgb, 0, IF_BFP) F(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, new, f1, cdlgb, 0, IF_BFP) - F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_P, x1, cxlgb, 0, IF_BFP) + F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_x, x1, cxlgb, 0, IF_BFP) =20 /* CONVERT UTF-8 TO UTF-16 */ D(0xb2a7, CU12, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 12) @@ -597,15 +597,15 @@ /* LOAD FP INTEGER */ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP) F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP) - F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_P, x1, fixb, 0, IF_BFP) + F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_x, x1, fixb, 0, IF_BFP) =20 /* LOAD LENGTHENED */ F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP) - F(0xb305, LXDBR, RRE, Z, 0, f2, new_P, x1, lxdb, 0, IF_BFP) - F(0xb306, LXEBR, RRE, Z, 0, e2, new_P, x1, lxeb, 0, IF_BFP) + F(0xb305, LXDBR, RRE, Z, 0, f2, new_x, x1, lxdb, 0, IF_BFP) + F(0xb306, LXEBR, RRE, Z, 0, e2, new_x, x1, lxeb, 0, IF_BFP) F(0xed04, LDEB, RXE, Z, 0, m2_32u, new, f1, ldeb, 0, IF_BFP) - F(0xed05, LXDB, RXE, Z, 0, m2_64, new_P, x1, lxdb, 0, IF_BFP) - F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_P, x1, lxeb, 0, IF_BFP) + F(0xed05, LXDB, RXE, Z, 0, m2_64, new_x, x1, lxdb, 0, IF_BFP) + F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_x, x1, lxeb, 0, IF_BFP) F(0xb324, LDER, RXE, Z, 0, e2, new, f1, lde, 0, IF_AFP1) F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1) /* LOAD ROUNDED */ @@ -835,7 +835,7 @@ /* SQUARE ROOT */ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP) F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP) - F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_P, x1, sqxb, 0, IF_BFP) + F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_x, x1, sqxb, 0, IF_BFP) F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP) F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) =20 diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index be80b2373c..13be44499b 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -34,7 +34,10 @@ #define HELPER_LOG(x...) #endif =20 -#define RET128(F) (env->retxl =3D F.low, F.high) +static inline Int128 RET128(float128 f) +{ + return int128_make128(f.low, f.high); +} =20 uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) { @@ -224,7 +227,7 @@ uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP addition */ -uint64_t HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_add(make_float128(ah, al), @@ -251,7 +254,7 @@ uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP subtraction */ -uint64_t HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_sub(make_float128(ah, al), @@ -278,7 +281,7 @@ uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP division */ -uint64_t HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_div(make_float128(ah, al), @@ -314,7 +317,7 @@ uint64_t HELPER(mdeb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP multiplication */ -uint64_t HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_mul(make_float128(ah, al), @@ -325,8 +328,7 @@ uint64_t HELPER(mxb)(CPUS390XState *env, uint64_t ah, u= int64_t al, } =20 /* 128/64-bit FP multiplication */ -uint64_t HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t f2) +Int128 HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t= f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); ret =3D float128_mul(make_float128(ah, al), ret, &env->fpu_status); @@ -355,7 +357,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, = uint64_t al, } =20 /* convert 64-bit float to 128-bit float */ -uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) +Int128 HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, false, GETPC()); @@ -363,7 +365,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) } =20 /* convert 32-bit float to 128-bit float */ -uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) +Int128 HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, false, GETPC()); @@ -486,7 +488,7 @@ uint64_t HELPER(cdgb)(CPUS390XState *env, int64_t v2, u= int32_t m34) } =20 /* convert 64-bit int to 128-bit float */ -uint64_t HELPER(cxgb)(CPUS390XState *env, int64_t v2, uint32_t m34) +Int128 HELPER(cxgb)(CPUS390XState *env, int64_t v2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D int64_to_float128(v2, &env->fpu_status); @@ -519,7 +521,7 @@ uint64_t HELPER(cdlgb)(CPUS390XState *env, uint64_t v2,= uint32_t m34) } =20 /* convert 64-bit uint to 128-bit float */ -uint64_t HELPER(cxlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) +Int128 HELPER(cxlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D uint64_to_float128(v2, &env->fpu_status); @@ -748,8 +750,7 @@ uint64_t HELPER(fidb)(CPUS390XState *env, uint64_t f2, = uint32_t m34) } =20 /* round to integer 128-bit */ -uint64_t HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +Int128 HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t= m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D float128_round_to_int(make_float128(ah, al), @@ -890,7 +891,7 @@ uint64_t HELPER(sqdb)(CPUS390XState *env, uint64_t f2) } =20 /* square root 128-bit */ -uint64_t HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) +Int128 HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float128 ret =3D float128_sqrt(make_float128(ah, al), &env->fpu_status= ); handle_exceptions(env, false, GETPC()); diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d25b6f3c03..0a750a5467 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1103,6 +1103,7 @@ typedef struct { bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; + TCGv_i128 out_128; } DisasOps; =20 /* Instructions can place constraints on their operands, raising specifica= tion @@ -1461,8 +1462,7 @@ static DisasJumpType op_adb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_axb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -1995,9 +1995,8 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxgb(o->out, cpu_env, o->in2, m34); + gen_helper_cxgb(o->out_128, cpu_env, o->in2, m34); tcg_temp_free_i32(m34); - return_low128(o->out2); return DISAS_NEXT; } =20 @@ -2032,9 +2031,8 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxlgb(o->out, cpu_env, o->in2, m34); + gen_helper_cxlgb(o->out_128, cpu_env, o->in2, m34); tcg_temp_free_i32(m34); - return_low128(o->out2); return DISAS_NEXT; } =20 @@ -2447,8 +2445,7 @@ static DisasJumpType op_ddb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_dxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -2553,8 +2550,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out, cpu_env, o->in1, o->in2, m34); - return_low128(o->out2); + gen_helper_fixb(o->out_128, cpu_env, o->in1, o->in2, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2866,15 +2862,13 @@ static DisasJumpType op_lexb(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_lxdb(DisasContext *s, DisasOps *o) { - gen_helper_lxdb(o->out, cpu_env, o->in2); - return_low128(o->out2); + gen_helper_lxdb(o->out_128, cpu_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_lxeb(DisasContext *s, DisasOps *o) { - gen_helper_lxeb(o->out, cpu_env, o->in2); - return_low128(o->out2); + gen_helper_lxeb(o->out_128, cpu_env, o->in2); return DISAS_NEXT; } =20 @@ -3590,15 +3584,13 @@ static DisasJumpType op_mdb(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_mxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out2); + gen_helper_mxdb(o->out_128, cpu_env, o->out, o->out2, o->in2); return DISAS_NEXT; } =20 @@ -4063,8 +4055,7 @@ static DisasJumpType op_sdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_sxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -4082,8 +4073,7 @@ static DisasJumpType op_sqdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2); - return_low128(o->out2); + gen_helper_sqxb(o->out_128, cpu_env, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -5395,6 +5385,14 @@ static void prep_new_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_new_P 0 =20 +static void prep_new_x(DisasContext *s, DisasOps *o) +{ + o->out =3D tcg_temp_new_i64(); + o->out2 =3D tcg_temp_new_i64(); + o->out_128 =3D tcg_temp_new_i128(); +} +#define SPEC_prep_new_x 0 + static void prep_r1(DisasContext *s, DisasOps *o) { o->out =3D regs[get_field(s, r1)]; @@ -5411,11 +5409,12 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_r1_P SPEC_r1_even =20 -/* Whenever we need x1 in addition to other inputs, we'll load it to out/o= ut2 */ static void prep_x1(DisasContext *s, DisasOps *o) { o->out =3D load_freg(get_field(s, r1)); o->out2 =3D load_freg(get_field(s, r1) + 2); + o->out_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->out_128, o->out2, o->out); } #define SPEC_prep_x1 SPEC_r1_f128 =20 @@ -5513,6 +5512,8 @@ static void wout_f1(DisasContext *s, DisasOps *o) static void wout_x1(DisasContext *s, DisasOps *o) { int f1 =3D get_field(s, r1); + + tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); store_freg(f1, o->out); store_freg(f1 + 2, o->out2); } @@ -6588,7 +6589,9 @@ static DisasJumpType translate_one(CPUS390XState *env= , DisasContext *s) if (o.addr1) { tcg_temp_free_i64(o.addr1); } - + if (o.out_128) { + tcg_temp_free_i128(o.out_128); + } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret =3D=3D DISAS_NEXT)) { ret =3D DISAS_TOO_MANY; --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115562; cv=none; d=zohomail.com; s=zohoarc; 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Hildenbrand Subject: [PATCH v6 31/36] target/s390x: Use Int128 for passing float128 Date: Mon, 30 Jan 2023 11:48:39 -1000 Message-Id: <20230130214844.1158612-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115563330100002 Content-Type: text/plain; charset="utf-8" Acked-by: David Hildenbrand Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v2: Fix SPEC_in1_x1. --- target/s390x/helper.h | 32 ++++++------ target/s390x/tcg/insn-data.h.inc | 30 +++++------ target/s390x/tcg/fpu_helper.c | 88 ++++++++++++++------------------ target/s390x/tcg/translate.c | 76 ++++++++++++++++++--------- 4 files changed, 121 insertions(+), 105 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index d40aeb471f..bccd3bfca6 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -41,55 +41,55 @@ DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(axb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(seb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(sdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(sxb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(dxb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) -DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i128, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(mxb, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(mxdb, TCG_CALL_NO_WG, i128, env, i128, i64) DEF_HELPER_FLAGS_2(ldeb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_4(ldxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(ldxb, TCG_CALL_NO_WG, i64, env, i128, i32) DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_3(ledb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(lexb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(lexb, TCG_CALL_NO_WG, i64, env, i128, i32) DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_3(cdb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) -DEF_HELPER_FLAGS_5(cxb, TCG_CALL_NO_WG_SE, i32, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(cxb, TCG_CALL_NO_WG_SE, i32, env, i128, i128) DEF_HELPER_FLAGS_3(keb, TCG_CALL_NO_WG, i32, env, i64, i64) DEF_HELPER_FLAGS_3(kdb, TCG_CALL_NO_WG, i32, env, i64, i64) -DEF_HELPER_FLAGS_5(kxb, TCG_CALL_NO_WG, i32, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(kxb, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_3(cgeb, i64, env, i64, i32) DEF_HELPER_3(cgdb, i64, env, i64, i32) -DEF_HELPER_4(cgxb, i64, env, i64, i64, i32) +DEF_HELPER_3(cgxb, i64, env, i128, i32) DEF_HELPER_3(cfeb, i64, env, i64, i32) DEF_HELPER_3(cfdb, i64, env, i64, i32) -DEF_HELPER_4(cfxb, i64, env, i64, i64, i32) +DEF_HELPER_3(cfxb, i64, env, i128, i32) DEF_HELPER_3(clgeb, i64, env, i64, i32) DEF_HELPER_3(clgdb, i64, env, i64, i32) -DEF_HELPER_4(clgxb, i64, env, i64, i64, i32) +DEF_HELPER_3(clgxb, i64, env, i128, i32) DEF_HELPER_3(clfeb, i64, env, i64, i32) DEF_HELPER_3(clfdb, i64, env, i64, i32) -DEF_HELPER_4(clfxb, i64, env, i64, i64, i32) +DEF_HELPER_3(clfxb, i64, env, i128, i32) DEF_HELPER_FLAGS_3(fieb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(fidb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i128, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(fixb, TCG_CALL_NO_WG, i128, env, i128, i32) DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(msdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_3(tceb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) -DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i128, i64) DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i128, env, i64, i64) +DEF_HELPER_FLAGS_2(sqxb, TCG_CALL_NO_WG, i128, env, i128) DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32) DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 517a4500ae..893f4b48db 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -34,7 +34,7 @@ C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64) F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP) F(0xb31a, ADBR, RRE, Z, f1, f2, new, f1, adb, f64, IF_BFP) - F(0xb34a, AXBR, RRE, Z, x2h, x2l, x1, x1, axb, f128, IF_BFP) + F(0xb34a, AXBR, RRE, Z, x1, x2, new_x, x1, axb, f128, IF_BFP) F(0xed0a, AEB, RXE, Z, e1, m2_32u, new, e1, aeb, f32, IF_BFP) F(0xed1a, ADB, RXE, Z, f1, m2_64, new, f1, adb, f64, IF_BFP) /* ADD HIGH */ @@ -172,13 +172,13 @@ C(0xe330, CGF, RXY_a, Z, r1_o, m2_32s, 0, 0, 0, cmps64) F(0xb309, CEBR, RRE, Z, e1, e2, 0, 0, ceb, 0, IF_BFP) F(0xb319, CDBR, RRE, Z, f1, f2, 0, 0, cdb, 0, IF_BFP) - F(0xb349, CXBR, RRE, Z, x2h, x2l, x1, 0, cxb, 0, IF_BFP) + F(0xb349, CXBR, RRE, Z, x1, x2, 0, 0, cxb, 0, IF_BFP) F(0xed09, CEB, RXE, Z, e1, m2_32u, 0, 0, ceb, 0, IF_BFP) F(0xed19, CDB, RXE, Z, f1, m2_64, 0, 0, cdb, 0, IF_BFP) /* COMPARE AND SIGNAL */ F(0xb308, KEBR, RRE, Z, e1, e2, 0, 0, keb, 0, IF_BFP) F(0xb318, KDBR, RRE, Z, f1, f2, 0, 0, kdb, 0, IF_BFP) - F(0xb348, KXBR, RRE, Z, x2h, x2l, x1, 0, kxb, 0, IF_BFP) + F(0xb348, KXBR, RRE, Z, x1, x2, 0, 0, kxb, 0, IF_BFP) F(0xed08, KEB, RXE, Z, e1, m2_32u, 0, 0, keb, 0, IF_BFP) F(0xed18, KDB, RXE, Z, f1, m2_64, 0, 0, kdb, 0, IF_BFP) /* COMPARE IMMEDIATE */ @@ -299,10 +299,10 @@ /* CONVERT TO FIXED */ F(0xb398, CFEBR, RRF_e, Z, 0, e2, new, r1_32, cfeb, 0, IF_BFP) F(0xb399, CFDBR, RRF_e, Z, 0, f2, new, r1_32, cfdb, 0, IF_BFP) - F(0xb39a, CFXBR, RRF_e, Z, x2h, x2l, new, r1_32, cfxb, 0, IF_BFP) + F(0xb39a, CFXBR, RRF_e, Z, 0, x2, new, r1_32, cfxb, 0, IF_BFP) F(0xb3a8, CGEBR, RRF_e, Z, 0, e2, r1, 0, cgeb, 0, IF_BFP) F(0xb3a9, CGDBR, RRF_e, Z, 0, f2, r1, 0, cgdb, 0, IF_BFP) - F(0xb3aa, CGXBR, RRF_e, Z, x2h, x2l, r1, 0, cgxb, 0, IF_BFP) + F(0xb3aa, CGXBR, RRF_e, Z, 0, x2, r1, 0, cgxb, 0, IF_BFP) /* CONVERT FROM FIXED */ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP) F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP) @@ -313,10 +313,10 @@ /* CONVERT TO LOGICAL */ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP) F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP) - F(0xb39e, CLFXBR, RRF_e, FPE, x2h, x2l, new, r1_32, clfxb, 0, IF_BFP) + F(0xb39e, CLFXBR, RRF_e, FPE, 0, x2, new, r1_32, clfxb, 0, IF_BFP) F(0xb3ac, CLGEBR, RRF_e, FPE, 0, e2, r1, 0, clgeb, 0, IF_BFP) F(0xb3ad, CLGDBR, RRF_e, FPE, 0, f2, r1, 0, clgdb, 0, IF_BFP) - F(0xb3ae, CLGXBR, RRF_e, FPE, x2h, x2l, r1, 0, clgxb, 0, IF_BFP) + F(0xb3ae, CLGXBR, RRF_e, FPE, 0, x2, r1, 0, clgxb, 0, IF_BFP) /* CONVERT FROM LOGICAL */ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP) F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP) @@ -343,7 +343,7 @@ C(0x5d00, D, RX_a, Z, r1_D32, m2_32s, new_P, r1_P32, divs32, = 0) F(0xb30d, DEBR, RRE, Z, e1, e2, new, e1, deb, 0, IF_BFP) F(0xb31d, DDBR, RRE, Z, f1, f2, new, f1, ddb, 0, IF_BFP) - F(0xb34d, DXBR, RRE, Z, x2h, x2l, x1, x1, dxb, 0, IF_BFP) + F(0xb34d, DXBR, RRE, Z, x1, x2, new_x, x1, dxb, 0, IF_BFP) F(0xed0d, DEB, RXE, Z, e1, m2_32u, new, e1, deb, 0, IF_BFP) F(0xed1d, DDB, RXE, Z, f1, m2_64, new, f1, ddb, 0, IF_BFP) /* DIVIDE LOGICAL */ @@ -597,7 +597,7 @@ /* LOAD FP INTEGER */ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP) F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP) - F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_x, x1, fixb, 0, IF_BFP) + F(0xb347, FIXBR, RRF_e, Z, 0, x2, new_x, x1, fixb, 0, IF_BFP) =20 /* LOAD LENGTHENED */ F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP) @@ -610,8 +610,8 @@ F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1) /* LOAD ROUNDED */ F(0xb344, LEDBR, RRF_e, Z, 0, f2, new, e1, ledb, 0, IF_BFP) - F(0xb345, LDXBR, RRF_e, Z, x2h, x2l, new, f1, ldxb, 0, IF_BFP) - F(0xb346, LEXBR, RRF_e, Z, x2h, x2l, new, e1, lexb, 0, IF_BFP) + F(0xb345, LDXBR, RRF_e, Z, 0, x2, new, f1, ldxb, 0, IF_BFP) + F(0xb346, LEXBR, RRF_e, Z, 0, x2, new, e1, lexb, 0, IF_BFP) =20 /* LOAD MULTIPLE */ C(0x9800, LM, RS_a, Z, 0, a2, 0, 0, lm32, 0) @@ -666,7 +666,7 @@ C(0xe384, MG, RXY_a, MIE2,r1p1_o, m2_64, r1_P, 0, muls128, 0) F(0xb317, MEEBR, RRE, Z, e1, e2, new, e1, meeb, 0, IF_BFP) F(0xb31c, MDBR, RRE, Z, f1, f2, new, f1, mdb, 0, IF_BFP) - F(0xb34c, MXBR, RRE, Z, x2h, x2l, x1, x1, mxb, 0, IF_BFP) + F(0xb34c, MXBR, RRE, Z, x1, x2, new_x, x1, mxb, 0, IF_BFP) F(0xb30c, MDEBR, RRE, Z, f1, e2, new, f1, mdeb, 0, IF_BFP) F(0xb307, MXDBR, RRE, Z, 0, f2, x1, x1, mxdb, 0, IF_BFP) F(0xed17, MEEB, RXE, Z, e1, m2_32u, new, e1, meeb, 0, IF_BFP) @@ -835,7 +835,7 @@ /* SQUARE ROOT */ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP) F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP) - F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_x, x1, sqxb, 0, IF_BFP) + F(0xb316, SQXBR, RRE, Z, 0, x2, new_x, x1, sqxb, 0, IF_BFP) F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP) F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) =20 @@ -913,7 +913,7 @@ C(0xe319, SGF, RXY_a, Z, r1, m2_32s, r1, 0, sub, subs64) F(0xb30b, SEBR, RRE, Z, e1, e2, new, e1, seb, f32, IF_BFP) F(0xb31b, SDBR, RRE, Z, f1, f2, new, f1, sdb, f64, IF_BFP) - F(0xb34b, SXBR, RRE, Z, x2h, x2l, x1, x1, sxb, f128, IF_BFP) + F(0xb34b, SXBR, RRE, Z, x1, x2, new_x, x1, sxb, f128, IF_BFP) F(0xed0b, SEB, RXE, Z, e1, m2_32u, new, e1, seb, f32, IF_BFP) F(0xed1b, SDB, RXE, Z, f1, m2_64, new, f1, sdb, f64, IF_BFP) /* SUBTRACT HALFWORD */ @@ -957,7 +957,7 @@ /* TEST DATA CLASS */ F(0xed10, TCEB, RXE, Z, e1, a2, 0, 0, tceb, 0, IF_BFP) F(0xed11, TCDB, RXE, Z, f1, a2, 0, 0, tcdb, 0, IF_BFP) - F(0xed12, TCXB, RXE, Z, 0, a2, x1, 0, tcxb, 0, IF_BFP) + F(0xed12, TCXB, RXE, Z, x1, a2, 0, 0, tcxb, 0, IF_BFP) =20 /* TEST DECIMAL */ C(0xebc0, TP, RSL, E2, la1, 0, 0, 0, tp, 0) diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 13be44499b..0bdab5bcf7 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -39,6 +39,11 @@ static inline Int128 RET128(float128 f) return int128_make128(f.low, f.high); } =20 +static inline float128 ARG128(Int128 i) +{ + return make_float128(int128_gethi(i), int128_getlo(i)); +} + uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) { uint8_t s390_exc =3D 0; @@ -227,12 +232,9 @@ uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP addition */ -Int128 HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(axb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_add(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_add(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -254,12 +256,9 @@ uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP subtraction */ -Int128 HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(sxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_sub(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_sub(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -281,12 +280,9 @@ uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP division */ -Int128 HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(dxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_div(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_div(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -317,21 +313,18 @@ uint64_t HELPER(mdeb)(CPUS390XState *env, uint64_t f1= , uint64_t f2) } =20 /* 128-bit FP multiplication */ -Int128 HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(mxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_mul(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_mul(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } =20 /* 128/64-bit FP multiplication */ -Int128 HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t= f2) +Int128 HELPER(mxdb)(CPUS390XState *env, Int128 a, uint64_t f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); - ret =3D float128_mul(make_float128(ah, al), ret, &env->fpu_status); + ret =3D float128_mul(ARG128(a), ret, &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -345,11 +338,10 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) } =20 /* convert 128-bit float to 64-bit float */ -uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +uint64_t HELPER(ldxb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float64 ret =3D float128_to_float64(make_float128(ah, al), &env->fpu_s= tatus); + float64 ret =3D float128_to_float64(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -384,11 +376,10 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2= , uint32_t m34) } =20 /* convert 128-bit float to 32-bit float */ -uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +uint64_t HELPER(lexb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float32 ret =3D float128_to_float32(make_float128(ah, al), &env->fpu_s= tatus); + float32 ret =3D float128_to_float32(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -412,11 +403,9 @@ uint32_t HELPER(cdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP compare */ -uint32_t HELPER(cxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +uint32_t HELPER(cxb)(CPUS390XState *env, Int128 a, Int128 b) { - FloatRelation cmp =3D float128_compare_quiet(make_float128(ah, al), - make_float128(bh, bl), + FloatRelation cmp =3D float128_compare_quiet(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return float_comp_to_cc(env, cmp); @@ -564,10 +553,10 @@ uint64_t HELPER(cgdb)(CPUS390XState *env, uint64_t v2= , uint32_t m34) } =20 /* convert 128-bit float to 64-bit int */ -uint64_t HELPER(cgxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t= m34) +uint64_t HELPER(cgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); int64_t ret =3D float128_to_int64(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -613,10 +602,10 @@ uint64_t HELPER(cfdb)(CPUS390XState *env, uint64_t v2= , uint32_t m34) } =20 /* convert 128-bit float to 32-bit int */ -uint64_t HELPER(cfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t= m34) +uint64_t HELPER(cfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); int32_t ret =3D float128_to_int32(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -662,10 +651,10 @@ uint64_t HELPER(clgdb)(CPUS390XState *env, uint64_t v= 2, uint32_t m34) } =20 /* convert 128-bit float to 64-bit uint */ -uint64_t HELPER(clgxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_= t m34) +uint64_t HELPER(clgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); uint64_t ret =3D float128_to_uint64(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -711,10 +700,10 @@ uint64_t HELPER(clfdb)(CPUS390XState *env, uint64_t v= 2, uint32_t m34) } =20 /* convert 128-bit float to 32-bit uint */ -uint64_t HELPER(clfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_= t m34) +uint64_t HELPER(clfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); uint32_t ret =3D float128_to_uint32(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -750,11 +739,10 @@ uint64_t HELPER(fidb)(CPUS390XState *env, uint64_t f2= , uint32_t m34) } =20 /* round to integer 128-bit */ -Int128 HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t= m34) +Int128 HELPER(fixb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 ret =3D float128_round_to_int(make_float128(ah, al), - &env->fpu_status); + float128 ret =3D float128_round_to_int(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -778,11 +766,9 @@ uint32_t HELPER(kdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP compare and signal */ -uint32_t HELPER(kxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +uint32_t HELPER(kxb)(CPUS390XState *env, Int128 a, Int128 b) { - FloatRelation cmp =3D float128_compare(make_float128(ah, al), - make_float128(bh, bl), + FloatRelation cmp =3D float128_compare(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return float_comp_to_cc(env, cmp); @@ -869,9 +855,9 @@ uint32_t HELPER(tcdb)(CPUS390XState *env, uint64_t v1, = uint64_t m2) } =20 /* test data class 128-bit */ -uint32_t HELPER(tcxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64= _t m2) +uint32_t HELPER(tcxb)(CPUS390XState *env, Int128 a, uint64_t m2) { - return (m2 & float128_dcmask(env, make_float128(ah, al))) !=3D 0; + return (m2 & float128_dcmask(env, ARG128(a))) !=3D 0; } =20 /* square root 32-bit */ @@ -891,9 +877,9 @@ uint64_t HELPER(sqdb)(CPUS390XState *env, uint64_t f2) } =20 /* square root 128-bit */ -Int128 HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) +Int128 HELPER(sqxb)(CPUS390XState *env, Int128 a) { - float128 ret =3D float128_sqrt(make_float128(ah, al), &env->fpu_status= ); + float128 ret =3D float128_sqrt(ARG128(a), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0a750a5467..d422a1e62b 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -305,6 +305,18 @@ static TCGv_i64 load_freg32_i64(int reg) return r; } =20 +static TCGv_i128 load_freg_128(int reg) +{ + TCGv_i64 h =3D load_freg(reg); + TCGv_i64 l =3D load_freg(reg + 2); + TCGv_i128 r =3D tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(r, l, h); + tcg_temp_free_i64(h); + tcg_temp_free_i64(l); + return r; +} + static void store_reg(int reg, TCGv_i64 v) { tcg_gen_mov_i64(regs[reg], v); @@ -1103,7 +1115,7 @@ typedef struct { bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; - TCGv_i128 out_128; + TCGv_i128 out_128, in1_128, in2_128; } DisasOps; =20 /* Instructions can place constraints on their operands, raising specifica= tion @@ -1462,7 +1474,7 @@ static DisasJumpType op_adb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_axb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -1778,7 +1790,7 @@ static DisasJumpType op_cdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_cxb(DisasContext *s, DisasOps *o) { - gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_cxb(cc_op, cpu_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -1841,7 +1853,7 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_cfxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1880,7 +1892,7 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_cgxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1919,7 +1931,7 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_clfxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1958,7 +1970,7 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_clgxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -2445,7 +2457,7 @@ static DisasJumpType op_ddb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_dxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -2550,7 +2562,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out_128, cpu_env, o->in1, o->in2, m34); + gen_helper_fixb(o->out_128, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2769,7 +2781,7 @@ static DisasJumpType op_kdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_kxb(DisasContext *s, DisasOps *o) { - gen_helper_kxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_kxb(cc_op, cpu_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -2843,7 +2855,7 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_ldxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2855,7 +2867,7 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_lexb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_lexb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -3584,13 +3596,13 @@ static DisasJumpType op_mdb(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_mxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out_128, cpu_env, o->out, o->out2, o->in2); + gen_helper_mxdb(o->out_128, cpu_env, o->in1_128, o->in2); return DISAS_NEXT; } =20 @@ -4055,7 +4067,7 @@ static DisasJumpType op_sdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_sxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -4073,7 +4085,7 @@ static DisasJumpType op_sqdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out_128, cpu_env, o->in1, o->in2); + gen_helper_sqxb(o->out_128, cpu_env, o->in2_128); return DISAS_NEXT; } =20 @@ -4852,7 +4864,7 @@ static DisasJumpType op_tcdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o) { - gen_helper_tcxb(cc_op, cpu_env, o->out, o->out2, o->in2); + gen_helper_tcxb(cc_op, cpu_env, o->in1_128, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -5387,8 +5399,6 @@ static void prep_new_P(DisasContext *s, DisasOps *o) =20 static void prep_new_x(DisasContext *s, DisasOps *o) { - o->out =3D tcg_temp_new_i64(); - o->out2 =3D tcg_temp_new_i64(); o->out_128 =3D tcg_temp_new_i128(); } #define SPEC_prep_new_x 0 @@ -5411,10 +5421,7 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) =20 static void prep_x1(DisasContext *s, DisasOps *o) { - o->out =3D load_freg(get_field(s, r1)); - o->out2 =3D load_freg(get_field(s, r1) + 2); - o->out_128 =3D tcg_temp_new_i128(); - tcg_gen_concat_i64_i128(o->out_128, o->out2, o->out); + o->out_128 =3D load_freg_128(get_field(s, r1)); } #define SPEC_prep_x1 SPEC_r1_f128 =20 @@ -5513,6 +5520,11 @@ static void wout_x1(DisasContext *s, DisasOps *o) { int f1 =3D get_field(s, r1); =20 + /* Split out_128 into out+out2 for cout_f128. */ + tcg_debug_assert(o->out =3D=3D NULL); + o->out =3D tcg_temp_new_i64(); + o->out2 =3D tcg_temp_new_i64(); + tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); store_freg(f1, o->out); store_freg(f1 + 2, o->out2); @@ -5755,6 +5767,12 @@ static void in1_f1(DisasContext *s, DisasOps *o) } #define SPEC_in1_f1 0 =20 +static void in1_x1(DisasContext *s, DisasOps *o) +{ + o->in1_128 =3D load_freg_128(get_field(s, r1)); +} +#define SPEC_in1_x1 SPEC_r1_f128 + /* Load the high double word of an extended (128-bit) format FP number */ static void in1_x2h(DisasContext *s, DisasOps *o) { @@ -5964,6 +5982,12 @@ static void in2_f2(DisasContext *s, DisasOps *o) } #define SPEC_in2_f2 0 =20 +static void in2_x2(DisasContext *s, DisasOps *o) +{ + o->in2_128 =3D load_freg_128(get_field(s, r2)); +} +#define SPEC_in2_x2 SPEC_r2_f128 + /* Load the low double word of an extended (128-bit) format FP number */ static void in2_x2l(DisasContext *s, DisasOps *o) { @@ -6592,6 +6616,12 @@ static DisasJumpType translate_one(CPUS390XState *en= v, DisasContext *s) if (o.out_128) { tcg_temp_free_i128(o.out_128); } + if (o.in1_128) { + tcg_temp_free_i128(o.in1_128); + } + if (o.in2_128) { + tcg_temp_free_i128(o.in2_128); + } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret =3D=3D DISAS_NEXT)) { ret =3D DISAS_TOO_MANY; --=20 2.34.1 From nobody Fri May 3 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115533163100004 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Acked-by: Ilya Leoshkevich --- Cc: David Hildenbrand Cc: Ilya Leoshkevich --- target/s390x/helper.h | 2 -- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/mem_helper.c | 52 ------------------------------ target/s390x/tcg/translate.c | 55 +++++++++++++++++++------------- 4 files changed, 33 insertions(+), 78 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bccd3bfca6..341bc51ec2 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -35,8 +35,6 @@ DEF_HELPER_3(cxgb, i128, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i128, env, i64, i32) -DEF_HELPER_4(cdsg, void, env, i64, i32, i32) -DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 893f4b48db..9d2d35f084 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -276,7 +276,7 @@ /* COMPARE DOUBLE AND SWAP */ D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEUQ) D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEUQ) - C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0) + C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, 0, r1_D64, cdsg, 0) /* COMPARE AND SWAP AND STORE */ C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) =20 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 49969abda7..d6725fd18c 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1771,58 +1771,6 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r= 1, uint32_t r2, return cc; } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - uintptr_t ra =3D GETPC(); - Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); - Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); - Int128 oldv; - uint64_t oldh, oldl; - bool fail; - - check_alignment(env, addr, 16, ra); - - oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); - oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); - - oldv =3D int128_make128(oldl, oldh); - fail =3D !int128_eq(oldv, cmpv); - if (fail) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); - cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); - - env->cc_op =3D fail; - env->regs[r1] =3D int128_gethi(oldv); - env->regs[r1 + 1] =3D int128_getlo(oldv); -} - -void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - uintptr_t ra =3D GETPC(); - Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); - Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); - int mem_idx; - MemOpIdx oi; - Int128 oldv; - bool fail; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - fail =3D !int128_eq(oldv, cmpv); - - env->cc_op =3D fail; - env->regs[r1] =3D int128_gethi(oldv); - env->regs[r1 + 1] =3D int128_getlo(oldv); -} - static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d422a1e62b..9ea28b3e52 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2224,31 +2224,25 @@ static DisasJumpType op_cs(DisasContext *s, DisasOp= s *o) static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) { int r1 =3D get_field(s, r1); - int r3 =3D get_field(s, r3); - int d2 =3D get_field(s, d2); - int b2 =3D get_field(s, b2); - DisasJumpType ret =3D DISAS_NEXT; - TCGv_i64 addr; - TCGv_i32 t_r1, t_r3; =20 - /* Note that R1:R1+1 =3D expected value and R3:R3+1 =3D new value. */ - addr =3D get_address(s, 0, b2, d2); - t_r1 =3D tcg_const_i32(r1); - t_r3 =3D tcg_const_i32(r3); - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); - } else if (HAVE_CMPXCHG128) { - gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); - } else { - gen_helper_exit_atomic(cpu_env); - ret =3D DISAS_NORETURN; - } - tcg_temp_free_i64(addr); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r3); + o->out_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->out_128, regs[r1 + 1], regs[r1]); =20 - set_cc_static(s); - return ret; + /* Note out (R1:R1+1) =3D expected value and in2 (R3:R3+1) =3D new val= ue. */ + tcg_gen_atomic_cmpxchg_i128(o->out_128, o->addr1, o->out_128, o->in2_1= 28, + get_mem_index(s), MO_BE | MO_128 | MO_ALIG= N); + + /* + * Extract result into cc_dst:cc_src, compare vs the expected value + * in the as yet unmodified input registers, then update CC_OP. + */ + tcg_gen_extr_i128_i64(cc_src, cc_dst, o->out_128); + tcg_gen_xor_i64(cc_dst, cc_dst, regs[r1]); + tcg_gen_xor_i64(cc_src, cc_src, regs[r1 + 1]); + tcg_gen_or_i64(cc_dst, cc_dst, cc_src); + set_cc_nz_u64(s, cc_dst); + + return DISAS_NEXT; } =20 static DisasJumpType op_csst(DisasContext *s, DisasOps *o) @@ -5488,6 +5482,13 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o) } #define SPEC_wout_r1_D32 SPEC_r1_even =20 +static void wout_r1_D64(DisasContext *s, DisasOps *o) +{ + int r1 =3D get_field(s, r1); + tcg_gen_extr_i128_i64(regs[r1 + 1], regs[r1], o->out_128); +} +#define SPEC_wout_r1_D64 SPEC_r1_even + static void wout_r3_P32(DisasContext *s, DisasOps *o) { int r3 =3D get_field(s, r3); @@ -5935,6 +5936,14 @@ static void in2_r3(DisasContext *s, DisasOps *o) } #define SPEC_in2_r3 0 =20 +static void in2_r3_D64(DisasContext *s, DisasOps *o) +{ + int r3 =3D get_field(s, r3); + o->in2_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->in2_128, regs[r3 + 1], regs[r3]); +} +#define SPEC_in2_r3_D64 SPEC_r3_even + static void in2_r3_sr32(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eNQ5cD41iWDDXrL/VUUAl3ccQjSxU/V7M1eUUGdE6wQ=; b=PELM8eSXwPeo0BVnsx2xPzvRG4ZmCLLqMpKKlXVpHGosdozFp0ZQheqzCJtxquG24H ItzCBraytg5ADp8JlHlMVbke2ogd4ECE+rT8bmm7wOJYHpw2h7ER4SMm3ERw7DwQb7lW 5An4S1dRa7jN02I52fpEXr/8JVftWQOGab8ywxxolkJHW0LYBczjjt3O2fqZ1PQU8bjU ncZsSUcnbEI2qp24bs4VeXaa06ArSVcTodipQFe2F4w4MyUHItPdQiZOH+YLez60ePGt oD4Op1jW/PQD0jpTCT/xj93Hi10Exleae/P70MUs8fwLV9ZhF+0kGtJLlkIdPumQKzEB XBtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eNQ5cD41iWDDXrL/VUUAl3ccQjSxU/V7M1eUUGdE6wQ=; b=i4T2zdvW93z09qrHZU7kPVm6Xl0F70+ulM2KwWLzTotzUB443dTTDxEuxumV5Uv8lb 7EpfiwsjAZj8zQZ374oeYtvD8+lGlZY4Rr0UyEgaklS4Jb22mklPqmsb9nVIwByTi/c3 BRL3XNP3WrYHHI9Ph/GFmalMYfzQ+HEJ5cdgVCnreJqosuWOc9El4+gSIN+OyM7cx9t4 TmCs8ztP3vYetZslYd9e2+f7yeaMoyPB+hFfcnlOtqArngVOnqEuVewOdoUrLtyQiWF2 WJL1RWODYSHa+CYwtGnQ3wEfkK1wcdXKO8Epq7Ksvs8EGgHmjf64nyYrjrw08hysxDuV ittA== X-Gm-Message-State: AO0yUKVm7CgqvGwXXt1U8K/5eKrTn2TtIDUEgF2dJmOTnMUliOT4YXjP h/+s9FRjrr6SyuKdqL2ubZeS7KfdS7S2zrU6 X-Google-Smtp-Source: AK7set/KkflpZYSTuQ5NzDLoJ/fOmND9BXl4fME85ePZkUFngGG8xVyWwKh+aB/qmKtvsu/OC74VtQ== X-Received: by 2002:a17:90b:3ec3:b0:22c:1920:27e5 with SMTP id rm3-20020a17090b3ec300b0022c192027e5mr11015951pjb.41.1675115382179; Mon, 30 Jan 2023 13:49:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, David Hildenbrand Subject: [PATCH v6 33/36] target/s390x: Implement CC_OP_NZ in gen_op_calc_cc Date: Mon, 30 Jan 2023 11:48:41 -1000 Message-Id: <20230130214844.1158612-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115651673100001 Content-Type: text/plain; charset="utf-8" This case is trivial to implement inline. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 9ea28b3e52..ac5bd98f04 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -625,6 +625,9 @@ static void gen_op_calc_cc(DisasContext *s) /* env->cc_op already is the cc value */ break; case CC_OP_NZ: + tcg_gen_setcondi_i64(TCG_COND_NE, cc_dst, cc_dst, 0); + tcg_gen_extrl_i64_i32(cc_op, cc_dst); + break; case CC_OP_ABS_64: case CC_OP_NABS_64: case CC_OP_ABS_32: --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115504; cv=none; d=zohomail.com; s=zohoarc; b=R0Zb/BehcMTe7/RAF336RUKZJRb9gJHZEXRM41xYpZth02jkK11YPTN2yS5AgwYn1h/Fo2zVP/moXx/8ls/EkrYn4/Mrwxp8S9o5Y6ZYK02dZpNBfWCG4NhAptLgRAvGlF08ZrUwn9x6dlyBhkd1RegUtUY0Q8XXleuS3teCjZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115504; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x14oGfCPbXFzwT0sz8fdoRC+6dXXFQJCDg5CcaWYsZ8=; b=ZqlEU41XrvthLBgNLr490Y9ICa47IBmDDi0p9JL9/jMJe7I/xCr5WFZuldsqFV/+yavI/nnwAzQo4O38OgOxpE1wOkvc/MI8iaboSplT2HwWHsJscTXgyw17upsJ80Ghmi9l512oT/ltQFigvx33sZ/NfoFo016VehG4ABGGZrc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115504186820.2112361541588; Mon, 30 Jan 2023 13:51:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc2J-0003Jk-Pl; Mon, 30 Jan 2023 16:49:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc26-0002q9-IJ for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:47 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc24-0005cc-U7 for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:46 -0500 Received: by mail-pj1-x1031.google.com with SMTP id rm7-20020a17090b3ec700b0022c05558d22so12468953pjb.5 for ; Mon, 30 Jan 2023 13:49:44 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x14oGfCPbXFzwT0sz8fdoRC+6dXXFQJCDg5CcaWYsZ8=; b=zI8QpcsyBgSEN+XLJBZuEoVC6G2RGExDsM5M4NoBc+Has29f1BuJCPUExgpNxpzunr Nl7l/bkLYOnUSSIaZJV3aUfqf3KrzoES0yw4XbGqrKckNudus+ihZglaVl3JovujtgTY Z6vAMKZVZMpmk/yzcjzKCeKlAYJ/MF4o64BfTQmcGcUkw1KxuPCnYCD4gWbWN6NLzH4j 4Tcb+mSutilCszNDaGJ5eGUd6csMcVJQTNvNpJMZyibdMa+n6f4Y2/MYy/rYy23V5QiW S62rSusybXEaS3EKmuH7ozAPq/D73pAcHcpl+m7tpyBDqKmofQIpdb+ysJeNfNfZyOpV 1R4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x14oGfCPbXFzwT0sz8fdoRC+6dXXFQJCDg5CcaWYsZ8=; b=BgyJck8jrQlPTB46OofL14IxNc1arXtolZpXb9r4OElcEw+G2O4gsf8YIRHS+k6ySZ UyFd3GZ+rUKbG5rEvhUentDvut0nFMc6cGNwyc4HvjQSKRvoK/U3IrxRJb5zdfW9A++A zOiOi/p6mOgxAcL3HgA7hbUKcBYYz9g0ON2pWRPo2iy2LFEf+TeyZkN0bg6D7IBB7qFh Mu6lhC1oDHDkM66PY6TY6FOGlc0xeNTqyUWbcykx1r/soCnFm62Zqu0IlmqNiAIEqc06 B4dmPALa/cMR5hhSx7ngu/OdDYF0Btmt0+8DaSVhqnRcZXm0pp6/s1ILgdt+2IZ0U+Ai BEFA== X-Gm-Message-State: AO0yUKVWChCIkYTtx2wQxvj2meceY75B3Blc6ULfR4mxMxyx9tpEk5JA bRyTkC1xsf/pRNUxFBRBwv+6lwzkv5FLSASs X-Google-Smtp-Source: AK7set/pa2IimDSlzNwUSMTaWVt928eu9m9JwVnZE0SgfFazTPcoc9aQuIE3EvT3LPBgXcCRKOe23w== X-Received: by 2002:a05:6a21:3384:b0:bc:caea:6cb8 with SMTP id yy4-20020a056a21338400b000bccaea6cb8mr9553760pzb.8.1675115384115; Mon, 30 Jan 2023 13:49:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 34/36] target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b Date: Mon, 30 Jan 2023 11:48:42 -1000 Message-Id: <20230130214844.1158612-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115505002100005 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 48 ++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7e0b2a709a..a82131d635 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2993,6 +2993,34 @@ static void gen_sty_env_A0(DisasContext *s, int offs= et, bool align) #include "emit.c.inc" #include "decode-new.c.inc" =20 +static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg8b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} + +#ifdef TARGET_X86_64 +static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg16b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} +#endif + /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static bool disas_insn(DisasContext *s, CPUState *cpu) @@ -3844,28 +3872,14 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg16b(s, env, modrm); break; } -#endif =20 +#endif if (!(s->cpuid_features & CPUID_CX8)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg8b(s, env, modrm); break; =20 case 7: /* RDSEED */ --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115625; cv=none; d=zohomail.com; s=zohoarc; b=d1cpHCd53PueEeEM3h6ZbltP982B+YgeFXVp2XCk/3yZ9+pFs/z0tRicFdYdfwkez1y6MkfV8OFqoAmmfTTXvqM6vUAK53/lDgxOt7enWRIR1jnRSZ5DPgWRqOdLEF62ylSriu0LLSwgYXaQlFJcp9vM23GR9XaaOGETA4TX0Mc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115625; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ziBn/5+saVd4auHCBHIgshaqj52WwpIAD7oymg6iFS8=; b=A8A+PtVurUaRTOl7wrT6ASJfnuZbBCTZSfwYYa5/dmjJxQYeeluuVWJI5ksG4dbVcGCPfGaMNIl8pvrc9mFq+79ZUoFsVH5i+lpKhUowlboEY01jWjKL25jybUEi/MsliW20f7aqdoYifEs/s+TJm8PPhZ7UVnqrkb6csiZe3WQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115625679186.38003738335374; Mon, 30 Jan 2023 13:53:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc2I-00037o-24; Mon, 30 Jan 2023 16:49:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc28-0002sh-Vq for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:49 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc27-0005kV-6G for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:48 -0500 Received: by mail-pj1-x1035.google.com with SMTP id cq16-20020a17090af99000b0022c9791ac39so4587500pjb.4 for ; Mon, 30 Jan 2023 13:49:46 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ziBn/5+saVd4auHCBHIgshaqj52WwpIAD7oymg6iFS8=; b=OvZwQ4utzR6wtc3CZec2Ac6Xz/EluV4w7fRP49d5nDnruuZGXvkx5ShSoy+KHrUPgX LZaivajKyq5XCRdPNvhCGdx2j2BuI8A0vFdo7QQZ8lVrkTeXxt2Z5CbI/B/BfsPOiHh9 BO6AxQCOs6p5lvmeIR7i07yP8xbS9DeMsgjLQ/6AOYXhOuXV6Hty2OF5a/PaCIQu9Xjf xXs7b1vGg2IrOASNgwYLNEsVvnO2YRd8IUr4gewGs4SGEvY+RwNeb4mwSSMKKEZquba4 yvkxm2MAujKUR9u3/f7GUcEAR+Q9rk5IMqfoBRb2xGuNDSQnTOx5s9SdGTxgTYbm23qZ ocsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ziBn/5+saVd4auHCBHIgshaqj52WwpIAD7oymg6iFS8=; b=ZgyfV0PFK3ggSvsetKBL3K2eWr1dSOag1U8c19ckV/DsihTKWbkOiVRUEiM9wazk1t nlWDyVwWiavfJ7Pl+8ibCiUNeRTDX4GkH9/ytfGsL66egLR4Ka0ZJTwneT1G0tVuUjbB vF1S9ENUoOz16/H4p9jGWXbjpiEbVNfM9zJ05tJYsjTqMwZRYrhZeGc3b9s+hYiUWR3y 6pVXxi1cQPkuDrmxOFU6lcQXvPYXdFZaXSTuPNIDgCbVEJ8PQEJZMBLskjJPsE4NUEGQ 7ge15ORUQnLAvQ9Q5oYExtL8hZwsQPj1UUWserJ8cT/eTW7R5iJ7H6kqAB+Cpf6PIfZP gwRQ== X-Gm-Message-State: AO0yUKVnIaALH+sSg/E9A8s35oC9mb5fFcjP5Wfbv/pZYjnFZY2yYJVA 5f0eeHwPJxrtCH1U/T0kXtnCWR4oKqJ3gRx8 X-Google-Smtp-Source: AK7set87k1krp5YWXPPQc6hE2aOBf6uajz277JpFBf/MhRbXKx9Ent9JWn9DufZag+F6K7XeyHxLdw== X-Received: by 2002:a05:6a20:7f91:b0:bc:a257:5b2a with SMTP id d17-20020a056a207f9100b000bca2575b2amr11362080pzj.31.1675115385949; Mon, 30 Jan 2023 13:49:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, Paolo Bonzini , Eduardo Habkost Subject: [PATCH v6 35/36] target/i386: Inline cmpxchg8b Date: Mon, 30 Jan 2023 11:48:43 -1000 Message-Id: <20230130214844.1158612-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115627675100007 Content-Type: text/plain; charset="utf-8" Use tcg_gen_atomic_cmpxchg_i64 for the atomic case, and tcg_gen_nonatomic_cmpxchg_i64 otherwise. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Paolo Bonzini Cc: Eduardo Habkost --- target/i386/helper.h | 2 -- target/i386/tcg/mem_helper.c | 57 ------------------------------------ target/i386/tcg/translate.c | 54 ++++++++++++++++++++++++++++++---- 3 files changed, 49 insertions(+), 64 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index b7de5429ef..2df8049f91 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,8 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ =20 DEF_HELPER_2(into, void, env, int) -DEF_HELPER_2(cmpxchg8b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg8b, void, env, tl) #ifdef TARGET_X86_64 DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index e3cdafd2d4..814786bb87 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,63 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" =20 -void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - uint64_t oldv, cmpv, newv; - int eflags; - - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - oldv =3D cpu_ldq_data_ra(env, a0, ra); - newv =3D (cmpv =3D=3D oldv ? newv : oldv); - /* always do the store */ - cpu_stq_data_ra(env, a0, newv, ra); - - if (oldv =3D=3D cmpv) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D (uint32_t)oldv; - env->regs[R_EDX] =3D (uint32_t)(oldv >> 32); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -} - -void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) -{ -#ifdef CONFIG_ATOMIC64 - uint64_t oldv, cmpv, newv; - int eflags; - - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - { - uintptr_t ra =3D GETPC(); - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mem_idx); - oldv =3D cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra); - } - - if (oldv =3D=3D cmpv) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D (uint32_t)oldv; - env->regs[R_EDX] =3D (uint32_t)(oldv >> 32); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -#else - cpu_loop_exit_atomic(env_cpu(env), GETPC()); -#endif /* CONFIG_ATOMIC64 */ -} - #ifdef TARGET_X86_64 void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a82131d635..b542b084a6 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2995,15 +2995,59 @@ static void gen_sty_env_A0(DisasContext *s, int off= set, bool align) =20 static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) { + TCGv_i64 cmp, val, old; + TCGv Z; + gen_lea_modrm(env, s, modrm); =20 - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); + cmp =3D tcg_temp_new_i64(); + val =3D tcg_temp_new_i64(); + old =3D tcg_temp_new_i64(); + + /* Construct the comparison values from the register pair. */ + tcg_gen_concat_tl_i64(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_tl_i64(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_= TEUQ); } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, + s->mem_index, MO_TEUQ); } - set_cc_op(s, CC_OP_EFLAGS); + tcg_temp_free_i64(val); + + /* Set tmp0 to match the required value of Z. */ + tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); + Z =3D tcg_temp_new(); + tcg_gen_trunc_i64_tl(Z, cmp); + tcg_temp_free_i64(cmp); + + /* + * Extract the result values for the register pair. + * For 32-bit, we may do this unconditionally, because on success (Z= =3D1), + * the old value matches the previous value in EDX:EAX. For x86_64, + * the store must be conditional, because we must leave the source + * registers unchanged on success, and zero-extend the writeback + * on failure (Z=3D0). + */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], old); + } else { + TCGv zero =3D tcg_constant_tl(0); + + tcg_gen_extr_i64_tl(s->T0, s->T1, old); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EAX], Z, zero, + s->T0, cpu_regs[R_EAX]); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, + s->T1, cpu_regs[R_EDX]); + } + tcg_temp_free_i64(old); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); + tcg_temp_free(Z); } =20 #ifdef TARGET_X86_64 --=20 2.34.1 From nobody Fri May 3 12:16:48 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675115637; cv=none; d=zohomail.com; s=zohoarc; b=EXb4VMI9Z/HZDVeY1fLrkZGsiITMXo4SpFsTfxfCXtRQaa6Wmp3OD5J4CC7Ps8Oqlem4mWIc7MgYBJUPePWuK+lPJigyFtn0YVWflRFsDEM5PS13PjQESMVNUhEOJIRptjpQs3Om5h4ehDwc/Ma/2TSOyawP+aDz90LCzds2VdI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675115637; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/wjq7xXevU0mmvHUtmHWv2FofdJ4SksIwuVkJSWY5CU=; b=K5SJ5A5fHLTx5m6W1cWq8Hcq7PqOVvw4//iFAegHRj2oNsh3SP/1tuzQ2tkFxUsGsqpQjVp4ScHPjffSX7T9POFyzKjp/kp7kwA15Mye8oQZvMjmQCTYMDO9QrN6qtjNUjuLL3elx+tWy88o3qUXenf6ZU2ljdTmVgIppFKWWjY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675115637533650.6133298514405; Mon, 30 Jan 2023 13:53:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMc2I-0003E5-Ev; Mon, 30 Jan 2023 16:49:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMc2A-0002uT-Hh for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:53 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMc28-0005hE-Nx for qemu-devel@nongnu.org; Mon, 30 Jan 2023 16:49:50 -0500 Received: by mail-pj1-x1033.google.com with SMTP id n20-20020a17090aab9400b00229ca6a4636so17013920pjq.0 for ; Mon, 30 Jan 2023 13:49:48 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/wjq7xXevU0mmvHUtmHWv2FofdJ4SksIwuVkJSWY5CU=; b=EmGqFaLK+m2ZIbjShyB5bzuBWLJg9OCLg9PmRp75SkKMIGF6xvmq+Mz7ytOEC0nT+X RNoCpCRH131HauQXRRJmrXe+2jy3ira3RMqXdDs2XRwFpAYzv7Um1kpwqUlglFOOeO1t 8FqMY1M6XTQ9ZWg4Wg9rqq1Fg4VCNGr/jMdvRp8es1NY+jOT6LEJnQITYQB2Ls0+Hrqs uX3h4uZ1ilVoGmkg9h2waqE8F0bQCgnH2pCG5V0g+IWhsxWGm+LfY8HDnE8M26OgAtAo L8V/51dUwyGcwvJ/hSSvMeTftq0ih2bcBS8Wk6YWnkIPMxSfPXGZnfV8iwZDTwKumvpG tipw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/wjq7xXevU0mmvHUtmHWv2FofdJ4SksIwuVkJSWY5CU=; b=D9Ldip4ZxLPQ95jTUXaa9nzVq4L1NbatHp2sM4BK/AM0p+MBxXr2w4l1tAZlRzjO8g urEqUYpKIyQnTu9jzqwezCccFICC3pY/e2yJm66k27BUDxZ7emp74OdeNl4kW82WWzvn xrpES2+uBzB/Ya+4KMK7U4hEJ+tKFEhtZLknKa6jcBB+iK8YBQA+1R+ZXbN3iwU7QZY8 aRRKv7NM8sA3tiw4O1x5z1RSTWvjI6ESPCIkqDXQjDJBudl8FXVX87+s8kdKXuaa30r1 2cTc2JKq1k97te2Qhxo08Qyy2Uo11HiQk/KHwWCcZdcqy8h9aDzUa/SBumh11DXoutzU CwQw== X-Gm-Message-State: AO0yUKXL8jPscuaRXZCtzr9uef0EWVNyIH79qEAWFkFUl5w/QWmkEuOs 5noue0zOI1i9hWEbr6z5u9ZJ9QFS5WAvv8nD X-Google-Smtp-Source: AK7set+qAGnxQ7iHnKCweJjQsmixTRFl5JeEG6xcE2Kyvfp2ZEy2EgCVuPNAY3zM8rvGEodgnTTnFw== X-Received: by 2002:a17:90b:4d88:b0:229:f0c7:487d with SMTP id oj8-20020a17090b4d8800b00229f0c7487dmr10656332pjb.2.1675115387784; Mon, 30 Jan 2023 13:49:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, Paolo Bonzini , Eduardo Habkost Subject: [PATCH v6 36/36] target/i386: Inline cmpxchg16b Date: Mon, 30 Jan 2023 11:48:44 -1000 Message-Id: <20230130214844.1158612-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115639631100006 Content-Type: text/plain; charset="utf-8" Use tcg_gen_atomic_cmpxchg_i128 for the atomic case, and tcg_gen_qemu_ld/st_i128 otherwise. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Paolo Bonzini Cc: Eduardo Habkost --- target/i386/helper.h | 4 --- target/i386/tcg/mem_helper.c | 69 ------------------------------------ target/i386/tcg/translate.c | 44 ++++++++++++++++++++--- 3 files changed, 39 insertions(+), 78 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 2df8049f91..e627a93107 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,10 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ =20 DEF_HELPER_2(into, void, env, int) -#ifdef TARGET_X86_64 -DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg16b, void, env, tl) -#endif DEF_HELPER_FLAGS_1(single_step, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rechecking_single_step, void, env) DEF_HELPER_1(cpuid, void, env) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 814786bb87..3ef84e90d9 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,75 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" =20 -#ifdef TARGET_X86_64 -void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - Int128 oldv, cmpv, newv; - uint64_t o0, o1; - int eflags; - bool success; - - if ((a0 & 0xf) !=3D 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - o0 =3D cpu_ldq_data_ra(env, a0 + 0, ra); - o1 =3D cpu_ldq_data_ra(env, a0 + 8, ra); - - oldv =3D int128_make128(o0, o1); - success =3D int128_eq(oldv, cmpv); - if (!success) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, a0 + 0, int128_getlo(newv), ra); - cpu_stq_data_ra(env, a0 + 8, int128_gethi(newv), ra); - - if (success) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D int128_getlo(oldv); - env->regs[R_EDX] =3D int128_gethi(oldv); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -} - -void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - - if ((a0 & 0xf) !=3D 0) { - raise_exception_ra(env, EXCP0D_GPF, ra); - } else if (HAVE_CMPXCHG128) { - int eflags =3D cpu_cc_compute_all(env, CC_OP); - - Int128 cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - Int128 newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - Int128 oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi= , ra); - - if (int128_eq(oldv, cmpv)) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D int128_getlo(oldv); - env->regs[R_EDX] =3D int128_gethi(oldv); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; - } else { - cpu_loop_exit_atomic(env_cpu(env), ra); - } -} -#endif - void helper_boundw(CPUX86State *env, target_ulong a0, int v) { int low, high; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b542b084a6..9d9392b009 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3053,15 +3053,49 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) #ifdef TARGET_X86_64 static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) { + MemOp mop =3D MO_TE | MO_128 | MO_ALIGN; + TCGv_i64 t0, t1; + TCGv_i128 cmp, val; + gen_lea_modrm(env, s, modrm); =20 - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); + cmp =3D tcg_temp_new_i128(); + val =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_i64_i128(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mo= p); } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index,= mop); } - set_cc_op(s, CC_OP_EFLAGS); + + tcg_gen_extr_i128_i64(s->T0, s->T1, val); + tcg_temp_free_i128(cmp); + tcg_temp_free_i128(val); + + /* Determine success after the fact. */ + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); + tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); + tcg_gen_or_i64(t0, t0, t1); + tcg_temp_free_i64(t1); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); + tcg_temp_free_i64(t0); + + /* + * Extract the result values for the register pair. We may do this + * unconditionally, because on success (Z=3D1), the old value matches + * the previous value in RDX:RAX. + */ + tcg_gen_mov_i64(cpu_regs[R_EAX], s->T0); + tcg_gen_mov_i64(cpu_regs[R_EDX], s->T1); } #endif =20 --=20 2.34.1