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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id m3-20020a056000180300b002755e301eeasm14834867wrh.100.2023.01.31.05.40.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:40:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Pu4CS8ZEwxyDoWSGcKVuwnDbAFzTS1eeQ8iquNKhHg=; b=ORjbnK8Q11fqZXsO26ntc5ZgkDSIIwe8ZSTOFy6jVASD2/vxW+i1nUf2bO/MW5fTo+ JO/HUaBgSTYCy4NoftoQj2C8a3rjLpFu+UVjq/S6P/gMM0AJROwewwJcbguB1wuufJVo KsueWgMjv8ihRupFtln5VKuOTE2V4z3DroVGSmAUslFznaJSysF6E3rDKdv/koDwk2py GPJ0hxe7Bc5mBvqkfW8lHpUBXIEBQJMP6IBCwmECXKoFTV8GxY4txo1BH6us/9f7ynEN e5HDbSqKDrvXEz+A4818Sh95wGkcXR9DisksV2jn1QyIVYRL/41zsFiffQyunezRv7ff vuSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Pu4CS8ZEwxyDoWSGcKVuwnDbAFzTS1eeQ8iquNKhHg=; b=5nKEoeeMFehcBZTyA66JX/6J/+jnF3SNgort33+UesPLtvI/h5O8B551/MqsyvZQ2Y UCHh6gn8+1zm86EBtZpLeBa9VJPEdkfCYbLA+M+V5SfOcJAIoczgUlqor/CgLpQ7hrPu y0iGnbH6dFZkWy2xkH/n240jfX956d45pMfyoqoMTBdlV306ubDYUJFkBsw9Kk9wdPch 1cffANGMgqhCq/t8Kh/5S1QDrox1bVzdLv62/5jL6SJW8wLAvKxpycFfVxXZquuC5miu UEbbqECbNWOiea5T8tJzg9cI9Qh2WQ8TFXKnuJJAil9Qvr0eTmMAuvYkgDozhv0f3BuO qBGA== X-Gm-Message-State: AO0yUKUfu08R0IDgkOXpA8Q8s/0z1jH/+H0g3z6j0q2sJTvXHYd4rPok mmJrupy90KITNc41fiKHspw0tA== X-Google-Smtp-Source: AK7set8BugGWSzpcXOF+U8ElZCVmwXxjqW+AUtbFzv/fvfmkxunl6Mx9kBB42SJN7PEw1mabD7MN+Q== X-Received: by 2002:adf:f041:0:b0:2bf:e45d:8e06 with SMTP id t1-20020adff041000000b002bfe45d8e06mr7616475wro.70.1675172409770; Tue, 31 Jan 2023 05:40:09 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v9 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Tue, 31 Jan 2023 14:39:02 +0100 Message-Id: <20230131133906.1956228-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1675176071564100001 Content-Type: text/plain; charset="utf-8" One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Reviewed-by: Bin Meng --- target/riscv/cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..7181b34f86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } =20 #if defined(TARGET_RISCV64) @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif =20 @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { Property *prop; + DeviceState *dev =3D DEVICE(obj); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); --=20 2.37.2 From nobody Fri Mar 29 05:50:34 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675175425; cv=none; d=zohomail.com; s=zohoarc; b=Fbd3EN4bWG8A+ZUM/C9oGOl9XIuDTvCQYFCA5l23r1RURKSlidaSj2nv2M5mD5PU5v0siQRWvi+cJGv9WFa5X8cF6ob0PmQI7iEO+ItUJN7+wCL6USl4+MPa00f1bmI0I6piyiqJNJy2oBZJMEkrJZ4o61qQ34Ob4nqysHLPmcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675175425; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ku5chqQZqihMdsh/PiLWwwVUxYQvo63LZ6tE21x8W2E=; b=jEVF6vgbpBoaww7fd1FWj03zKTLNKElV0cbjQYi/7E6a53fgBhNJ2oyEeOp/sbcSBiyZsXJO/fY/Wrr2OITAoScYPkzEo2PQLMjQc7rQXuZbh4GI+50KVjwqNwEMDLHyrDMJDY4J55BiWANP+RBH0iO+JR5NiTkFleadcW/te+Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675175425258475.50475085878406; Tue, 31 Jan 2023 06:30:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMqt1-0003UH-BM; Tue, 31 Jan 2023 08:41:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqst-0003TR-Au for qemu-devel@nongnu.org; Tue, 31 Jan 2023 08:41:16 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqsq-00068z-Ck for qemu-devel@nongnu.org; Tue, 31 Jan 2023 08:41:14 -0500 Received: by mail-wm1-x330.google.com with SMTP id o36so4335461wms.1 for ; Tue, 31 Jan 2023 05:41:11 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id q17-20020a05600c46d100b003dc530186e1sm9930680wmo.45.2023.01.31.05.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:41:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ku5chqQZqihMdsh/PiLWwwVUxYQvo63LZ6tE21x8W2E=; b=AwzYVplaT0WA/lNvdWJFGBJ/s1hcEeT1p+2quzbqk5/KvUx9MvaXHt1rP8Pbe9Yzq2 NAF4aSKEY2h69EzcpeSOWNpQo2SczlktgZq3Yx6sKC3u2nVmjl2We0pW1i72JI4HdRmz w42U1tOcmO/vo+Jw6mVBgCZHF/blne/bV9obo4X4J//yGzFbdFK32fuvRhGguIHib800 qb0sIcWduPcNWWaov8udkFvK9jU4lG42iHw6yZSXUDPRlAgVnkG9nv8z/TJ664Kt5uTX 0sQEDLnMG2RKJE8RYkjuhie/dUSXxbLy1k3pgC8VTQW89vc8+hVaqRKrrLkXlzfOJ8ZK Lm0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ku5chqQZqihMdsh/PiLWwwVUxYQvo63LZ6tE21x8W2E=; b=Fa5lDKM5YS5WDkDmZOWoK/c0+W+Rtma+YcLNmPstpfgHz367auUNJAqtj9AFyOFUSU mHYzjUHzbwLrml+6q6ymJ/+aaFk6YksrJYOnyLQIb1UN9EulXx/yYI5603tiHcC/lkf4 S2zbrmpF/SpFgaGLYzSJw17Pwf9w7zYr2Ow6CgIcSePN3ATthxeSnQnkdCryEjReciqQ P6XRey1cJWVSafIVf6+JR7DZq7H0a8mEesH9UWa7Odu1nhzYnUxh2hlGwgLENutEIfZB Y4VETn8g13A/zgli5Btu6hl1+duVTSCz6O8MPE8eaF0ESwEyClvVCqM30P0LdcD+b5on f7cg== X-Gm-Message-State: AO0yUKV5nBBxuSrMYQiVU2G+PHOg2rtJuwd3f37xOaVQlmes03a8t/Ed SDwZpuYwwEpqFzW49tlhHjgDTg== X-Google-Smtp-Source: AK7set+xnFsQeypNN5GmlkA9HSsjJNUzwVGy636BPp46R9gstn14tGJE7W/jW4k+1SChO5ZcPiB/8A== X-Received: by 2002:a05:600c:4e89:b0:3dc:198c:dde with SMTP id f9-20020a05600c4e8900b003dc198c0ddemr24378639wmq.41.1675172470734; Tue, 31 Jan 2023 05:41:10 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v9 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Date: Tue, 31 Jan 2023 14:39:03 +0100 Message-Id: <20230131133906.1956228-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1675175426728100001 Content-Type: text/plain; charset="utf-8" This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang --- target/riscv/csr.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..6b157806a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask =3D MIP= _VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; =20 -static const char valid_vm_1_10_32[16] =3D { - [VM_1_10_MBARE] =3D 1, - [VM_1_10_SV32] =3D 1 +static const bool valid_vm_1_10_32[16] =3D { + [VM_1_10_MBARE] =3D true, + [VM_1_10_SV32] =3D true }; =20 -static const char valid_vm_1_10_64[16] =3D { - [VM_1_10_MBARE] =3D 1, - [VM_1_10_SV39] =3D 1, - [VM_1_10_SV48] =3D 1, - [VM_1_10_SV57] =3D 1 +static const bool valid_vm_1_10_64[16] =3D { + [VM_1_10_MBARE] =3D true, + [VM_1_10_SV39] =3D true, + [VM_1_10_SV48] =3D true, + [VM_1_10_SV57] =3D true }; =20 /* Machine Information Registers */ @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 -static int validate_vm(CPURISCVState *env, target_ulong vm) +static bool validate_vm(CPURISCVState *env, target_ulong vm) { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, i= nt csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong vm, mask; + target_ulong mask; + bool vm; =20 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; --=20 2.37.2 From nobody Fri Mar 29 05:50:34 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675177976; cv=none; d=zohomail.com; s=zohoarc; b=IkX/ZafWi633nJ0Jru6ZBwNSkK4/lHwSUXRDoOXDNKhLgxNyIYc1yf2E8G6G0+j24Bg88P337ltypRCpMxeY+evAZpuD6woQL3p+EojZ1yHJQ1UNDffViPVlmqzfh64OI8XM442Wkub/amNHuhXS3JAD6TD2ngvHoRMU3Mw+yH0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675177976; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/xWI81SB82ol0jqat49BKKkw/QWECDCIZK34P0AOPDY=; b=TcRrLUEBIMPhxWXJ+8GELmjFwG3oXd6EnkuDE3nPyNIfjlM1vFUzDT3USFWReodyjHmLzTrxsjV2+1JeW+LnTd1DnyjQlSRb9BkwlPqk55jQd2OyC0V1d5iE4jEXkcevvIbh27Z3bIVW6s0ueia5o97Tu5JD5Cet+57vgOgEeKw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675177976113582.9761800766242; Tue, 31 Jan 2023 07:12:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMqtu-0003a2-L7; Tue, 31 Jan 2023 08:42:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqtt-0003Zh-FM for qemu-devel@nongnu.org; Tue, 31 Jan 2023 08:42:17 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqtp-0006Hk-Mx for qemu-devel@nongnu.org; Tue, 31 Jan 2023 08:42:16 -0500 Received: by mail-wm1-x32b.google.com with SMTP id o36so4337649wms.1 for ; Tue, 31 Jan 2023 05:42:13 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id j15-20020a5d452f000000b002be505ab59asm14740250wra.97.2023.01.31.05.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:42:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/xWI81SB82ol0jqat49BKKkw/QWECDCIZK34P0AOPDY=; b=2qkqGvDbenczEGG0DoMmxmGpa/G1hjy6XPsgiAEN9KLXnMFdw0lIxqrxMJL7HXxneD 9AKIzfa75Xhi8jTvR6oJYle03PNbMrwAIcefFZeXl0ZfgOhEwxDp+WSPquOVMOIOm7/9 wH5+TL87aPL5VrTtnsC0pZbqFpGY4vufA4dVYocl/ZGIV3DCes0uILGzJgW3o6HrQhd7 f/nd7SWhXWCurc8KN06W2J03aySLwZcwIY8v96inlya+7Km+e6DfKT9/m+yhGjI8fntN DUVaI4C3VQk6KwBHJm4L69+yIjWTMivdwuLUAqRKei9nFhKoTBK4LSqx5hAdfKhJ9XYx UXMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/xWI81SB82ol0jqat49BKKkw/QWECDCIZK34P0AOPDY=; b=NM+fZuOViP7cM1zpfVriS4O1coKOPfOUFgOvaUJTP7x3K4LYqJGNcmVzz+djCos7PD 54S5P6458sKg7Sz3GaNG/65Dj8ix5UuhxGrrgkjESju2F8ySGVyha5Dr3+ARsjeXYCWW pUWzWiek987OcUMUbAoAVrKILT5HhtoRZKnoubMvc0SErrNhg2+GQTAIPIQL+V00zoDv TWtk/d80/iXTrNpejaU46ecPY883taq4Yri85+0OpTPXHJL9/+hlzhjQfzNU8yu7HNwO X1TVmW7iSr1pbwmv5EdvM4qZdmT7Bg2GfISoDxVawn5an7xol37wlgxyIr+7AS7vyObG ESkw== X-Gm-Message-State: AO0yUKVHS+YZFSP2eOFXMI4NJP6Tvtobp2i2v2FhURipazMUifnPwExD KrIeZwaoVDkYzFNDEek6UIl7YQ== X-Google-Smtp-Source: AK7set9R5GvHOxAGra/GqnbrijAvtZPDrUeiu02fnemnV9zxkrkpbGH5ZxA0RkG7VkVYPXDcDIocxg== X-Received: by 2002:a05:600c:548c:b0:3dc:5390:6499 with SMTP id iv12-20020a05600c548c00b003dc53906499mr3662861wmb.1.1675172531676; Tue, 31 Jan 2023 05:42:11 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Ludovic Henry Subject: [PATCH v9 3/5] riscv: Allow user to set the satp mode Date: Tue, 31 Jan 2023 14:39:04 +0100 Message-Id: <20230131133906.1956228-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1675178074790100001 Content-Type: text/plain; charset="utf-8" RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=3Don # Linux will boot using sv57 scheme -cpu rv64,sv39=3Don # Linux will boot using sv39 scheme -cpu rv64,sv57=3Doff # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=3Don,sv57=3Don # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=3Doff,sv48=3Don # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=3Don,sv57=3Doff # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=3Don,sv48=3Doff # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Acked-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 207 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 19 +++++ target/riscv/csr.c | 12 ++- 3 files changed, 231 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7181b34f86..3a7a1746aa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -27,6 +27,7 @@ #include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int v= ext_ver) env->vext_ver =3D vext_ver; } =20 +static uint8_t satp_mode_from_str(const char *satp_mode_str) +{ + if (!strncmp(satp_mode_str, "mbare", 5)) { + return VM_1_10_MBARE; + } + + if (!strncmp(satp_mode_str, "sv32", 4)) { + return VM_1_10_SV32; + } + + if (!strncmp(satp_mode_str, "sv39", 4)) { + return VM_1_10_SV39; + } + + if (!strncmp(satp_mode_str, "sv48", 4)) { + return VM_1_10_SV48; + } + + if (!strncmp(satp_mode_str, "sv57", 4)) { + return VM_1_10_SV57; + } + + if (!strncmp(satp_mode_str, "sv64", 4)) { + return VM_1_10_SV64; + } + + g_assert_not_reached(); +} + +uint8_t satp_mode_max_from_map(uint32_t map) +{ + /* map here has at least one bit set, so no problem with clz */ + return 31 - __builtin_clz(map); +} + +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) +{ + if (is_32_bit) { + switch (satp_mode) { + case VM_1_10_SV32: + return "sv32"; + case VM_1_10_MBARE: + return "none"; + } + } else { + switch (satp_mode) { + case VM_1_10_SV64: + return "sv64"; + case VM_1_10_SV57: + return "sv57"; + case VM_1_10_SV48: + return "sv48"; + case VM_1_10_SV39: + return "sv39"; + case VM_1_10_MBARE: + return "none"; + } + } + + g_assert_not_reached(); +} + +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default_map(RISCVCPU *cpu) +{ + bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; + + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + cpu->cfg.satp_mode.map |=3D + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); + } else { + cpu->cfg.satp_mode.map |=3D (1 << satp_mode_from_str("mbare")); + } +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -619,6 +695,83 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) +{ + bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; + const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + uint8_t satp_mode_max; + + if (cpu->cfg.satp_mode.map =3D=3D 0) { + if (cpu->cfg.satp_mode.init =3D=3D 0) { + /* If unset by the user, we fallback to the default satp mode.= */ + set_satp_mode_default_map(cpu); + } else { + /* + * Find the lowest level that was disabled and then enable the + * first valid level below which can be found in + * valid_vm_1_10_32/64. + */ + for (int i =3D 1; i < 16; ++i) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { + for (int j =3D i - 1; j >=3D 0; --j) { + if (valid_vm[j]) { + cpu->cfg.satp_mode.map |=3D (1 << j); + break; + } + } + break; + } + } + } + } + + /* Make sure the configuration asked is supported by qemu */ + for (int i =3D 0; i < 16; ++i) { + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { + error_setg(errp, "satp_mode %s is not valid", + satp_mode_str(i, rv32)); + return; + } + } + + /* + * Make sure the user did not ask for an invalid configuration as per + * the specification. + */ + satp_mode_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + if (!rv32) { + for (int i =3D satp_mode_max - 1; i >=3D 0; --i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + error_setg(errp, "cannot disable %s satp mode if %s " + "is enabled", satp_mode_str(i, false), + satp_mode_str(satp_mode_max, false)); + return; + } + } + } + + /* Finally expand the map so that all valid modes are set */ + for (int i =3D satp_mode_max - 1; i >=3D 0; --i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.map |=3D (1 << i); + } + } +} + +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + Error *local_err =3D NULL; + + riscv_cpu_satp_mode_finalize(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -919,6 +1072,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } #endif =20 + riscv_cpu_finalize_features(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_register_gdb_regs_for_features(cs); =20 qemu_init_vcpu(cs); @@ -927,6 +1086,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) mcc->parent_realize(dev, errp); } =20 +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map =3D opaque; + uint8_t satp =3D satp_mode_from_str(name); + bool value; + + value =3D satp_map->map & (1 << satp); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map =3D opaque; + uint8_t satp =3D satp_mode_from_str(name); + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + satp_map->map =3D deposit32(satp_map->map, satp, 1, value); + satp_map->init |=3D 1 << satp; +} + +static void riscv_add_satp_mode_properties(Object *obj) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + + if (cpu->env.misa_mxl =3D=3D MXL_RV32) { + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } else { + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } +} + #ifndef CONFIG_USER_ONLY static void riscv_cpu_set_irq(void *opaque, int irq, int level) { @@ -1091,6 +1296,8 @@ static void register_cpu_props(Object *obj) for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + riscv_add_satp_mode_properties(obj); } =20 static Property riscv_cpu_properties[] =3D { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..e37177db5c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "qapi/qapi-types-common.h" =20 #define TCG_GUEST_DEFAULT_MO 0 =20 @@ -413,6 +414,17 @@ struct RISCVCPUClass { ResettablePhases parent_phases; }; =20 +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maxi= mum + * satp mode that is supported. + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPMap; + struct RISCVCPUConfig { bool ext_i; bool ext_e; @@ -488,6 +500,8 @@ struct RISCVCPUConfig { bool debug; =20 bool short_isa_string; + + RISCVSATPMap satp_mode; }; =20 typedef struct RISCVCPUConfig RISCVCPUConfig; @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 +uint8_t satp_mode_max_from_map(uint32_t map); +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b157806a5..f9eff3f1e3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask =3D MIP= _VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; =20 -static const bool valid_vm_1_10_32[16] =3D { +const bool valid_vm_1_10_32[16] =3D { [VM_1_10_MBARE] =3D true, [VM_1_10_SV32] =3D true }; =20 -static const bool valid_vm_1_10_64[16] =3D { +const bool valid_vm_1_10_64[16] =3D { [VM_1_10_MBARE] =3D true, [VM_1_10_SV39] =3D true, [VM_1_10_SV48] =3D true, @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *en= v, int csrno, =20 static bool validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; - } else { - return valid_vm_1_10_64[vm & 0xf]; - } + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + + return (vm & 0xf) <=3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); } =20 static RISCVException write_mstatus(CPURISCVState *env, int csrno, --=20 2.37.2 From nobody Fri Mar 29 05:50:34 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id z14-20020a5d4d0e000000b002bde537721dsm14674268wrt.20.2023.01.31.05.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:43:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xr8l2kRHet+WGvZ91sTorq6F44YCzLQrc8tXbbSCvKg=; b=MqM5lEinciXBWajqof4C//fBExmr3SFmwkkNcOBJlYx/h7zg04ClJWTq6UNwjluALH PlHsvMgJxgaukU0OYOBczfSuRtuOxof6YDyekJbWZ3WehM7hxYC8T439MxcnwP7N4yNw oImn4tvyBD1B06M8TuPkjvtqOb3n2YBIlqFAxcZ8wB/RbTVcMzInV4NgDcLPVPg9KU1A JCEVt86V4tk6Qw5PsFGp481sAscni/y/UYldOvWGSFOa8iBiAnfDfwQyehfngo22hfJ5 mROdQiar4du1S0ubPi7e99o5tJ3xFPR46rrXcF+5MJz6DsCboC5FdG87g1pyiHXFT0ez BfAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xr8l2kRHet+WGvZ91sTorq6F44YCzLQrc8tXbbSCvKg=; b=nNTS10wppDz5VQYKXP0K+qoonyJ+WbitdX18fxiwkZkFhmvo+N1rc0nJRr0U1dwpjf vio1VHnZKI+Cv6Rqh/05OAtjDTyolNK9Zyy3T5/ASeGszCIUo8og+4hf1wQgvwfH+mfc X0Qa6u3DAklZqs4DVmKWOMo8gX3Omxr5BQfs5rkjjz33t7kUZjSzhU9ZZ6Wa9Ah6LlBO VO3phhKKvmOwcFrJnJZp7buKcnGivE27njpxVNmJCvORn4xEpKf5b4+daiUYUZO3Sif6 wyJhUuf5ue+Fh3STla6QZWPWC++31kgHTpare+F+IlYj5Z7bbEb0QxpykIhJORASortj De5w== X-Gm-Message-State: AO0yUKWmOHwy7u4UN7YOte+ZtnrHxpruhGGTNWH1+6jfkgbShkcnzsjs bo3DOuuP3LxgQSI46c9KxmQXlg== X-Google-Smtp-Source: AK7set/JXsj1d3DPJPO7x3X67IhSmvGgTgh0MkjgpAgXh/TeiSKJGNAPBt08vr42jvGc+iYE2N6N0g== X-Received: by 2002:a5d:610f:0:b0:2bf:ede3:988a with SMTP id v15-20020a5d610f000000b002bfede3988amr6829997wrt.22.1675172592608; Tue, 31 Jan 2023 05:43:12 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v9 4/5] riscv: Introduce satp mode hw capabilities Date: Tue, 31 Jan 2023 14:39:05 +0100 Message-Id: <20230131133906.1956228-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1675176201348100003 Content-Type: text/plain; charset="utf-8" Currently, the max satp mode is set with the only constraint that it must be implemented in QEMU, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng --- target/riscv/cpu.c | 79 +++++++++++++++++++++++++++++++--------------- target/riscv/cpu.h | 8 +++-- 2 files changed, 60 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3a7a1746aa..6dd76355ec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_= 32_bit) g_assert_not_reached(); } =20 -/* Sets the satp mode to the max supported */ -static void set_satp_mode_default_map(RISCVCPU *cpu) +static void set_satp_mode_max_supported(RISCVCPU *cpu, + uint8_t satp_mode) { bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; + const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; =20 - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { - cpu->cfg.satp_mode.map |=3D - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); - } else { - cpu->cfg.satp_mode.map |=3D (1 << satp_mode_from_str("mbare")); + for (int i =3D 0; i <=3D satp_mode; ++i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.supported |=3D (1 << i); + } } } =20 +/* Set the satp mode to the max supported */ +static void set_satp_mode_default_map(RISCVCPU *cpu) +{ + cpu->cfg.satp_mode.map =3D cpu->cfg.satp_mode.supported; +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); #endif set_priv_version(env, PRIV_VERSION_1_12_0); register_cpu_props(obj); @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj) static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); } =20 static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV39); } =20 static void rv64_sifive_e_cpu_init(Object *obj) @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } =20 static void rv128_base_cpu_init(Object *obj) @@ -354,28 +371,36 @@ static void rv128_base_cpu_init(Object *obj) exit(EXIT_FAILURE); } CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); } #else static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); } =20 static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); } =20 static void rv32_sifive_e_cpu_init(Object *obj) @@ -386,6 +411,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } =20 static void rv32_ibex_cpu_init(Object *obj) @@ -396,6 +422,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu =3D false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); cpu->cfg.epmp =3D true; } =20 @@ -407,6 +434,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } #endif =20 @@ -698,8 +726,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disas= semble_info *info) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; - const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - uint8_t satp_mode_max; + uint8_t satp_mode_map_max; + uint8_t satp_mode_supported_max =3D + satp_mode_max_from_map(cpu->cfg.satp_mode.supporte= d); =20 if (cpu->cfg.satp_mode.map =3D=3D 0) { if (cpu->cfg.satp_mode.init =3D=3D 0) { @@ -712,9 +741,10 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu= , Error **errp) * valid_vm_1_10_32/64. */ for (int i =3D 1; i < 16; ++i) { - if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && + (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j =3D i - 1; j >=3D 0; --j) { - if (valid_vm[j]) { + if (cpu->cfg.satp_mode.supported & (1 << j)) { cpu->cfg.satp_mode.map |=3D (1 << j); break; } @@ -725,37 +755,36 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) } } =20 - /* Make sure the configuration asked is supported by qemu */ - for (int i =3D 0; i < 16; ++i) { - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { - error_setg(errp, "satp_mode %s is not valid", - satp_mode_str(i, rv32)); - return; - } + satp_mode_map_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + /* Make sure the user asked for a supported configuration (HW and qemu= ) */ + if (satp_mode_map_max > satp_mode_supported_max) { + error_setg(errp, "satp_mode %s is higher than hw max capability %s= ", + satp_mode_str(satp_mode_map_max, rv32), + satp_mode_str(satp_mode_supported_max, rv32)); + return; } =20 /* * Make sure the user did not ask for an invalid configuration as per * the specification. */ - satp_mode_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); - if (!rv32) { - for (int i =3D satp_mode_max - 1; i >=3D 0; --i) { + for (int i =3D satp_mode_map_max - 1; i >=3D 0; --i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), - satp_mode_str(satp_mode_max, false)); + satp_mode_str(satp_mode_map_max, false)); return; } } } =20 /* Finally expand the map so that all valid modes are set */ - for (int i =3D satp_mode_max - 1; i >=3D 0; --i) { - if (valid_vm[i]) { + for (int i =3D satp_mode_map_max - 1; i >=3D 0; --i) { + if (cpu->cfg.satp_mode.supported & (1 << i)) { cpu->cfg.satp_mode.map |=3D (1 << i); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e37177db5c..b591122099 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -416,13 +416,17 @@ struct RISCVCPUClass { =20 /* * map is a 16-bit bitmap: the most significant set bit in map is the maxi= mum - * satp mode that is supported. + * satp mode that is supported. It may be chosen by the user and must resp= ect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). * * init is a 16-bit bitmap used to make sure the user selected a correct * configuration as per the specification. + * + * supported is a 16-bit bitmap used to reflect the hw capabilities. */ typedef struct { - uint16_t map, init; + uint16_t map, init, supported; } RISCVSATPMap; =20 struct RISCVCPUConfig { --=20 2.37.2 From nobody Fri Mar 29 05:50:34 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675175508; cv=none; d=zohomail.com; s=zohoarc; b=e0F7GOEZJiwHFATNMq1tDe1LzSncEohRXrzISFcSlO1vfQ49xyFddAY39yoR7Yw9/DtOgpdAK9rTWdfWSC1hmI9pmc+Wgh9+qoaWr+OPpX0PkKhUbdaZXv5IOisCCirVpSCYy4uNHSqXqfsYsqo5TRB22jiJDrkmZJfKAOzqpZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675175508; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KnBnWPYZTJbtqglsFebcan2CK1/moGM7upa/HPAcASY=; b=fcy7yuyWI+iFtQzYemNBvdxVMBp23782zwfqRJ3XfE4spGFaPvNszpg9Y4CXy/01ybaR7Mm0D1Qf/lMrLiBxLGFvd7rX5fRweZTgzu+7vuTYLrK6MoauTwNsd368eWmMnrX6anbjRhGtTncjWpC3MDq1MpQc9e8qs3H8TTwYBM8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675175508091502.1423091335953; Tue, 31 Jan 2023 06:31:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMqvq-00047S-Mb; Tue, 31 Jan 2023 08:44:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqvp-00047C-S6 for qemu-devel@nongnu.org; Tue, 31 Jan 2023 08:44:17 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqvm-0006V8-T2 for qemu-devel@nongnu.org; Tue, 31 Jan 2023 08:44:17 -0500 Received: by mail-wm1-x32e.google.com with SMTP id k16so10379673wms.2 for ; Tue, 31 Jan 2023 05:44:14 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id i19-20020a05600c2d9300b003dc4fd6e624sm9127246wmg.19.2023.01.31.05.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:44:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KnBnWPYZTJbtqglsFebcan2CK1/moGM7upa/HPAcASY=; b=s87HJBFMwu70JeiT/b45Ow0Qn3rHu7bS7vFRw+vffUis2sgQLkD+oCVOfdv8D+geiP VbzIKHNznO1fMXLxedThqw33tg/MAU0tdQj9emshENFZ17zRwd9oAKQ8yxnc/kArFA8Y 1x3PdoBOWCMTalFQSYgCFqVf8FZDJfKGdaxfkoVMjbItJYHtU5NxQnipTm+M+YTkKpSB wDHOeGPbzSsg4Kj7J15OIr/zbHPhIjWOuoF4xam+0+ma7hANb6wD0kvU6Z5jXUjWYvK1 k/U5bHe/Nf6l5kMv1ix0B7tteGv5jZKhWfQtf+BCQbysnFLKz0on7jVVoNU8AjrpHy0R C55Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KnBnWPYZTJbtqglsFebcan2CK1/moGM7upa/HPAcASY=; b=i+Y88CUUbnGtI7WbDX4pRxcTjGGYKQbbZ9f9TUy8sfQLc8/yBkAvSVBtPCXZIUi+b7 zQqc3Hxh7eSalqQyRZIO9MbCJ2Ibw/B3qkpxDzXaeFSCDoczLvmUc/KsAlG/ZMm25WR/ m5pVvMPFb8KwYgsNt81wviSA73K8PlyMF8pArgTZ/Td6nRmBfaY4V+6Qjuifda4EKICl PS81diavghzZArCYVpyIaLG8vlUyCMWJI3sSdNqIQLMrsiR4ECh1Y1aCVtjmDIX1upZB fhLpPfmDubJ29JVB0qewmEQfVBZqxOalJJJLdyGB6x6TGkiJ4aImpp8t6jaDjmmSw/qx rN0w== X-Gm-Message-State: AFqh2krK8uPl0pIyt1kSHIbdwUvASJxZsSaOuRh23YjtWkdsLOgQsPb4 Hm7Mn4pF7oMpVKRK34y+R+lsgA== X-Google-Smtp-Source: AMrXdXvSi4cR1fwWVRlWrtR2Q9AZ1HH7nA3Hr2AuyvmfwS2+JHt/p8biQlRTFnpAOHejUIjQKGDyxg== X-Received: by 2002:a05:600c:4f96:b0:3db:2dbb:d70e with SMTP id n22-20020a05600c4f9600b003db2dbbd70emr42419610wmq.6.1675172653566; Tue, 31 Jan 2023 05:44:13 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v9 5/5] riscv: Correctly set the device-tree entry 'mmu-type' Date: Tue, 31 Jan 2023 14:39:06 +0100 Message-Id: <20230131133906.1956228-6-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1675175509431100001 Content-Type: text/plain; charset="utf-8" The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang --- hw/riscv/virt.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..48d034a5f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, i= nt socket, int cpu; uint32_t cpu_phandle; MachineState *mc =3D MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + uint8_t satp_mode_max; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; =20 for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { cpu_phandle =3D (*phandle)++; @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,= int socket, cpu_name =3D g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? "riscv,sv32" : "riscv,sv= 48"); - } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - "riscv,none"); - } + + satp_mode_max =3D satp_mode_max_from_map( + s->soc[socket].harts[cpu].cfg.satp_mode.map); + sv_name =3D g_strdup_printf("riscv,%s", + satp_mode_str(satp_mode_max, is_32_bit)); + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); + g_free(sv_name); + name =3D riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); g_free(name); --=20 2.37.2