From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675196530; cv=none; d=zohomail.com; s=zohoarc; b=PK4R8yK5Oev0nF2wWCgIrCEDFadDVLrPhDr5uEAgPdoMtQjwFJT8rujq0pdERyj7cCCa4A0zyeNeWz+bHNaUgSaJt7txF3CvW3Cii912XQr1idtaTJZQfhgFLpjfLGjRIb50j4fxOPb/A21iwB+AGnT1H4aYzNgjRxlF1ay4qvs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675196530; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UIMc0yh6nW6tPabnRz0gkGn0xHCplcfPWfd18Srv1EY=; b=AC6Qjpqtf1OtC5EHH18LmFcNabUKVczh7MaoV7pcx8ky++hNEMTFj/ICCjeo5Sad+mAv7BguDhT4Do5q2puO6pdsxGm9aFZzgUxS/LX/ckzQy3Ez5bF6RlA1mEwiYQVxiHjvwFTBLiygp1alq8xcPP6Fe9sxSpwdiQhwmX7wtvw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675196530305692.0131554571344; Tue, 31 Jan 2023 12:22:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMx7B-0006lB-Gl; Tue, 31 Jan 2023 15:20:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMx7A-0006kc-5b for qemu-devel@nongnu.org; Tue, 31 Jan 2023 15:20:24 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMx75-0002if-UX for qemu-devel@nongnu.org; Tue, 31 Jan 2023 15:20:23 -0500 Received: by mail-wr1-x436.google.com with SMTP id h16so15326406wrz.12 for ; Tue, 31 Jan 2023 12:20:19 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UIMc0yh6nW6tPabnRz0gkGn0xHCplcfPWfd18Srv1EY=; b=QYn/YpvVHYyT1BPfyo8SQiVCWbAYXVm8uWeS6/ZFJ6GEl6EtopkvGXzz/YHyA5ck1K xg5KNWajEATBB+pThWirLHedtO8moMYAHypOKRkNFUOA87gbz3XqXPjKOIJteqIV8gjT wnLFL7BPdpRgXynhKzChnT9GoM7vToLmY2jxgJT2eaHFjVfFEsgUF32vshSPaRsrSkxk cMgZFqUXkXNa+yi41up9AnGGS4es8Z/B/y/eCsqFSVBGjo3zbbGs6tnStSnVHM/OZ48C J4vtkoNkRMxuD27wQk95K6KAk2qSViyvEV3spv8CBbUS3MqMTBgSXe4jq0PLlse5/aTb A0pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UIMc0yh6nW6tPabnRz0gkGn0xHCplcfPWfd18Srv1EY=; b=l+4XkWhh70CcrC/gSeECyRgtrUYlFtmpgBpj4UC0Cd40T+RUNVzDhtjW5+F04mAhTn IA9wUGuuBiXV+Tk8K5g5qC9doe7yyrIM3sJnE245DA4MEFqeQh+a1jba5n6yaD5w6GOw lBBpLhu5a2aCEeLMg3tZSzeG7WF9tfy4x+G1IlvX92Ct8IMEp5WM55Qb9pf8MpBaBHft zfPpxsAtjeDssate8rzecikuZzwbODgEydLLN9wm0odbpZsOdO/DgdVywB+jL9AUK/li xNG9Uifo0p6sc7qUXoaGLBjDTtYSBHr5yFlMfY2QbLArkcikA/w+3pyjCC7VY+o0T4QV EZMw== X-Gm-Message-State: AO0yUKVjHpjgleWJ2TgJX6pdYk5bV5J0rkrGCe1g+zuLOPc3z2keRk0x e9QcwVfVlhqnlcOuSB36qylPvw== X-Google-Smtp-Source: AK7set9+rnZw3lr7AAR8L5ga+c1w2grYjWW83nXaonox5qjASLBXL20HLGKBsRohM/ydVx+bD+D+kQ== X-Received: by 2002:a5d:5958:0:b0:2bf:ee58:72ae with SMTP id e24-20020a5d5958000000b002bfee5872aemr239811wri.50.1675196418407; Tue, 31 Jan 2023 12:20:18 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 01/14] RISC-V: Adding XTheadCmo ISA extension Date: Tue, 31 Jan 2023 21:20:00 +0100 Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196532379100006 From: Christoph M=C3=BCllner This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific files. Future patches should be able to easily add additional T-Head extension. The implementation does not have much functionality (besides accepting the instructions and not qualifying them as illegal instructions if the hart executes in the required privilege level for the instruction), as QEMU does not model CPU caches and instructions are documented to not raise any exceptions. Co-developed-by: LIU Zhiwei Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Explicit test for PRV_U - Encapsule access to env-priv in inline function - Use single decoder for XThead extensions Changes in v3: - Appling mask TB_FLAGS_PRIV_MMU_MASK to use of ctx->mem_idx - Removing code from test macro REQUIRE_PRIV_MSU() - Removing PRV_H from test macro REQUIRE_PRIV_MS() - Remove unrelated clean-up - Reorder decoder includes Changes in v4: - Reorder decoder includes target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 81 ++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 8 +++ target/riscv/xthead.decode | 38 ++++++++++ 6 files changed, 131 insertions(+) create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xthead.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 14a7027095..6ea61e5b22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; =20 @@ -1088,6 +1089,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), =20 /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bcf0826753..d3ebc6f112 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { uint64_t mimpid; =20 /* Vendor-specific custom extensions */ + bool ext_xtheadcmo; bool ext_XVentanaCondOps; =20 uint8_t pmu_num; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc new file mode 100644 index 0000000000..24acaf188c --- /dev/null +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -0,0 +1,81 @@ +/* + * RISC-V translation routines for the T-Head vendor extensions (xthead*). + * + * Copyright (c) 2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#define REQUIRE_XTHEADCMO(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ + return false; \ + } \ +} while (0) + +/* XTheadCmo */ + +static inline int priv_level(DisasContext *ctx) +{ +#ifdef CONFIG_USER_ONLY + return PRV_U; +#else + /* Priv level is part of mem_idx. */ + return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK; +#endif +} + +/* Test if priv level is M, S, or U (cannot fail). */ +#define REQUIRE_PRIV_MSU(ctx) + +/* Test if priv level is M or S. */ +#define REQUIRE_PRIV_MS(ctx) \ +do { \ + int priv =3D priv_level(ctx); \ + if (!(priv =3D=3D PRV_M || \ + priv =3D=3D PRV_S)) { \ + return false; \ + } \ +} while (0) + +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ +{ \ + (void) a; \ + extcheck(ctx); \ + privcheck(ctx); \ + return true; \ +} + +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) + +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index ba25164d74..5dee37a242 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -2,6 +2,7 @@ gen =3D [ decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), + decodetree.process('xthead.decode', extra_args: '--static-decode=3Ddecod= e_xthead'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), ] =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 01cc30a365..1e29ac9886 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -130,6 +130,11 @@ static bool always_true_p(DisasContext *ctx __attribu= te__((__unused__))) return true; } =20 +static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) +{ + return ctx->cfg_ptr->ext_xtheadcmo; +} + #define MATERIALISE_EXT_PREDICATE(ext) \ static bool has_ ## ext ## _p(DisasContext *ctx) \ { \ @@ -1080,6 +1085,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" +#include "decode-xthead.c.inc" +#include "insn_trans/trans_xthead.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" =20 /* Include the auto-generated decoder for 16 bit insn */ @@ -1106,6 +1113,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] =3D { { always_true_p, decode_insn32 }, + { has_xthead_p, decode_xthead }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; =20 diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode new file mode 100644 index 0000000000..30533a66f5 --- /dev/null +++ b/target/riscv/xthead.decode @@ -0,0 +1,38 @@ +# +# Translation routines for the instructions of the XThead* ISA extensions +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The documentation of the ISA extensions can be found here: +# https://github.com/T-head-Semi/thead-extension-spec/releases/latest + +# Fields: +%rs1 15:5 + +# Formats +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 + +# XTheadCmo +th_dcache_call 0000000 00001 00000 000 00000 0001011 +th_dcache_ciall 0000000 00011 00000 000 00000 0001011 +th_dcache_iall 0000000 00010 00000 000 00000 0001011 +th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm +th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm +th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm +th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm +th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm +th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm +th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm +th_icache_iall 0000000 10000 00000 000 00000 0001011 +th_icache_ialls 0000000 10001 00000 000 00000 0001011 +th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm +th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm +th_l2cache_call 0000000 10101 00000 000 00000 0001011 +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 +th_l2cache_iall 0000000 10110 00000 000 00000 0001011 --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SZegSXhsxlv9N/vVZ4WumTWFg4tDXkbLvsFx6aF6o0o=; b=PdQ76napMucS6ZFXKtiVthT5n3g+Nk7UEI/iL3OV9tarSnW0eohkaUx0fhrKFZariY G/YAqZA6LcO5C29DlEWsY/5zAwbyLZFxvL9MvO8yLl1x1wTnQVmem1msfLhYexqkg3r9 lgbFfgLTbSTWxDvTv35CXn24UjKML5ymhzDO2nvQ7kj+Wq615P7n6iJr4KbWfjNwzr7y wvVPbANIbfssKhpC2Es/fpVzFztdpUsRrxwuS4GhCa6/2HhoiUuz1K8dtK5UcA4+Pz01 mv1k0d6klX/MRVmgCeXL4n0+U503KgGr6hMRk8dSpHVj+6niRWHYlU6uTeU+ovSGe6DM 60Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SZegSXhsxlv9N/vVZ4WumTWFg4tDXkbLvsFx6aF6o0o=; b=XM4/PO2xXPqftaQLlRxE3zQKANUbcFLYjIxYP4LmuXSQV8SvRsM0PdeL2+ByNUJyBu Prfy9x9wZHiEMZ7grTpBybfECKkB1Ge1hdWAYtVyLM7cVlaqMMdIe5+WafQMNs8MvOlR fq4eTdtuksjs+Oj3ebgdtrM4anesYRDXzv51gQjf5mOUAE96X5VM5UJ1Du0awcgKb2aE pBAb9fK4IkH3ZdurnmlgcJg++z6m77/ClZ08eHsfXTISs2hckjoVEpe1cR5OI2hZ2Spy k90QvtVYJD8CBoHBjbgtCHqTKODLlTo10ftdGImfOzmYsMfkbLUpHDxXNiAucLw3g9XI z9BA== X-Gm-Message-State: AO0yUKXCxEZ6vmjFZatHJY0oAR8H/1ucZEXj4taIpKBTOlRIjv0Asgs+ 5j9mpdvvVoDlxcajZNjpiyQkyw== X-Google-Smtp-Source: AK7set8xZkkJTRapDFZvayCPpWi241jYZ9/yRVak4kdiRprHY9fYPlGjqklO5R2JKXjZTRahGzut5A== X-Received: by 2002:a5d:5602:0:b0:2bd:dd13:170f with SMTP id l2-20020a5d5602000000b002bddd13170fmr261996wrv.26.1675196420075; Tue, 31 Jan 2023 12:20:20 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 02/14] RISC-V: Adding XTheadSync ISA extension Date: Tue, 31 Jan 2023 21:20:01 +0100 Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196471378100001 From: Christoph M=C3=BCllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use helper to synchronize CPUs and perform TLB flushes - Change implemenation to follow latest spec update - Use single decoder for XThead extensions Changes in v3: - Adjust for renamed REQUIRE_PRIV_* test macros Changes in v4: - Drop decode_save_opc() in trans_th_sfence_vmas() target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 85 ++++++++++++++++++++++ target/riscv/op_helper.c | 6 ++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 9 +++ 7 files changed, 105 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ea61e5b22..f76639845d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), + ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; =20 @@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] =3D { =20 /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3ebc6f112..ea00586436 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { =20 /* Vendor-specific custom extensions */ bool ext_xtheadcmo; + bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 uint8_t pmu_num; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 58a30f03d6..0497370afd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -109,6 +109,7 @@ DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) +DEF_HELPER_1(tlb_flush_all, void, env) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) #endif diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 24acaf188c..f35bf6ea89 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADSYNC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadsync) { \ + return false; \ + } \ +} while (0) + /* XTheadCmo */ =20 static inline int priv_level(DisasContext *ctx) @@ -79,3 +85,82 @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_= PRIV_MSU) NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +/* XTheadSync */ + +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MS(ctx); + gen_helper_tlb_flush_all(cpu_env); + return true; +#else + return false; +#endif +} + +#ifndef CONFIG_USER_ONLY +static void gen_th_sync_local(DisasContext *ctx) +{ + /* + * Emulate out-of-order barriers with pipeline flush + * by exiting the translation block. + */ + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp =3D DISAS_NORETURN; +} +#endif + +static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync is an out-of-order barrier. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync.i is th.sync plus pipeline flush. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a) +{ + /* This instruction has the same behaviour like th.sync.i. */ + return trans_th_sync_i(ctx, a); +} + +static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a) +{ + /* This instruction has the same behaviour like th.sync. */ + return trans_th_sync(ctx, a); +} diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 878bcb03b8..48f918b71b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -258,6 +258,12 @@ void helper_tlb_flush(CPURISCVState *env) } } =20 +void helper_tlb_flush_all(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + tlb_flush_all_cpus_synced(cs); +} + void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1e29ac9886..0657a4bea2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,7 @@ static bool always_true_p(DisasContext *ctx __attribut= e__((__unused__))) =20 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo; + return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 30533a66f5..1d86f3a012 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -10,9 +10,11 @@ =20 # Fields: %rs1 15:5 +%rs2 20:5 =20 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 +@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 =20 # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 @@ -36,3 +38,10 @@ th_icache_iva 0000001 10000 ..... 000 00000 0001011 @= sfence_vm th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 + +# XTheadSync +th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s +th_sync 0000000 11000 00000 000 00000 0001011 +th_sync_i 0000000 11010 00000 000 00000 0001011 +th_sync_is 0000000 11011 00000 000 00000 0001011 +th_sync_s 0000000 11001 00000 000 00000 0001011 --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/mM0RV3PefqaiI7iAU8sksvWno5KVWr8UtNXABgTCGU=; b=JRfWCnVBw+VmCTOyw/2wuflcE+z31JaaqzfWi3lsDRznLUcPknn8vihuJpohdR32Ja UUt2p2PxU2GxH3qQmlCQzhShV5wDksFcv8G9Gd39YvA7ikuNtMVvu06754zcKoCTuG21 JloIBWhIhjr6fjSL2Fx0hCZVE/fZbKj+dduBT0MRQAHusOlDsH/2oCRxyv5qCBDSobNB 98KKLf/kUOaCMu7IEPsi43gI6EKxSSoAr3SjOEBAENDdgSvAiX7agEd4x+g7V2bCfw8g 3SDfy7rCkXYuaE7d3OHRZVlFWZ2Jdv6NrqBHKpYvuY3R8mAR4vENNCDWguMR59ytfVWw B89A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/mM0RV3PefqaiI7iAU8sksvWno5KVWr8UtNXABgTCGU=; b=McKsjeARHcgupHtDB5T3SUd3dPr0GrggGauPwR2TA2QC9u7yTAI7u57K/3Wmx3zwld qoEDa3M1vOmv/gbMVuZPP4kX9cz88u8CwiP3RQwkXsrqWsH0l2IpKbYO6UrHefKGsTTY hGrFBOSqxEQUmY+sCkMRbbVO8jejKACaCx78U5klzRQOJau5FsZTtaZa8jypwtFbOiG5 xkJUVHezKQNSaxpDQT25tQ1G2dg/xn7qEpQ3WF8AEdyNxTnelGUNUU+BBv8oLaMBIV/I ifS8CjdH30lgM56+wu7t0LLcAk50ouq7zMJeCSBBmraxx+g0f+IbhPPw/dH9MTvrD9U2 FLuQ== X-Gm-Message-State: AO0yUKX8vHNF0YSM+8W1FxvYA/JAuBwFwYoc7KTmO7QFl1iBeTQqgDn7 J1KPZNLQOMdlOLBdeT9BPs5UKw== X-Google-Smtp-Source: AK7set+NIYUqDfnOIHlAgJjF1W4ZdoiUQZPMusxNk9m929nAZLmTZT+olfyP7MkhOkGlB8ZyGVi5sA== X-Received: by 2002:a5d:4352:0:b0:2be:12a8:9f75 with SMTP id u18-20020a5d4352000000b002be12a89f75mr199359wrr.55.1675196421790; Tue, 31 Jan 2023 12:20:21 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 03/14] RISC-V: Adding XTheadBa ISA extension Date: Tue, 31 Jan 2023 21:20:02 +0100 Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196510951100003 From: Christoph M=C3=BCllner This patch adds support for the XTheadBa ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 39 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 22 ++++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f76639845d..dd5ff82f22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), @@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), =20 /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ea00586436..f1f7795bd5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { uint64_t mimpid; =20 /* Vendor-specific custom extensions */ + bool ext_xtheadba; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index f35bf6ea89..a6fb8132a8 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -16,6 +16,12 @@ * this program. If not, see . */ =20 +#define REQUIRE_XTHEADBA(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadba) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -28,6 +34,39 @@ } \ } while (0) =20 +/* XTheadBa */ + +/* + * th.addsl is similar to sh[123]add (from Zba), but not an + * alternative encoding: while sh[123] applies the shift to rs1, + * th.addsl shifts rs2. + */ + +#define GEN_TH_ADDSL(SHAMT) \ +static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t =3D tcg_temp_new(); \ + tcg_gen_shli_tl(t, arg2, SHAMT); \ + tcg_gen_add_tl(ret, t, arg1); \ + tcg_temp_free(t); \ +} + +GEN_TH_ADDSL(1) +GEN_TH_ADDSL(2) +GEN_TH_ADDSL(3) + +#define GEN_TRANS_TH_ADDSL(SHAMT) \ +static bool trans_th_addsl##SHAMT(DisasContext *ctx, \ + arg_th_addsl##SHAMT * a) \ +{ \ + REQUIRE_XTHEADBA(ctx); \ + return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \ +} + +GEN_TRANS_TH_ADDSL(1) +GEN_TRANS_TH_ADDSL(2) +GEN_TRANS_TH_ADDSL(3) + /* XTheadCmo */ =20 static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0657a4bea2..4683562ecf 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribut= e__((__unused__))) =20 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 1d86f3a012..b149f13018 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -2,6 +2,7 @@ # Translation routines for the instructions of the XThead* ISA extensions # # Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu # # SPDX-License-Identifier: LGPL-2.1-or-later # @@ -9,12 +10,33 @@ # https://github.com/T-head-Semi/thead-extension-spec/releases/latest =20 # Fields: +%rd 7:5 %rs1 15:5 %rs2 20:5 =20 +# Argument sets +&r rd rs1 rs2 !extern + # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# XTheadBa +# Instead of defining a new encoding, we simply use the decoder to +# extract the imm[0:1] field and dispatch to separate translation +# functions (mirroring the `sh[123]add` instructions from Zba and +# the regular RVI `add` instruction. +# +# The only difference between sh[123]add and addsl is that the shift +# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add). +# +# Note that shift-by-0 is a valid operation according to the manual. +# This will be equivalent to a regular add. +add 0000000 ..... ..... 001 ..... 0001011 @r +th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r +th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r +th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r =20 # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GE6UHNfhTt3OeATwdmkz/K6JNViPPGH9KAVxcrptl/o=; b=aG6zsrqSacRmDZSpoKPNmcA2ljr6g4lQHWIGg4pjNOrd8aIiO9C331T8bSbO5oL+kr 7bO9Cdpx3Q9C0/jUtWDtMUbmFVGbccr7g42HMpNELOvhHoQzrIiDTswNRqCEJQmkrp0d KqDu0o08+a7+H5erv/u6xETzWyDO8XwmbpQrAr1gq+gsFccVxnei+Niv9Lw2fTRj2HoV Tmc9adr9EpNUpX/p/mZmnPnTYQ7psl52b9CheSfahvayGbHkzZBqeKl1Q6pw6WuCowBz DaPLCSMQuAPzxwRCRpbTNBJNWWkA8s4vJvIDLTxjp2f7kTBNuzpvyKfh2L0IDkgTPrzY V4Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GE6UHNfhTt3OeATwdmkz/K6JNViPPGH9KAVxcrptl/o=; b=otYh5+rprynSC9A3hyWFShVlNadISGhrACioNFssnfiWD3NDo1nDxb+3MapkU+9ifA Oxz0i96qmGAps2yn3eC4Y8ndWFB0/atFcrq4zC+2FPaMg/w/QuOpQlgJKgDEM1zKlEqT WydxE/AMY8B3DUvC3JtszKdNMoW7aMINteslpprYsF9hN80BjDNrkJaW+b8whS+4tj+s Z5sjL0FsIrrv0I6vJs6Y2Rcv24+X77yyrYNgd6LtorTYvsl1/mfZAaCO/cFknBmF5w8j xRc9WJ1CQmhXuJmDHJTMZqrZAGZlvdkRKh/fPzY6hRlhsp1Vlp967dOSXq5GGLiG2ekw 1FVQ== X-Gm-Message-State: AO0yUKU+Ja9vTpGh+AfQWDe/Ax8WZWz5myZ+lFtIJWZCCDqiPrO6iXwE U1C2DFRQNGa8paLNYIhC7R4k/Q== X-Google-Smtp-Source: AK7set+b08t/Gss3dRwsgrUUP0aI6250T0mKBHg4P6zST5ACHZg2XPwQvlCfkIgOzdF4vc9djb9xsw== X-Received: by 2002:a05:600c:3797:b0:3d9:f769:2115 with SMTP id o23-20020a05600c379700b003d9f7692115mr570353wmr.26.1675196423270; Tue, 31 Jan 2023 12:20:23 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 04/14] RISC-V: Adding XTheadBb ISA extension Date: Tue, 31 Jan 2023 21:20:03 +0100 Message-Id: <20230131202013.2541053-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196560553100003 From: Christoph M=C3=BCllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Make implementation compatible with RV32. - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 124 +++++++++++++++++++++ target/riscv/translate.c | 4 +- target/riscv/xthead.decode | 20 ++++ 5 files changed, 149 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dd5ff82f22..def27a53f2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), + ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), @@ -1092,6 +1093,7 @@ static Property riscv_cpu_extensions[] =3D { =20 /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), + DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f1f7795bd5..be86c2fb95 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { =20 /* Vendor-specific custom extensions */ bool ext_xtheadba; + bool ext_xtheadbb; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index a6fb8132a8..ebfab90dd9 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADBB(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbb) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -67,6 +73,124 @@ GEN_TRANS_TH_ADDSL(1) GEN_TRANS_TH_ADDSL(2) GEN_TRANS_TH_ADDSL(3) =20 +/* XTheadBb */ + +/* th.srri is an alternate encoding for rori (from Zbb) */ +static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_rotri_tl, gen_roriw, NULL); +} + +/* th.srriw is an alternate encoding for roriw (from Zbb) */ +static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a) +{ + REQUIRE_XTHEADBB(ctx); + REQUIRE_64BIT(ctx); + ctx->ol =3D MXL_RV32; + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL); +} + +/* th.ext and th.extu perform signed/unsigned bitfield extraction */ +static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a, + void (*f)(TCGv, TCGv, unsigned int, unsigned = int)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv source =3D get_gpr(ctx, a->rs1, EXT_ZERO); + + if (a->lsb <=3D a->msb) { + f(dest, source, a->lsb, a->msb - a->lsb + 1); + gen_set_gpr(ctx, a->rd, dest); + } + return true; +} + +static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl); +} + +static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_bfextract(ctx, a, tcg_gen_extract_tl); +} + +/* th.ff0: find first zero (clz on an inverted input) */ +static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + + int olen =3D get_olen(ctx); + TCGv t =3D tcg_temp_new(); + + tcg_gen_not_tl(t, src1); + if (olen !=3D TARGET_LONG_BITS) { + if (olen =3D=3D 32) { + gen_clzw(dest, t); + } else { + g_assert_not_reached(); + } + } else { + gen_clz(dest, t); + } + + tcg_temp_free(t); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_ff0(ctx, a, EXT_NONE); +} + +/* th.ff1 is an alternate encoding for clz (from Zbb) */ +static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); +} + +static void gen_th_revw(TCGv ret, TCGv arg1) +{ + tcg_gen_bswap32_tl(ret, arg1, TCG_BSWAP_OS); +} + +/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */ +static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a) +{ + REQUIRE_XTHEADBB(ctx); + + return gen_unary_per_ol(ctx, a, EXT_NONE, tcg_gen_bswap_tl, gen_th_rev= w); +} + +/* th.revw is a sign-extended byte-swap of the lower word */ +static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a) +{ + REQUIRE_XTHEADBB(ctx); + REQUIRE_64BIT(ctx); + return gen_unary(ctx, a, EXT_NONE, gen_th_revw); +} + +/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */ +static void gen_th_tstnbz(TCGv ret, TCGv source1) +{ + gen_orc_b(ret, source1); + tcg_gen_not_tl(ret, ret); +} + +static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); +} + /* XTheadCmo */ =20 static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4683562ecf..387ef0ad8b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,8 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribut= e__((__unused__))) =20 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadsync; + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || + ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index b149f13018..8cd140891b 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -13,14 +13,23 @@ %rd 7:5 %rs1 15:5 %rs2 20:5 +%sh5 20:5 +%sh6 20:6 =20 # Argument sets &r rd rs1 rs2 !extern +&r2 rd rs1 !extern +&shift shamt rs1 rd !extern +&th_bfext msb lsb rs1 rd =20 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 %r= s1 %rd =20 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -38,6 +47,17 @@ th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r =20 +# XTheadBb +th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext +th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext +th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2 +th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2 +th_srri 000100 ...... ..... 001 ..... 0001011 @sh6 +th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5 +th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 +th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 +th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ieN/2+dlX6IBcad+vE1WfHWnV34lFlP6rY4YQzmk0Bw=; b=tKE+WA411KjhtT7sqZ8CqJEyjl2J78ypoCPw+HtygZxlmTc3LU24a+5kMLl2Og8vt9 Yic0AvqW9wyLgXqio0FMB+KtHfquHx/wWxe32VxMNF/MgTE6NEaleN2dQhNd6rwyCIz0 hIKJm+Mrs2j6gnTN1bfqUUKd27DPEE+ROPixrBDqv5LsGdT9jJmUDou8iuEZAD0dDupa pUY1b2y5q0ajpJVB6TgJLRNGw3LYakL0vpOMuVfwPM7VwTunpXW8QAZ5D/+jmU2J3PGU bj6th5/Y03DtUTIarMzYFkIAegX4z+648JcUk8czYDRcybOuZb4gTw9hQOrMbV/HwL5g Lrwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ieN/2+dlX6IBcad+vE1WfHWnV34lFlP6rY4YQzmk0Bw=; b=xiNNR3vKQre3vSKp0lVZ20vzijpRi1KmpgzoW91y4uCr/JmZWDzP4GTWuBS5iaVGoT lNITt6+VFndBbSpsbxjeQHjCN8MV7+LimrAVv71/Ctt7jqg0BGvREilcpsJWi+ium+/z YHEctQiaAc0nD4B5zxupMv/K5DazN6e/HxGWjeIhVIvyT00Epjs41qCtxoDM6fFw/e7I 705INXZAA90Bli5Y7x16m3Pu25Rwgk6OPlA0t+TGmZIj9tAMU5iYNxmJeJeDrUaJx9T2 NYRZyEPVWXQE2rVECkJpMdCQAoG9IHIWeaCmklhd7dIZLib1a2Fhqq/TLyWfCIXwGTM6 9Eyw== X-Gm-Message-State: AO0yUKUHhQ09ZMM1Cwb3yzk4YkGIQ5z+Pnfz/QN+HvzewWUIgJr3801V AwIbz+RQlRuxSGph8h66zg05Cw== X-Google-Smtp-Source: AK7set/Jo9cCsvqpY0uO68OZSRIB7XQjaahVCkuHIiqRhDi9gGSeVVUXH1MdaP79b0QrKquXrxOwjQ== X-Received: by 2002:a05:6000:2aa:b0:2bf:edc4:9cf4 with SMTP id l10-20020a05600002aa00b002bfedc49cf4mr5359525wry.58.1675196424733; Tue, 31 Jan 2023 12:20:24 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 05/14] RISC-V: Adding XTheadBs ISA extension Date: Tue, 31 Jan 2023 21:20:04 +0100 Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196544403100007 From: Christoph M=C3=BCllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++ target/riscv/translate.c | 3 ++- target/riscv/xthead.decode | 3 +++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index def27a53f2..c541924214 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), + ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), @@ -1094,6 +1095,7 @@ static Property riscv_cpu_extensions[] =3D { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index be86c2fb95..876eaebd0e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -475,6 +475,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; + bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index ebfab90dd9..bc1605445d 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -28,6 +28,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADBS(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbs) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_th_= tstnbz *a) return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); } =20 +/* XTheadBs */ + +/* th.tst is an alternate encoding for bexti (from Zbs) */ +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) +{ + REQUIRE_XTHEADBS(ctx); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); +} + /* XTheadCmo */ =20 static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 387ef0ad8b..880324e617 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -133,7 +133,8 @@ static bool always_true_p(DisasContext *ctx __attribut= e__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || - ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8cd140891b..8494805611 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 =20 +# XTheadBs +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675196510; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F34s/BqR7DZslK/seY6TWRFLpbaO1IVWnnk22jxZxIM=; b=i7MTBMV5ijPJTfMQvMJs652ABUu4vxibdje99j9XV2XXDBmizZroNfwDjidunXEt42 ApYL5KKZskZ2xp5Ft3M0csaYaT6JiqlTo4XlOHjbMP0YDDi0PbXLC/z5cKDuX2iNvbFL PC6jmC/fO/BDt9u7uzSL9TOpGBv9kge0sPrpMkTmRAu0L+Ck2uoq1ftA3S5l3lEP88Wc zpvChrk5J2NpcGFf9BYWpBDf1HXPSfGGF4lPzMdWYAzMG/LTnkVpDNnDn88rb9fEYcSB K22OtgotFU80mmDM6vuajeh7kq5hkTDRJTCq4ZjEKkXtMFuuX9X6MgEFFxKHw9bmTO9p FhOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F34s/BqR7DZslK/seY6TWRFLpbaO1IVWnnk22jxZxIM=; b=6Tw9afKDPlgxb2KMlYLmzQdOZ+z+vubPbQP5Lo7BBWc1ksHeO+k6RoMdVZwQxXM3mV lmrP2L1jKXv80o2plsxCCQRaughTg8js9f/ze/aWrOF0sABnro+0HnQVLE+5eMf/eUkc Eo17Ary+8SLyAHpmZkXYUDkr7Av4flVChT6AFJhHeohPOzm+X/Q7Ck3k69MIc4AsxhQP kxhtVYGbmjf2PLabSjuRnVdmsy+9pBkFdYpAJLKZM/tuV2SV7/E1hi7gLkv2lUlLqSH0 TUMrE0pREJ0gd1okFrOa9T9PfGxTDwdrX7xQ/WUVpPh83sKbOLoBHzQJ2TxM0Je4XBup WUmg== X-Gm-Message-State: AO0yUKUltHAwrONVJ9R6CUg5F+5Fq0X73RDws3Iw6FreWpnzgYl51Tcm 0T5mX03ondv9q0QfJYEUcMrIIg== X-Google-Smtp-Source: AK7set98i2broAuJnYbNRZQLse9iVea+QOzEmLVBCjiooK7Yf7J3WGe9n1hgsg0U9bXRQp0rykZujw== X-Received: by 2002:a05:6000:104:b0:2c2:6541:7b00 with SMTP id o4-20020a056000010400b002c265417b00mr221880wrx.54.1675196426821; Tue, 31 Jan 2023 12:20:26 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 06/14] RISC-V: Adding XTheadCondMov ISA extension Date: Tue, 31 Jan 2023 21:20:05 +0100 Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196510955100004 From: Christoph M=C3=BCllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix invalid use of register from dest_gpr() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 4 +++ 5 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c541924214..13b065bc68 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -113,6 +113,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), + ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; @@ -1097,6 +1098,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 876eaebd0e..a313e025e7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -477,6 +477,7 @@ struct RISCVCPUConfig { bool ext_xtheadbb; bool ext_xtheadbs; bool ext_xtheadcmo; + bool ext_xtheadcondmov; bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index bc1605445d..089b51f468 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -40,6 +40,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADCONDMOV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadcondmov) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -264,6 +270,35 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQU= IRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) =20 +/* XTheadCondMov */ + +static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv old =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv dest =3D dest_gpr(ctx, a->rd); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +/* th.mveqz: "if (rs2 =3D=3D 0) rd =3D rs1;" */ +static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a) +{ + REQUIRE_XTHEADCONDMOV(ctx); + return gen_th_condmove(ctx, a, TCG_COND_EQ); +} + +/* th.mvnez: "if (rs2 !=3D 0) rd =3D rs1;" */ +static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) +{ + REQUIRE_XTHEADCONDMOV(ctx); + return gen_th_condmove(ctx, a, TCG_COND_NE); +} + /* XTheadSync */ =20 static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 880324e617..4f4c09cd68 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8494805611..a8ebd8a18b 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -84,6 +84,10 @@ th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 =20 +# XTheadCondMov +th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r +th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4ro3zV/8frUQCS512EVPsuQE0kUlUm+PFZm4/WXtpfo=; b=VLkNOPhz8P/4OebgzbV5HUW2vARkuhhL9aV6gOxW7S6hro7lSlfV2BKj9BEJmZ7tn1 tktBcU/CLlruVyDTlnEcrbctGwuyzkLa+XsjEiq3FUH6y+r0asGsqHeYQwlBrtRJahlH Q+dKCe42a+u5SW4fbEnvG67Y8XRQx8v7PXyEi5K3X/+uqz9H7M0dtnxlsIM0Ch7Qcer5 zlIdQHFe/CVYWizFgnwWCYbHD5KlgVdq/5zHgU0dNnVR7XFcGthHQ63U4ADzLwDOMgvu Kc9oycdgLosuqXtAH3FiIpQTxVs/oQbEsyK9ZhtRM/DO3LPDYZkMOvqeLOQQODtEkzk0 QM7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4ro3zV/8frUQCS512EVPsuQE0kUlUm+PFZm4/WXtpfo=; b=ba2azbC8Zur9QFr1wbifbd9tcmIFdoxwXWFZV7GEdnr6bjWKRP2FG9Q4QWmrjQUvgK gmNgKowO9TR7zU8NSkQ/IIMFoD5BYy5Sa4eB31k7XDbET+yfH07uUN1Noj6jRF4TmcEa k8ewzcruNhVFqlxUX4dOOwE96Uu1OPF110nLYEIG7DQAZoouSu12mJluR0zDykX0nfQq 8DitIQH6CZyT02MvPkkFuhq5BkNXXTS7Kr2dCFI/h/q+RrVWmJLsXv73IIP7jncWvqnw wZPpg3vXg8veMIicuZLA0tV6Omcr73nnUDcWT86Q1kBeI9W/rqG86KmjgXC4h8yV1tGu hsAg== X-Gm-Message-State: AO0yUKWJBv9NbynADlnKNOTVuWEl+Xnhp24Y1SYsoqGF0wbhEUFutdD/ ub9XzH9OnWOdNJl9x9FU3TqC6A== X-Google-Smtp-Source: AK7set9NHU/OGthtN7oWiffRBDsu8+jMmu1J+/KiJ5gB7edaABLJr64Hibu8WYe5dyDggP5KUIUzAA== X-Received: by 2002:adf:e181:0:b0:2bd:c4ea:3b59 with SMTP id az1-20020adfe181000000b002bdc4ea3b59mr343493wrb.0.1675196428299; Tue, 31 Jan 2023 12:20:28 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Date: Tue, 31 Jan 2023 21:20:06 +0100 Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196542388100003 From: Christoph M=C3=BCllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 8 +++ 5 files changed, 96 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13b065bc68..88da4de14d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), + ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; @@ -1099,6 +1100,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a313e025e7..830b20558c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadmac; bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 089b51f468..31a4034927 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADMAC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmac) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -299,6 +305,83 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_m= veqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } =20 +/* XTheadMac */ + +static bool gen_th_mac(DisasContext *ctx, arg_r *a, + void (*accumulate_func)(TCGv, TCGv, TCGv), + void (*extend_operand_func)(TCGv, TCGv)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src0 =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv tmp =3D tcg_temp_new(); + + if (extend_operand_func) { + TCGv tmp2 =3D tcg_temp_new(); + extend_operand_func(tmp, src1); + extend_operand_func(tmp2, src2); + tcg_gen_mul_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + } else { + tcg_gen_mul_tl(tmp, src1, src2); + } + + accumulate_func(dest, src0, tmp); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(tmp); + + return true; +} + +/* th.mula: "rd =3D rd + rs1 * rs2" */ +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.mulah: "rd =3D sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); +} + +/* th.mulaw: "rd =3D sext.w(rd + rs1 * rs2)" */ +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.muls: "rd =3D rd - rs1 * rs2" */ +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + +/* th.mulsh: "rd =3D sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); +} + +/* th.mulsw: "rd =3D sext.w(rd - rs1 * rs2)" */ +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + /* XTheadSync */ =20 static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4f4c09cd68..e5a57a8516 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac = || + ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index a8ebd8a18b..696de6cecf 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -88,6 +88,14 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r =20 +# XTheadMac +th_mula 00100 00 ..... ..... 001 ..... 0001011 @r +th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r +th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r +th_muls 00100 01 ..... ..... 001 ..... 0001011 @r +th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r +th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xm+YXRWYUm4OQJWfKMIGdiAhga6zqnD1FiBxxxopHlo=; b=ovXplVjiGoziJI6gEwJsABcDiXLKd51jg0L8x9pRxFMJX/bUR33MGhwpy0qVbl/RPZ IKa54glgf7GVLlQg6IwF/TIZ4eXp7D2xmdKBlFycg7fwDOxC7vl4qKfQozziBH7jyxr3 5e1sNq+AY4ex70pkAlcnhgNM1WSeS1sWgZhea+46iugw8HcoNC/6W543UNjlU1rLpuRi E3a2ZCQSOk/8JJmQcyiJ7bfmuyTxFy0q88magUDnHIVl2VxNfkXorYcNH7LVlfWcBOsz nT/zx3gT/f8fy/RKWvPTrLiuHkUwBGaEFV0Ns+JGxlwmNUFoI6WMp7VZyJ2/KdXHq6RK UHvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xm+YXRWYUm4OQJWfKMIGdiAhga6zqnD1FiBxxxopHlo=; b=d+rLXsQ6eE0wHX91D+CWXJx56f2wJcvkDiDhwwh+x9p1ZauqM9vTT4AR9QjwhEHjXK YO4WSkcmE8Pjkup+ByCraiQPZs+gtHlawJNYxtSJrdZOZU5VGx7NeX2FtEWmUD6AUvTs F2Hv0IV/jx4B2xGdIGd2IXwh6lxuuxDC3CsxO2oeRl1vD2qQkzvDhXdHSYuDeAlFY0ma nWsmQvDQfEU0S7Lja4Khw5DBBBv49OW395rDkqYG7r8h2/nF419Ma2BRQo1YltbSInoM z7jAk3daFQBwp3qShvfsLfDBr0BtkNmVO5Gw2AGbWvZMGKQeD9YDh/70PKVSbEz64/Mq Mpag== X-Gm-Message-State: AO0yUKVJ4EVglGPzJC5rjVxlEHPKHLBM5vdXfm48MhBznxA3CJdYWZTU shVOtDkgA5V8R/LOlCKVHiwlqQ== X-Google-Smtp-Source: AK7set+/QZby1lBNTdNJqzl0KDyJY+1jEP+Cdc1fNWhP1GooVW05PqRmcKiAKgTdRhGsev4QklmvNw== X-Received: by 2002:a5d:510f:0:b0:2bf:ae4b:4cbf with SMTP id s15-20020a5d510f000000b002bfae4b4cbfmr230544wrt.55.1675196429996; Tue, 31 Jan 2023 12:20:29 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 08/14] RISC-V: Adding T-Head MemPair extension Date: Tue, 31 Jan 2023 21:20:07 +0100 Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196536512100003 From: Christoph M=C3=BCllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_address() to calculate addresses Changes in v4: - Don't translate in case of overlapping registers - Use temporaries to avoid unexpected behaviour in case of exceptions - There have also been clarifications in the specification Changes in v5: - Use memop_size() instead of hard coded constants target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 92 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 13 +++ 5 files changed, 109 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 88da4de14d..b7047d139d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), + ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xthea= dmempair), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; @@ -1101,6 +1102,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), + DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 830b20558c..38e80d44d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -479,6 +479,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadmac; + bool ext_xtheadmempair; bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 31a4034927..f1bd0dbad5 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADMEMPAIR(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmempair) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -382,6 +388,92 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_m= ulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } =20 +/* XTheadMemPair */ + +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + if (a->rs =3D=3D a->rd1 || a->rs =3D=3D a->rd2 || a->rd1 =3D=3D a->rd2= ) { + return false; + } + + TCGv t1 =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv addr1 =3D tcg_temp_new(); + TCGv addr2 =3D tcg_temp_new(); + int imm =3D a->sh2 << shamt; + + addr1 =3D get_address(ctx, a->rs, imm); + addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); + + tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd1, t1); + gen_set_gpr(ctx, a->rd2, t2); + + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_loadpair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TESL, 3); +} + +static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TEUL, 3); +} + +static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memo= p, + int shamt) +{ + if (a->rs =3D=3D a->rd1 || a->rs =3D=3D a->rd2 || a->rd1 =3D=3D a->rd2= ) { + return false; + } + + TCGv data1 =3D get_gpr(ctx, a->rd1, EXT_NONE); + TCGv data2 =3D get_gpr(ctx, a->rd2, EXT_NONE); + TCGv addr1 =3D tcg_temp_new(); + TCGv addr2 =3D tcg_temp_new(); + int imm =3D a->sh2 << shamt; + + addr1 =3D get_address(ctx, a->rs, imm); + addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); + + tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); + + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_storepair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_storepair_tl(ctx, a, MO_TESL, 3); +} + /* XTheadSync */ =20 static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e5a57a8516..f383e69db3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,7 +135,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac = || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 696de6cecf..ff2a83b56d 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -11,16 +11,21 @@ =20 # Fields: %rd 7:5 +%rd1 7:5 +%rs 15:5 %rs1 15:5 +%rd2 20:5 %rs2 20:5 %sh5 20:5 %sh6 20:6 +%sh2 25:2 =20 # Argument sets &r rd rs1 rs2 !extern &r2 rd rs1 !extern &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd +&th_pair rd1 rs rd2 sh2 =20 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -30,6 +35,7 @@ @th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd @sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 %r= s1 %rd +@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2= %sh2 =20 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -96,6 +102,13 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011= @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r =20 +# XTheadMemPair +th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair +th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair +th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aSU3bmaSh6WmNi3SOC/Mq3el8z9EChFXj1EuvaUe/j0=; b=dCgg+3IaApeuOxPh2tJYSYvlaaP46mrHRYVWKupPKQlT+zvLXPq5tTKc4MhDHfg5R4 BgWVvrK3gNQAXWAAVjeB8rTwo6xOTpvVtc0OtHiSGux3QadGVxHz6WxhIhPUjEMnk4jE iMzLdf55lJtJ5Zsp3fLzSeHsqpy7cMVDnV33nLt3lp3KaGWJrK3pI5OBoWGyS55aXRQ/ KsAIWoxoVWnMbvrrZe783PJuot/XDcEfzilgh5BKWMi2zcbopNwPk9P5hUlgO92DnYAy m15Z9tn4qofebrNsFr1I3sO+r0p8Ony+tb2N3ejtedPy41W8VT4aXMFw70ZYl2ohcNPz Jg/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aSU3bmaSh6WmNi3SOC/Mq3el8z9EChFXj1EuvaUe/j0=; b=HCnHMGdwd2OMA1Vu9AOE349P7WZLPwdACGAD38cnVdmIMQzK9o9hEPML5WXw6nFVCH NVHZJvdhgsOc5IDnLQ9gurWoGrwSdN4CMhA/RyT8lc/sA1w3TgqF9pToDpWZkqgOg0gL TfFOymqelDoaSSAvWfR/iYjQ8ky5BmeWpRRsRbWk9pEUn+nUmREcv3r28w18X5oy31ki ZF+vPa5RUv2gVYNd25G9taN6t1nFY6RUnLS+r3r+15LiHs63YIkHhUVo0JA8IdGN2A92 ISSPgfhjcuVwjxU0zFxOe2QTouCQQwKbVrlqv58MnHMoF6IFALDmWvM6k2B4oNaBaoqh wRWA== X-Gm-Message-State: AO0yUKWPYMvdwbxOsY6wbc+pGj/iUPMR6S3NLCFUphGmmWqo00q+fObq w1xalPX/rohbHS6ch9xVQsfbFN46ApFZhNgg X-Google-Smtp-Source: AK7set91FUt7srxZf1ypv/aub2xTcUcJEt/V/c+exEDJQIWORuYMLPEpM2KRRSaQGmA3n7g4mMhdog== X-Received: by 2002:a5d:6d05:0:b0:2bf:ee65:b0b0 with SMTP id e5-20020a5d6d05000000b002bfee65b0b0mr343346wrq.41.1675196431435; Tue, 31 Jan 2023 12:20:31 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 09/14] RISC-V: Adding T-Head MemIdx extension Date: Tue, 31 Jan 2023 21:20:08 +0100 Message-Id: <20230131202013.2541053-10-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196562485100007 From: Christoph M=C3=BCllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Avoid signed-bitfield-extraction by using signed immediate field imm5 - Use get_address() to calculate addresses - Introduce helper get_th_address_indexed for rs1+(rs2<cfg_ptr->ext_xtheadmemidx) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMEMPAIR(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmempair) { \ return false; \ @@ -64,6 +70,30 @@ } \ } while (0) =20 +/* + * Calculate and return the address for indexed mem operations: + * If !zext_offs, then the address is rs1 + (rs2 << imm2). + * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2, + int imm2, bool zext_offs) +{ + TCGv src2 =3D get_gpr(ctx, rs2, EXT_NONE); + TCGv offs =3D tcg_temp_new(); + + if (zext_offs) { + tcg_gen_extract_tl(offs, src2, 0, 32); + tcg_gen_shli_tl(offs, offs, imm2); + } else { + tcg_gen_shli_tl(offs, src2, imm2); + } + + TCGv addr =3D get_address_indexed(ctx, rs1, offs); + + tcg_temp_free(offs); + return addr; +} + /* XTheadBa */ =20 /* @@ -388,6 +418,363 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_= mulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } =20 +/* XTheadMemIdx */ + +/* + * Load with memop from indexed address and add (imm5 << imm2) to rs1. + * If !preinc, then the load address is rs1. + * If preinc, then the load address is rs1 + (imm5) << imm2). + */ +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + if (a->rs1 =3D=3D a->rd) { + return false; + } + + int imm =3D a->imm5 << a->imm2; + TCGv addr =3D get_address(ctx, a->rs1, preinc ? imm : 0); + TCGv rd =3D dest_gpr(ctx, a->rd); + TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + tcg_gen_addi_tl(rs1, rs1, imm); + gen_set_gpr(ctx, a->rd, rd); + gen_set_gpr(ctx, a->rs1, rs1); + + tcg_temp_free(addr); + return true; +} + +/* + * Store with memop to indexed address and add (imm5 << imm2) to rs1. + * If !preinc, then the store address is rs1. + * If preinc, then the store address is rs1 + (imm5) << imm2). + */ +static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + int imm =3D a->imm5 << a->imm2; + TCGv addr =3D get_address(ctx, a->rs1, preinc ? imm : 0); + TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + tcg_gen_addi_tl(rs1, rs1, imm); + gen_set_gpr(ctx, a->rs1, rs1); + + tcg_temp_free(addr); + return true; +} + +static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_SB, true); +} + +static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_UB, false); +} + +static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_UB, true); +} + +static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_SB, true); +} + +/* + * Load with memop from indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv rd =3D dest_gpr(ctx, a->rd); + TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd, rd); + + return true; +} + +/* + * Store with memop to indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + + return true; +} + +static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_SB, false); +} + +static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_UB, false); +} + +static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_SB, false); +} +static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_SB, true); +} + +static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_UB, true); +} + +static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_SB, true); +} + /* XTheadMemPair */ =20 static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f383e69db3..a979d43a6a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,7 +135,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac = || - ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempa= ir || + ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ @@ -597,6 +598,24 @@ static TCGv get_address(DisasContext *ctx, int rs1, in= t imm) return addr; } =20 +/* Compute a canonical address from a register plus reg offset. */ +static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) +{ + TCGv addr =3D temp_new(ctx); + TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); + + tcg_gen_add_tl(addr, src1, offs); + if (ctx->pm_mask_enabled) { + tcg_gen_andc_tl(addr, addr, pm_mask); + } else if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + if (ctx->pm_base_enabled) { + tcg_gen_or_tl(addr, addr, pm_base); + } + return addr; +} + #ifndef CONFIG_USER_ONLY /* The states of mstatus_fs are: * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index ff2a83b56d..69e40f22dc 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -17,8 +17,10 @@ %rd2 20:5 %rs2 20:5 %sh5 20:5 +%imm5 20:s5 %sh6 20:6 %sh2 25:2 +%imm2 25:2 =20 # Argument sets &r rd rs1 rs2 !extern @@ -26,6 +28,8 @@ &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd &th_pair rd1 rs rd2 sh2 +&th_memidx rd rs1 rs2 imm2 +&th_meminc rd rs1 imm5 imm2 =20 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -36,6 +40,8 @@ @sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 %r= s1 %rd @th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2= %sh2 +@th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %r= s2 %imm2 +@th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %i= mm5 %imm2 =20 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -102,6 +108,54 @@ th_muls 00100 01 ..... ..... 001 ..... 000101= 1 @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r =20 +# XTheadMemIdx +th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbia 00011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbib 00001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuia 10011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuib 10001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc + +th_lrd 01100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrw 01000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrwu 11000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrh 00100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrhu 10100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrb 00000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrbu 10000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srh 00100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srb 00000 .. ..... ..... 101 ..... 0001011 @th_memidx + +th_lurd 01110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurw 01010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurwu 11010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurh 00110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurhu 10110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurb 00010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurbu 10010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_surd 01110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surw 01010 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surh 00110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surb 00010 .. ..... ..... 101 ..... 0001011 @th_memidx + # XTheadMemPair th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OoP+nPrZ8X/E61rS0pZ6ZpAy4ylmkEAW2GcHPYOCEqI=; b=ixDt3dxpCO6blyBxBS0ciMutEyYhSTFm3haYvLAn8+aBZEnk8LVAj++JvzoWRL5Pbm pKqfmAUlG3ja2ZUO7Krjn+nwV1Ya1eyO1W0rsNpm48hQwXtMBh9dg4JvwUDNuedIc1Bt a+xANYGyeBY9oFLevflycJdguVddl6C3zBtTSwJdNi/qJIdnxiAzCW5ULvKPR+c8p8F5 6lVwO2Z0SOjrgp6jhrNvA92scR3wFGGNFnLCckd2saFazW6YWxiDq1MuohpEpY/br7F+ MX1+j8UDKm4zv8C6ZXCIKYAs752ZRoPtLwzTTfds8Mkxlvh5/OUnM9ts5m4KhhTOrN2C QzpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OoP+nPrZ8X/E61rS0pZ6ZpAy4ylmkEAW2GcHPYOCEqI=; b=hzJ5ianYN1DOFYWviiY3anFiirdWgZvcZiqYIvC2dHvHGbhGhqE5931iGbDHZ3y/HU NIy0zYRoLAYPuwSuyMiUxOcQJhTVpWANOjgdTa+n5qC1o0uVzAGYsZAtuGmv6I7yGijo oEDXO0Ily0jRiBJxXn++CmT2SKULOzmKbhw6+jVfEpCIJLEwYQ0u6PQ4P3S3A2eqyanO VbSWrYiHQ5acmXAthYoy6bZJPJAaoM0cjfFADlqAFlGvd8Vry/rRrA4/9gXSaVSpvehg Wwr9HVDL4p62l6yol6ZKY/+z92qAexMwM0J0q1p2dhKoxGsTnobdsbbj/uAcRo1MsZ5v VQEg== X-Gm-Message-State: AO0yUKWUql8ZMf7+060jcAl+IdvD4VkkVIJDFKAe5cQMtHyUGJ2Yo374 tpEgbQCotFw9cdDCRoDCJ46G0A== X-Google-Smtp-Source: AK7set/t0HOwKBIKDLBGTbVtRhCN0Xpo8FyJpxa8NraoJAjpR3WCHmoQ5UnxUfu6wFdt3JW0zhhrqQ== X-Received: by 2002:a05:600c:511d:b0:3db:3695:11b4 with SMTP id o29-20020a05600c511d00b003db369511b4mr5064232wms.33.1675196433178; Tue, 31 Jan 2023 12:20:33 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 10/14] RISC-V: Adding T-Head FMemIdx extension Date: Tue, 31 Jan 2023 21:20:09 +0100 Message-Id: <20230131202013.2541053-11-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196568559100007 From: Christoph M=C3=BCllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_th_address_indexed for address calculations target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 108 +++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 10 ++ 5 files changed, 123 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2d5a0881f1..5679e2cb83 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), + ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xthea= dfmemidx), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthead= memidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xthea= dmempair), @@ -1102,6 +1103,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), + DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, fal= se), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false= ), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d776fea760..5cc3011529 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadfmemidx; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 8167de0393..37373732f6 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADFMEMIDX(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmemidx) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -341,6 +347,108 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_= mveqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } =20 +/* XTheadFMem */ + +/* + * Load 64-bit float from indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv_i64 rd =3D cpu_fpr[a->rd]; + TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); + + tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); + if ((memop & MO_SIZE) =3D=3D MO_32) { + gen_nanbox_s(rd, rd); + } + + mark_fs_dirty(ctx); + return true; +} + +/* + * Store 64-bit float to indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memo= p, + bool zext_offs) +{ + TCGv_i64 rd =3D cpu_fpr[a->rd]; + TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); + + tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); + + return true; +} + +static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, true); +} + /* XTheadMac */ =20 static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a979d43a6a..216eaf9d12 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac = || + ctx->cfg_ptr->ext_xtheadcondmov || + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac = || ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempa= ir || ctx->cfg_ptr->ext_xtheadsync; } diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 69e40f22dc..81daf1d694 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -100,6 +100,16 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r =20 +# XTheadFMemIdx +th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx +th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yvHIRBCasGI/M7FOrkWVgk4VvqK1NIRoMsNprIYB95I=; b=BDko/+ssRjluYDfvKBYy0smVa0kz9wSGdnF99Zx7twGkCx0HfngosH1ne5KFp3PW0p PetLcKcxq22u5Ww3pGyYwrtThbsDvEviuz/rvsHhP0Z4UUNWSXpLWuaAmUDzrVtQzHca JiiG8h0FxJgqDJE4D2w3xgc6DL9nDojxnSa/FjKQHaAFUS1hTocSRLr6XQEaIBwvO005 eIjQOi6Zy3pd+MwycdsbVYn+02Vh88Bm4EQwIZ5AWdt6XZIeby3BoWDoUG7wQVZcyFK7 Fv2Hb6TYMbpF7Rw8ASd+QbbxyMNm00QdU+grsZsh5mUXvuDgpPwXOxTpzHhKgUkZP2d6 yxpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yvHIRBCasGI/M7FOrkWVgk4VvqK1NIRoMsNprIYB95I=; b=GgMP0gacNF/sjWpQd5X9SW5MFnxJb/BWZEjONKZtWx4WOeRto0EeGXgqDCl1NiygQH QAPFPu3hcNKdaiqIbRtt7hKjtaW4bvtjPfKYHf2Ht+ghHI6kjqkhAEzFC7WHO39+dvnL nzfsy+SQaDM88uc76HVLHtEXRit7uzANGOIjUwbilHFU3Y3tNF5PzccrLUPTM0S4/rtD it1Ubqh3bJRtnDSyo69Y3R7r3JAM4uMsUhBFBJMEtVx0ampT+pJpPn17rgoJlvQe3tvK e6L4I6yQBp14GhGKaGMPbUSUpP4IbiMXFrxJQ5P4JtOGxsoa8DYR3MUbnsNSn6zKvtR6 B+aQ== X-Gm-Message-State: AO0yUKUWpyJts0ymnFRaNSGPbrHl+7hnl0X6b4zy0id2WR5xXzErCVFk 1hV/K7ZycV6kKQBwu8IFpu6i/w== X-Google-Smtp-Source: AK7set8vfYp+x4QI1WlbuxSnLwDyUs9v98U5JH1WVfDdyc/tyiBnIuOOWB5DREF6vUUSRRbriAhfEQ== X-Received: by 2002:a05:600c:314d:b0:3dc:2039:1710 with SMTP id h13-20020a05600c314d00b003dc20391710mr25222101wmo.20.1675196434782; Tue, 31 Jan 2023 12:20:34 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Date: Tue, 31 Jan 2023 21:20:10 +0100 Message-Id: <20230131202013.2541053-12-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196566484100001 From: Christoph M=C3=BCllner There are no differences for floating point instructions in priv version 1.= 11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Acked-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5679e2cb83..3078556f1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -77,7 +77,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintp= ause), ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), - ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675196499; cv=none; d=zohomail.com; s=zohoarc; b=QiHkRiT1WHbR0gBDBgNVLiRSo8p46GiqciyPEOrIwg8r/N4y+oHU7f5U/8/d3yLshFKFrtoWeIaAIzeY6bUFUAQ0gv5cLSXVmL7brpgUIF1tFTei3rzt0CV3Ep1MNQDnPTPrQ2RyecLzqBaCI9gJwGuTFtk7XLF0wqPRXCcjfjM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675196499; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ygu0duwWgb07Jo+qlRVPI7Zizkm9Hcw3R3ZaXGJeNaI=; b=mpsnjbb4elTxpdAFP0vSpc2Akx12wUFsUy580TF6MHg/3bofaq5wXtcUW7iZHa70i5ea1NMCr83Xs+67nJROAl8bheeV8/0Bs8aiR25xOPwztIvW1Ob2+L47KetyxYshTk3h9l43eILL4rYbMZbheGqaIY6FioEqRFPOWoO7bOA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675196499914354.2799508523416; Tue, 31 Jan 2023 12:21:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pMx7e-000730-NI; Tue, 31 Jan 2023 15:20:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMx7Q-0006tl-Ck for qemu-devel@nongnu.org; Tue, 31 Jan 2023 15:20:40 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMx7N-0002io-75 for qemu-devel@nongnu.org; Tue, 31 Jan 2023 15:20:38 -0500 Received: by mail-wr1-x435.google.com with SMTP id m7so15349753wru.8 for ; Tue, 31 Jan 2023 12:20:36 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ygu0duwWgb07Jo+qlRVPI7Zizkm9Hcw3R3ZaXGJeNaI=; b=E22vbgmJzo8I+hieRTSX4rrt4eWDktifyXi5kb04kI+vE5iw8iNwcbwQbqFi/3bHyW aD7/uFay6CPtcQ9OrnZ5mM+8l53JU0UvSuRx8ccrpbH3vRBKv25Ah5Tlmx5Cg+wq7cDE biAELt3C+cz9bM59i90j6BFgtvfphg8ZcfzrD8yCToPJZtY/OFSpoyGn/XYsmn9h5/RG 6XjMNe1xobeZ7QHot47WQ084Q5kxh/ITd2VqsXpFNHuKKqaessG0Xzdrss/bJQC+cqr7 YQz1lW18ZljntBaCHjGLAGIvSk8v8qgvuAnVLT5dRBBdSyyVVNc26U2GZxb2cpxKioj5 goIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ygu0duwWgb07Jo+qlRVPI7Zizkm9Hcw3R3ZaXGJeNaI=; b=p18BYiO5iAzbG8CbKoz6WquSDA4dyAdmp0MQmf7pZD18jzxTQRg+ZLgz1i5iM+w8g+ av2ncD1dwa3JtPOaF74zoo40aVG0OLvZZWNYfsFsqJhYEryE3k+KvKVmFrX1inFsGN/Z a1G6myOlynT15XdeKM408IjiYGbRMx3Qs2I+SwSPRG6SXK+HNRkZgMaB4bQHdHo1Ozph fgiyo6y5eolyvTyEdIYAfLGa5KpFpW87uWCX49ijMMyAXs4LJei43U8NABTAgsreGi7Z VtVHVUvwjtRHR1hb3t2QbiHLjiWeaFEz+/AVhytyW0hNwFn79S26BCnrWRmngr4Vf8z2 qChw== X-Gm-Message-State: AO0yUKUWH1omEg1a0nlzAFe52RVFOY2/Z42rmx9j0cN+E3VnpWEh76ZR +TxW0uSHt4b73LrA8a2b456nTzMOhTTVZPrd X-Google-Smtp-Source: AK7set83x50Wr6OLwouSd9FYtIMUWEF17/WCDZMfbyiKThXFEdQWz+va8GhYtFkHWDw/bmmEH+n4Mw== X-Received: by 2002:a5d:5047:0:b0:2be:151a:dda0 with SMTP id h7-20020a5d5047000000b002be151adda0mr202559wrt.70.1675196436463; Tue, 31 Jan 2023 12:20:36 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 12/14] RISC-V: Add initial support for T-Head C906 Date: Tue, 31 Jan 2023 21:20:11 +0100 Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196500854100001 From: Christoph M=C3=BCllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Drop C910 as it does not differ from C906 - Set priv version to 1.11 (new fmin/fmax behaviour) Changes in v3: - Removed setting dropped 'xtheadxmae' extension Changes in v4: - Inlcude cpu_vendorid.h in cpu.c instead cpu.h target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ target/riscv/cpu.h | 1 + target/riscv/cpu_vendorid.h | 6 ++++++ 3 files changed, 38 insertions(+) create mode 100644 target/riscv/cpu_vendorid.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3078556f1b..8cbc5c9c1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "cpu_vendorid.h" #include "pmu.h" #include "internals.h" #include "time_helper.h" @@ -281,6 +282,35 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu =3D false; } =20 +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_11_0); + + cpu->cfg.ext_g =3D true; + cpu->cfg.ext_c =3D true; + cpu->cfg.ext_u =3D true; + cpu->cfg.ext_s =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.ext_zfh =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.ext_xtheadba =3D true; + cpu->cfg.ext_xtheadbb =3D true; + cpu->cfg.ext_xtheadbs =3D true; + cpu->cfg.ext_xtheadcmo =3D true; + cpu->cfg.ext_xtheadcondmov =3D true; + cpu->cfg.ext_xtheadfmemidx =3D true; + cpu->cfg.ext_xtheadmac =3D true; + cpu->cfg.ext_xtheadmemidx =3D true; + cpu->cfg.ext_xtheadmempair =3D true; + cpu->cfg.ext_xtheadsync =3D true; + + cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1371,6 +1401,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5cc3011529..60478f4a9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,6 +53,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */ --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=566M9qySxN23A71+uLC8/2FZUCFdWIxzeit6Cy0IHpE=; b=JmrILXtOD9SHgJ6R3EqpNLtq+ZJkzZ9HChifdx1XAaURYdVPHSmgHwfwcf7DG6v6XV 7jmd7eXHZdAFUCAd6XCJ88fhUhVxg4mXRudbkVXsC5l7w3n30Wo7Jq4dxG/zs3qK30hU OvWbGGZ8LLBmIG4tyXstL/M59vFTypga8eQLWuLTdLylRkDwNp4QgOfARA1KHQ70gwcb XNcQm9s+KmRt7TOXkdO5/LoBUqL1GF3UIhoRaTmAgggAa0Sfu/wvJd5bASOkmdtD8yTR ez0LEsUSrs2XPVAPhaWDxSgtN7mU9AfOonIKEe5CVfDJIFQX5gtEtIzGc7/VRA2mIUC8 EpIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=566M9qySxN23A71+uLC8/2FZUCFdWIxzeit6Cy0IHpE=; b=i2HmJki3+xVL5fmWOQmsYFgCSy8xzw8ggQsQd0UKyX9glqd48+eF/FjTisok5oYr1k cnjPvyOER1Hhjgjtl8fbMfX0ygcQdjfkYl4fY3hf7v8mYIsjdj0FXjAiKN+U0yDx78RK ug/w3by5qAl6e0czHdOrN6eiW7SsRXexN/ubgOo3ZHTVJlGAGFzmMAbhT868BbtVSMGO lZTQsasz1eW4TERMRTHTxiSgKmNH+UAoqQ+0J0fP5Ct52OnEfRHIsdX+OzWUcyZ4bT/g Il9HvZZvjrYuO8uvFMEBj0mbzIMMw+AyaJjgFW2pyMUQNXensC08c+tHFclTHi1fbX8e jmWQ== X-Gm-Message-State: AFqh2krHyj9oPoDAdYNutKGxS/ydFaJmf1JaV0QPDQRVhe4oFDcy1IP3 VE7TdQnEUWUduo23CRHUiDOn/g== X-Google-Smtp-Source: AMrXdXvk4HQimGZ0PYNsLjHeA06UIiAXs6S98MNkgVYFNZ+h233NCyhKpJsHV54z30JaDQsZvPvDNw== X-Received: by 2002:a05:600c:3495:b0:3db:a3a:4594 with SMTP id a21-20020a05600c349500b003db0a3a4594mr57673839wmq.28.1675196438062; Tue, 31 Jan 2023 12:20:38 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 13/14] RISC-V: Adding XTheadFmv ISA extension Date: Tue, 31 Jan 2023 21:20:12 +0100 Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196491135100003 From: Christoph M=C3=BCllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++ target/riscv/translate.c | 6 +-- target/riscv/xthead.decode | 4 ++ 5 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbc5c9c1b..0dd2f0c753 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -116,6 +116,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xthea= dfmemidx), + ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv= ), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthead= memidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xthea= dmempair), @@ -1134,6 +1135,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, fal= se), + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false= ), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60478f4a9c..7128438d8e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -480,6 +480,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadfmemidx; + bool ext_xtheadfmv; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 37373732f6..be87c34f56 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADFMV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmv) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -449,6 +455,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_m= emidx *a) return gen_fstore_idx(ctx, a, MO_TEUL, true); } =20 +/* XTheadFmv */ + +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t1, src1); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + TCGv dst; + TCGv_i64 t1; + + dst =3D dest_gpr(ctx, a->rd); + t1 =3D tcg_temp_new_i64(); + + tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); + tcg_gen_trunc_i64_tl(dst, t1); + gen_set_gpr(ctx, a->rd, dst); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + /* XTheadMac */ =20 static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 216eaf9d12..182649dcb6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,9 +135,9 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac = || - ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempa= ir || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv = || + ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 81daf1d694..d1d104bcf2 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 000101= 1 @th_memidx th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx =20 +# XTheadFmv +th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2 +th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2 + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r --=20 2.39.1 From nobody Thu Mar 28 12:17:47 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ztCilUCc1TA2sITRxRLcH39NMH4uHHWLjoD1hpEHldM=; b=VPxikWJqZJrtBu1Pos5YXivoQ3Xgu7Re4C9is/oYEsPM/TuZz+8ousjy56t6V25hbL fArTHYMIbsBs7q7zBNllWB6BGu0DEf4c8FfEmEF65Rb2stOauC0i77CBLEQL91yejsBr +d1EYpN5k0yqFRLicyOiJMkoWMjHpNZrcPGPko3Zh8cSJHT07hn6DvV4h+z7FP7d5obn IfjR/hp8uudQMhdePhL9Pv4FbBwdrzz4pX9yDS8uHxIn9l1FhaGcrLSUuiPravT3jtV/ ADSgz05fIzyr8U5a/3OZvQpHADHcU7jOdR/+xitTfQkbxQ1c+QHslvrh1Qd7KCg4yLT+ q3DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ztCilUCc1TA2sITRxRLcH39NMH4uHHWLjoD1hpEHldM=; b=hngC19jfwhgdHSr55Od2WdMGOmU4w27xNMJpFI1w3oXw7XOb73WihMpb9RLGQWAwvB VVz0DS9aGSvRLA/jmZDrxJp0WE8PjOdFFw0MLWD0h9b32/qpZ9PR+XKKezxkxqUDSz6p mjLHfqM0S+AMYIJwW2QGmgzzluyZFLY/Uwz0ghVcK1KjjrWGzG7bOB5oBrOCugwqCM/t gZeHVX0gP2VP4EAG3dQF5sOFXe5BTB1fZdTy3rnKG92fYLbyK6hrmwEiScICt4bHj68y 74LBV/1l4eYeNiBJbB/+yQ9DC16B2iL3/qS3qZrJ1QfTZjzE9nQQKSTuKcrIJbUwnkK/ I4IA== X-Gm-Message-State: AO0yUKWWRz4wX2H+e/3LU452jN4H5X2h/9KJ5/1JGyDF+8EVvWNDxN0z HhoQH3cqeeCbIPGGk0mGczueqQ== X-Google-Smtp-Source: AK7set+a6yEvzExo1SdzDHufeAJy4by1vPJVgdgY/Fh+K5S3L2JevVysEz+HD+1iBVRBo+3OdxRGQw== X-Received: by 2002:a5d:6501:0:b0:2c2:de2b:e7cd with SMTP id x1-20020a5d6501000000b002c2de2be7cdmr290196wru.50.1675196439782; Tue, 31 Jan 2023 12:20:39 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Date: Tue, 31 Jan 2023 21:20:13 +0100 Message-Id: <20230131202013.2541053-15-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196532282100005 From: Christoph M=C3=BCllner The XThead* extensions are maintained by T-Head and VRULL. Adding a point of contact from both companies. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c581c11a64..9dc0a2954e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,6 +295,14 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ =20 +RISC-V XThead* extensions +M: Christoph Muellner +M: LIU Zhiwei +L: qemu-riscv@nongnu.org +S: Supported +F: target/riscv/insn_trans/trans_xthead.c.inc +F: target/riscv/xthead*.decode + RISC-V XVentanaCondOps extension M: Philipp Tomsich L: qemu-riscv@nongnu.org --=20 2.39.1