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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ygu0duwWgb07Jo+qlRVPI7Zizkm9Hcw3R3ZaXGJeNaI=; b=E22vbgmJzo8I+hieRTSX4rrt4eWDktifyXi5kb04kI+vE5iw8iNwcbwQbqFi/3bHyW aD7/uFay6CPtcQ9OrnZ5mM+8l53JU0UvSuRx8ccrpbH3vRBKv25Ah5Tlmx5Cg+wq7cDE biAELt3C+cz9bM59i90j6BFgtvfphg8ZcfzrD8yCToPJZtY/OFSpoyGn/XYsmn9h5/RG 6XjMNe1xobeZ7QHot47WQ084Q5kxh/ITd2VqsXpFNHuKKqaessG0Xzdrss/bJQC+cqr7 YQz1lW18ZljntBaCHjGLAGIvSk8v8qgvuAnVLT5dRBBdSyyVVNc26U2GZxb2cpxKioj5 goIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ygu0duwWgb07Jo+qlRVPI7Zizkm9Hcw3R3ZaXGJeNaI=; b=p18BYiO5iAzbG8CbKoz6WquSDA4dyAdmp0MQmf7pZD18jzxTQRg+ZLgz1i5iM+w8g+ av2ncD1dwa3JtPOaF74zoo40aVG0OLvZZWNYfsFsqJhYEryE3k+KvKVmFrX1inFsGN/Z a1G6myOlynT15XdeKM408IjiYGbRMx3Qs2I+SwSPRG6SXK+HNRkZgMaB4bQHdHo1Ozph fgiyo6y5eolyvTyEdIYAfLGa5KpFpW87uWCX49ijMMyAXs4LJei43U8NABTAgsreGi7Z VtVHVUvwjtRHR1hb3t2QbiHLjiWeaFEz+/AVhytyW0hNwFn79S26BCnrWRmngr4Vf8z2 qChw== X-Gm-Message-State: AO0yUKUWH1omEg1a0nlzAFe52RVFOY2/Z42rmx9j0cN+E3VnpWEh76ZR +TxW0uSHt4b73LrA8a2b456nTzMOhTTVZPrd X-Google-Smtp-Source: AK7set83x50Wr6OLwouSd9FYtIMUWEF17/WCDZMfbyiKThXFEdQWz+va8GhYtFkHWDw/bmmEH+n4Mw== X-Received: by 2002:a5d:5047:0:b0:2be:151a:dda0 with SMTP id h7-20020a5d5047000000b002be151adda0mr202559wrt.70.1675196436463; Tue, 31 Jan 2023 12:20:36 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 12/14] RISC-V: Add initial support for T-Head C906 Date: Tue, 31 Jan 2023 21:20:11 +0100 Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196500854100001 From: Christoph M=C3=BCllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Drop C910 as it does not differ from C906 - Set priv version to 1.11 (new fmin/fmax behaviour) Changes in v3: - Removed setting dropped 'xtheadxmae' extension Changes in v4: - Inlcude cpu_vendorid.h in cpu.c instead cpu.h target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ target/riscv/cpu.h | 1 + target/riscv/cpu_vendorid.h | 6 ++++++ 3 files changed, 38 insertions(+) create mode 100644 target/riscv/cpu_vendorid.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3078556f1b..8cbc5c9c1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "cpu_vendorid.h" #include "pmu.h" #include "internals.h" #include "time_helper.h" @@ -281,6 +282,35 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu =3D false; } =20 +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_11_0); + + cpu->cfg.ext_g =3D true; + cpu->cfg.ext_c =3D true; + cpu->cfg.ext_u =3D true; + cpu->cfg.ext_s =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.ext_zfh =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.ext_xtheadba =3D true; + cpu->cfg.ext_xtheadbb =3D true; + cpu->cfg.ext_xtheadbs =3D true; + cpu->cfg.ext_xtheadcmo =3D true; + cpu->cfg.ext_xtheadcondmov =3D true; + cpu->cfg.ext_xtheadfmemidx =3D true; + cpu->cfg.ext_xtheadmac =3D true; + cpu->cfg.ext_xtheadmemidx =3D true; + cpu->cfg.ext_xtheadmempair =3D true; + cpu->cfg.ext_xtheadsync =3D true; + + cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1371,6 +1401,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5cc3011529..60478f4a9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,6 +53,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */ --=20 2.39.1