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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=566M9qySxN23A71+uLC8/2FZUCFdWIxzeit6Cy0IHpE=; b=JmrILXtOD9SHgJ6R3EqpNLtq+ZJkzZ9HChifdx1XAaURYdVPHSmgHwfwcf7DG6v6XV 7jmd7eXHZdAFUCAd6XCJ88fhUhVxg4mXRudbkVXsC5l7w3n30Wo7Jq4dxG/zs3qK30hU OvWbGGZ8LLBmIG4tyXstL/M59vFTypga8eQLWuLTdLylRkDwNp4QgOfARA1KHQ70gwcb XNcQm9s+KmRt7TOXkdO5/LoBUqL1GF3UIhoRaTmAgggAa0Sfu/wvJd5bASOkmdtD8yTR ez0LEsUSrs2XPVAPhaWDxSgtN7mU9AfOonIKEe5CVfDJIFQX5gtEtIzGc7/VRA2mIUC8 EpIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=566M9qySxN23A71+uLC8/2FZUCFdWIxzeit6Cy0IHpE=; b=i2HmJki3+xVL5fmWOQmsYFgCSy8xzw8ggQsQd0UKyX9glqd48+eF/FjTisok5oYr1k cnjPvyOER1Hhjgjtl8fbMfX0ygcQdjfkYl4fY3hf7v8mYIsjdj0FXjAiKN+U0yDx78RK ug/w3by5qAl6e0czHdOrN6eiW7SsRXexN/ubgOo3ZHTVJlGAGFzmMAbhT868BbtVSMGO lZTQsasz1eW4TERMRTHTxiSgKmNH+UAoqQ+0J0fP5Ct52OnEfRHIsdX+OzWUcyZ4bT/g Il9HvZZvjrYuO8uvFMEBj0mbzIMMw+AyaJjgFW2pyMUQNXensC08c+tHFclTHi1fbX8e jmWQ== X-Gm-Message-State: AFqh2krHyj9oPoDAdYNutKGxS/ydFaJmf1JaV0QPDQRVhe4oFDcy1IP3 VE7TdQnEUWUduo23CRHUiDOn/g== X-Google-Smtp-Source: AMrXdXvk4HQimGZ0PYNsLjHeA06UIiAXs6S98MNkgVYFNZ+h233NCyhKpJsHV54z30JaDQsZvPvDNw== X-Received: by 2002:a05:600c:3495:b0:3db:a3a:4594 with SMTP id a21-20020a05600c349500b003db0a3a4594mr57673839wmq.28.1675196438062; Tue, 31 Jan 2023 12:20:38 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 13/14] RISC-V: Adding XTheadFmv ISA extension Date: Tue, 31 Jan 2023 21:20:12 +0100 Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196491135100003 From: Christoph M=C3=BCllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++ target/riscv/translate.c | 6 +-- target/riscv/xthead.decode | 4 ++ 5 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbc5c9c1b..0dd2f0c753 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -116,6 +116,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xthea= dfmemidx), + ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv= ), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthead= memidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xthea= dmempair), @@ -1134,6 +1135,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, fal= se), + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false= ), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60478f4a9c..7128438d8e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -480,6 +480,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadfmemidx; + bool ext_xtheadfmv; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 37373732f6..be87c34f56 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADFMV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmv) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -449,6 +455,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_m= emidx *a) return gen_fstore_idx(ctx, a, MO_TEUL, true); } =20 +/* XTheadFmv */ + +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t1, src1); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + TCGv dst; + TCGv_i64 t1; + + dst =3D dest_gpr(ctx, a->rd); + t1 =3D tcg_temp_new_i64(); + + tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); + tcg_gen_trunc_i64_tl(dst, t1); + gen_set_gpr(ctx, a->rd, dst); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + /* XTheadMac */ =20 static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 216eaf9d12..182649dcb6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,9 +135,9 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac = || - ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempa= ir || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv = || + ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 81daf1d694..d1d104bcf2 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 000101= 1 @th_memidx th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx =20 +# XTheadFmv +th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2 +th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2 + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r --=20 2.39.1