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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SZegSXhsxlv9N/vVZ4WumTWFg4tDXkbLvsFx6aF6o0o=; b=PdQ76napMucS6ZFXKtiVthT5n3g+Nk7UEI/iL3OV9tarSnW0eohkaUx0fhrKFZariY G/YAqZA6LcO5C29DlEWsY/5zAwbyLZFxvL9MvO8yLl1x1wTnQVmem1msfLhYexqkg3r9 lgbFfgLTbSTWxDvTv35CXn24UjKML5ymhzDO2nvQ7kj+Wq615P7n6iJr4KbWfjNwzr7y wvVPbANIbfssKhpC2Es/fpVzFztdpUsRrxwuS4GhCa6/2HhoiUuz1K8dtK5UcA4+Pz01 mv1k0d6klX/MRVmgCeXL4n0+U503KgGr6hMRk8dSpHVj+6niRWHYlU6uTeU+ovSGe6DM 60Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SZegSXhsxlv9N/vVZ4WumTWFg4tDXkbLvsFx6aF6o0o=; b=XM4/PO2xXPqftaQLlRxE3zQKANUbcFLYjIxYP4LmuXSQV8SvRsM0PdeL2+ByNUJyBu Prfy9x9wZHiEMZ7grTpBybfECKkB1Ge1hdWAYtVyLM7cVlaqMMdIe5+WafQMNs8MvOlR fq4eTdtuksjs+Oj3ebgdtrM4anesYRDXzv51gQjf5mOUAE96X5VM5UJ1Du0awcgKb2aE pBAb9fK4IkH3ZdurnmlgcJg++z6m77/ClZ08eHsfXTISs2hckjoVEpe1cR5OI2hZ2Spy k90QvtVYJD8CBoHBjbgtCHqTKODLlTo10ftdGImfOzmYsMfkbLUpHDxXNiAucLw3g9XI z9BA== X-Gm-Message-State: AO0yUKXCxEZ6vmjFZatHJY0oAR8H/1ucZEXj4taIpKBTOlRIjv0Asgs+ 5j9mpdvvVoDlxcajZNjpiyQkyw== X-Google-Smtp-Source: AK7set8xZkkJTRapDFZvayCPpWi241jYZ9/yRVak4kdiRprHY9fYPlGjqklO5R2JKXjZTRahGzut5A== X-Received: by 2002:a5d:5602:0:b0:2bd:dd13:170f with SMTP id l2-20020a5d5602000000b002bddd13170fmr261996wrv.26.1675196420075; Tue, 31 Jan 2023 12:20:20 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 02/14] RISC-V: Adding XTheadSync ISA extension Date: Tue, 31 Jan 2023 21:20:01 +0100 Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196471378100001 From: Christoph M=C3=BCllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use helper to synchronize CPUs and perform TLB flushes - Change implemenation to follow latest spec update - Use single decoder for XThead extensions Changes in v3: - Adjust for renamed REQUIRE_PRIV_* test macros Changes in v4: - Drop decode_save_opc() in trans_th_sfence_vmas() target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 85 ++++++++++++++++++++++ target/riscv/op_helper.c | 6 ++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 9 +++ 7 files changed, 105 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ea61e5b22..f76639845d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), + ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; =20 @@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] =3D { =20 /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3ebc6f112..ea00586436 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { =20 /* Vendor-specific custom extensions */ bool ext_xtheadcmo; + bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 uint8_t pmu_num; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 58a30f03d6..0497370afd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -109,6 +109,7 @@ DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) +DEF_HELPER_1(tlb_flush_all, void, env) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) #endif diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 24acaf188c..f35bf6ea89 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADSYNC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadsync) { \ + return false; \ + } \ +} while (0) + /* XTheadCmo */ =20 static inline int priv_level(DisasContext *ctx) @@ -79,3 +85,82 @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_= PRIV_MSU) NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +/* XTheadSync */ + +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MS(ctx); + gen_helper_tlb_flush_all(cpu_env); + return true; +#else + return false; +#endif +} + +#ifndef CONFIG_USER_ONLY +static void gen_th_sync_local(DisasContext *ctx) +{ + /* + * Emulate out-of-order barriers with pipeline flush + * by exiting the translation block. + */ + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp =3D DISAS_NORETURN; +} +#endif + +static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync is an out-of-order barrier. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync.i is th.sync plus pipeline flush. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a) +{ + /* This instruction has the same behaviour like th.sync.i. */ + return trans_th_sync_i(ctx, a); +} + +static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a) +{ + /* This instruction has the same behaviour like th.sync. */ + return trans_th_sync(ctx, a); +} diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 878bcb03b8..48f918b71b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -258,6 +258,12 @@ void helper_tlb_flush(CPURISCVState *env) } } =20 +void helper_tlb_flush_all(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + tlb_flush_all_cpus_synced(cs); +} + void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1e29ac9886..0657a4bea2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,7 @@ static bool always_true_p(DisasContext *ctx __attribut= e__((__unused__))) =20 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo; + return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 30533a66f5..1d86f3a012 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -10,9 +10,11 @@ =20 # Fields: %rs1 15:5 +%rs2 20:5 =20 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 +@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 =20 # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 @@ -36,3 +38,10 @@ th_icache_iva 0000001 10000 ..... 000 00000 0001011 @= sfence_vm th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 + +# XTheadSync +th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s +th_sync 0000000 11000 00000 000 00000 0001011 +th_sync_i 0000000 11010 00000 000 00000 0001011 +th_sync_is 0000000 11011 00000 000 00000 0001011 +th_sync_s 0000000 11001 00000 000 00000 0001011 --=20 2.39.1