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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4ro3zV/8frUQCS512EVPsuQE0kUlUm+PFZm4/WXtpfo=; b=VLkNOPhz8P/4OebgzbV5HUW2vARkuhhL9aV6gOxW7S6hro7lSlfV2BKj9BEJmZ7tn1 tktBcU/CLlruVyDTlnEcrbctGwuyzkLa+XsjEiq3FUH6y+r0asGsqHeYQwlBrtRJahlH Q+dKCe42a+u5SW4fbEnvG67Y8XRQx8v7PXyEi5K3X/+uqz9H7M0dtnxlsIM0Ch7Qcer5 zlIdQHFe/CVYWizFgnwWCYbHD5KlgVdq/5zHgU0dNnVR7XFcGthHQ63U4ADzLwDOMgvu Kc9oycdgLosuqXtAH3FiIpQTxVs/oQbEsyK9ZhtRM/DO3LPDYZkMOvqeLOQQODtEkzk0 QM7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4ro3zV/8frUQCS512EVPsuQE0kUlUm+PFZm4/WXtpfo=; b=ba2azbC8Zur9QFr1wbifbd9tcmIFdoxwXWFZV7GEdnr6bjWKRP2FG9Q4QWmrjQUvgK gmNgKowO9TR7zU8NSkQ/IIMFoD5BYy5Sa4eB31k7XDbET+yfH07uUN1Noj6jRF4TmcEa k8ewzcruNhVFqlxUX4dOOwE96Uu1OPF110nLYEIG7DQAZoouSu12mJluR0zDykX0nfQq 8DitIQH6CZyT02MvPkkFuhq5BkNXXTS7Kr2dCFI/h/q+RrVWmJLsXv73IIP7jncWvqnw wZPpg3vXg8veMIicuZLA0tV6Omcr73nnUDcWT86Q1kBeI9W/rqG86KmjgXC4h8yV1tGu hsAg== X-Gm-Message-State: AO0yUKWJBv9NbynADlnKNOTVuWEl+Xnhp24Y1SYsoqGF0wbhEUFutdD/ ub9XzH9OnWOdNJl9x9FU3TqC6A== X-Google-Smtp-Source: AK7set9NHU/OGthtN7oWiffRBDsu8+jMmu1J+/KiJ5gB7edaABLJr64Hibu8WYe5dyDggP5KUIUzAA== X-Received: by 2002:adf:e181:0:b0:2bd:c4ea:3b59 with SMTP id az1-20020adfe181000000b002bdc4ea3b59mr343493wrb.0.1675196428299; Tue, 31 Jan 2023 12:20:28 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Date: Tue, 31 Jan 2023 21:20:06 +0100 Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196542388100003 From: Christoph M=C3=BCllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 8 +++ 5 files changed, 96 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13b065bc68..88da4de14d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), + ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; @@ -1099,6 +1100,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a313e025e7..830b20558c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadmac; bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 089b51f468..31a4034927 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADMAC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmac) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -299,6 +305,83 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_m= veqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } =20 +/* XTheadMac */ + +static bool gen_th_mac(DisasContext *ctx, arg_r *a, + void (*accumulate_func)(TCGv, TCGv, TCGv), + void (*extend_operand_func)(TCGv, TCGv)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src0 =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv tmp =3D tcg_temp_new(); + + if (extend_operand_func) { + TCGv tmp2 =3D tcg_temp_new(); + extend_operand_func(tmp, src1); + extend_operand_func(tmp2, src2); + tcg_gen_mul_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + } else { + tcg_gen_mul_tl(tmp, src1, src2); + } + + accumulate_func(dest, src0, tmp); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(tmp); + + return true; +} + +/* th.mula: "rd =3D rd + rs1 * rs2" */ +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.mulah: "rd =3D sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); +} + +/* th.mulaw: "rd =3D sext.w(rd + rs1 * rs2)" */ +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.muls: "rd =3D rd - rs1 * rs2" */ +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + +/* th.mulsh: "rd =3D sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); +} + +/* th.mulsw: "rd =3D sext.w(rd - rs1 * rs2)" */ +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + /* XTheadSync */ =20 static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4f4c09cd68..e5a57a8516 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac = || + ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index a8ebd8a18b..696de6cecf 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -88,6 +88,14 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r =20 +# XTheadMac +th_mula 00100 00 ..... ..... 001 ..... 0001011 @r +th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r +th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r +th_muls 00100 01 ..... ..... 001 ..... 0001011 @r +th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r +th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 --=20 2.39.1