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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xm+YXRWYUm4OQJWfKMIGdiAhga6zqnD1FiBxxxopHlo=; b=ovXplVjiGoziJI6gEwJsABcDiXLKd51jg0L8x9pRxFMJX/bUR33MGhwpy0qVbl/RPZ IKa54glgf7GVLlQg6IwF/TIZ4eXp7D2xmdKBlFycg7fwDOxC7vl4qKfQozziBH7jyxr3 5e1sNq+AY4ex70pkAlcnhgNM1WSeS1sWgZhea+46iugw8HcoNC/6W543UNjlU1rLpuRi E3a2ZCQSOk/8JJmQcyiJ7bfmuyTxFy0q88magUDnHIVl2VxNfkXorYcNH7LVlfWcBOsz nT/zx3gT/f8fy/RKWvPTrLiuHkUwBGaEFV0Ns+JGxlwmNUFoI6WMp7VZyJ2/KdXHq6RK UHvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xm+YXRWYUm4OQJWfKMIGdiAhga6zqnD1FiBxxxopHlo=; b=d+rLXsQ6eE0wHX91D+CWXJx56f2wJcvkDiDhwwh+x9p1ZauqM9vTT4AR9QjwhEHjXK YO4WSkcmE8Pjkup+ByCraiQPZs+gtHlawJNYxtSJrdZOZU5VGx7NeX2FtEWmUD6AUvTs F2Hv0IV/jx4B2xGdIGd2IXwh6lxuuxDC3CsxO2oeRl1vD2qQkzvDhXdHSYuDeAlFY0ma nWsmQvDQfEU0S7Lja4Khw5DBBBv49OW395rDkqYG7r8h2/nF419Ma2BRQo1YltbSInoM z7jAk3daFQBwp3qShvfsLfDBr0BtkNmVO5Gw2AGbWvZMGKQeD9YDh/70PKVSbEz64/Mq Mpag== X-Gm-Message-State: AO0yUKVJ4EVglGPzJC5rjVxlEHPKHLBM5vdXfm48MhBznxA3CJdYWZTU shVOtDkgA5V8R/LOlCKVHiwlqQ== X-Google-Smtp-Source: AK7set+/QZby1lBNTdNJqzl0KDyJY+1jEP+Cdc1fNWhP1GooVW05PqRmcKiAKgTdRhGsev4QklmvNw== X-Received: by 2002:a5d:510f:0:b0:2bf:ae4b:4cbf with SMTP id s15-20020a5d510f000000b002bfae4b4cbfmr230544wrt.55.1675196429996; Tue, 31 Jan 2023 12:20:29 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 08/14] RISC-V: Adding T-Head MemPair extension Date: Tue, 31 Jan 2023 21:20:07 +0100 Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1675196536512100003 From: Christoph M=C3=BCllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Christoph M=C3=BCllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_address() to calculate addresses Changes in v4: - Don't translate in case of overlapping registers - Use temporaries to avoid unexpected behaviour in case of exceptions - There have also been clarifications in the specification Changes in v5: - Use memop_size() instead of hard coded constants target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 92 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 13 +++ 5 files changed, 109 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 88da4de14d..b7047d139d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), + ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xthea= dmempair), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; @@ -1101,6 +1102,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), + DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 830b20558c..38e80d44d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -479,6 +479,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadmac; + bool ext_xtheadmempair; bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 31a4034927..f1bd0dbad5 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADMEMPAIR(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmempair) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -382,6 +388,92 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_m= ulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } =20 +/* XTheadMemPair */ + +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + if (a->rs =3D=3D a->rd1 || a->rs =3D=3D a->rd2 || a->rd1 =3D=3D a->rd2= ) { + return false; + } + + TCGv t1 =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv addr1 =3D tcg_temp_new(); + TCGv addr2 =3D tcg_temp_new(); + int imm =3D a->sh2 << shamt; + + addr1 =3D get_address(ctx, a->rs, imm); + addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); + + tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd1, t1); + gen_set_gpr(ctx, a->rd2, t2); + + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_loadpair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TESL, 3); +} + +static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TEUL, 3); +} + +static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memo= p, + int shamt) +{ + if (a->rs =3D=3D a->rd1 || a->rs =3D=3D a->rd2 || a->rd1 =3D=3D a->rd2= ) { + return false; + } + + TCGv data1 =3D get_gpr(ctx, a->rd1, EXT_NONE); + TCGv data2 =3D get_gpr(ctx, a->rd2, EXT_NONE); + TCGv addr1 =3D tcg_temp_new(); + TCGv addr2 =3D tcg_temp_new(); + int imm =3D a->sh2 << shamt; + + addr1 =3D get_address(ctx, a->rs, imm); + addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); + + tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); + + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_storepair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_storepair_tl(ctx, a, MO_TESL, 3); +} + /* XTheadSync */ =20 static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e5a57a8516..f383e69db3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,7 +135,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute= __((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac = || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 696de6cecf..ff2a83b56d 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -11,16 +11,21 @@ =20 # Fields: %rd 7:5 +%rd1 7:5 +%rs 15:5 %rs1 15:5 +%rd2 20:5 %rs2 20:5 %sh5 20:5 %sh6 20:6 +%sh2 25:2 =20 # Argument sets &r rd rs1 rs2 !extern &r2 rd rs1 !extern &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd +&th_pair rd1 rs rd2 sh2 =20 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -30,6 +35,7 @@ @th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd @sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 %r= s1 %rd +@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2= %sh2 =20 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -96,6 +102,13 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011= @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r =20 +# XTheadMemPair +th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair +th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair +th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 --=20 2.39.1