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Tue, 31 Jan 2023 22:56:54 GMT Received: from hu-devc-lv-u18-c.qualcomm.com (hu-tsimpson-lv.qualcomm.com [10.47.235.220]) by NALASPPMTA02.qualcomm.com (PPS) with ESMTP id 30VMur41001956; Tue, 31 Jan 2023 22:56:54 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 1A41450011B; Tue, 31 Jan 2023 14:56:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=Y9wciQmWDduxdfjaS52eUcJlIv+40aOUxk1wbe5KtWk=; b=Y9FmlK5PmBRmgGuiIqTKlgBwvLE+NwbLJDqF0C3k8LnJ6jjJTMi1JT97dvHIHw/PnWQw BjdvP5VX1ubjeETVwYlai7BU0SRc9hf2oTrXwCLzO3k097mXeSv9PQJUO8WTH9RFEjAX iHPeg1Xvj7KqFxJk+A+EiqkvOSDXUztJAaj1c+22MnNVJIilRU08mxysEpIphj8UHkmm 3upPqSa4eHz91EZR3I190MthK0GevBySFu+TZMaNwukZsDyOwrgvIJ+E6QagxAfXG+xD 0BeW9UxMKEIhIW8/0aEvBKRxPfhL/iughgupsnY4IrIcIrOhritR/bU2XHnxqRXWhYng lA== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v5 14/14] Hexagon (target/hexagon) Improve code gen for predicated HVX instructions Date: Tue, 31 Jan 2023 14:56:47 -0800 Message-Id: <20230131225647.25274-15-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230131225647.25274-1-tsimpson@quicinc.com> References: <20230131225647.25274-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1675205927479100011 The following improvements are made for predicated HVX instructions During gen_commit_hvx, unconditionally move the "new" value into the dest Don't set slot_cancelled Remove runtime bookkeeping of which registers were updated Reduce the cases where gen_log_vreg_write[_pair] is called It's only needed for special operands VxxV and VyV Remove gen_log_qreg_write Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson --- target/hexagon/cpu.h | 5 +-- target/hexagon/gen_tcg_hvx.h | 17 +------- target/hexagon/translate.h | 16 +++----- target/hexagon/genptr.c | 50 +++--------------------- target/hexagon/translate.c | 60 +++-------------------------- target/hexagon/README | 28 ++++---------- target/hexagon/gen_analyze_funcs.py | 3 +- target/hexagon/gen_tcg_funcs.py | 35 ++++------------- 8 files changed, 37 insertions(+), 177 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 34c0ae0a67..81b663ecfb 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -111,11 +111,8 @@ typedef struct CPUArchState { MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); =20 - VRegMask VRegs_updated; - MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); - QRegMask QRegs_updated; =20 /* Temporaries used within instructions */ MMVectorPair VuuV QEMU_ALIGNED(16); diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index 083f4d92c6..3154c65ce1 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -133,17 +133,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ TCGv lsb =3D tcg_temp_new(); \ TCGLabel *false_label =3D gen_new_label(); \ - TCGLabel *end_label =3D gen_new_label(); \ tcg_gen_andi_tl(lsb, PsV, 1); \ tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \ tcg_temp_free(lsb); \ tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_br(end_label); \ gen_set_label(false_label); \ - tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \ - 1 << insn->slot); \ - gen_set_label(end_label); \ } while (0) =20 =20 @@ -560,18 +555,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ TCGv LSB =3D tcg_temp_new(); \ TCGLabel *false_label =3D gen_new_label(); \ - TCGLabel *end_label =3D gen_new_label(); \ GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ tcg_temp_free(LSB); \ gen_vreg_load(ctx, DSTOFF, EA, true); \ INC; \ - tcg_gen_br(end_label); \ gen_set_label(false_label); \ - tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \ - 1 << insn->slot); \ - gen_set_label(end_label); \ } while (0) =20 #define fGEN_TCG_PRED_VEC_LOAD_pred_pi \ @@ -731,18 +721,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ TCGv LSB =3D tcg_temp_new(); \ TCGLabel *false_label =3D gen_new_label(); \ - TCGLabel *end_label =3D gen_new_label(); \ GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ tcg_temp_free(LSB); \ gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \ INC; \ - tcg_gen_br(end_label); \ gen_set_label(false_label); \ - tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \ - 1 << insn->slot); \ - gen_set_label(end_label); \ } while (0) =20 #define fGEN_TCG_PRED_VEC_STORE_pred_pi(ALIGN) \ diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 765f2c6a22..04ffa4d041 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -49,7 +49,6 @@ typedef struct DisasContext { int tmp_vregs_idx; int tmp_vregs_num[VECTOR_TEMPS_MAX]; int vreg_log[NUM_VREGS]; - bool vreg_is_predicated[NUM_VREGS]; int vreg_log_idx; DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS); DECLARE_BITMAP(vregs_updated, NUM_VREGS); @@ -57,7 +56,6 @@ typedef struct DisasContext { DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS); DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS); int qreg_log[NUM_QREGS]; - bool qreg_is_predicated[NUM_QREGS]; int qreg_log_idx; bool pre_commit; TCGCond branch_cond; @@ -111,11 +109,12 @@ static inline void ctx_log_vreg_write(DisasContext *c= tx, bool is_predicated) { if (type !=3D EXT_TMP) { - ctx->vreg_log[ctx->vreg_log_idx] =3D rnum; - ctx->vreg_is_predicated[ctx->vreg_log_idx] =3D is_predicated; - ctx->vreg_log_idx++; + if (!test_bit(rnum, ctx->vregs_updated)) { + ctx->vreg_log[ctx->vreg_log_idx] =3D rnum; + ctx->vreg_log_idx++; + set_bit(rnum, ctx->vregs_updated); + } =20 - set_bit(rnum, ctx->vregs_updated); if (is_predicated) { set_bit(rnum, ctx->predicated_future_vregs); } @@ -140,10 +139,9 @@ static inline void ctx_log_vreg_write_pair(DisasContex= t *ctx, } =20 static inline void ctx_log_qreg_write(DisasContext *ctx, - int rnum, bool is_predicated) + int rnum) { ctx->qreg_log[ctx->qreg_log_idx] =3D rnum; - ctx->qreg_is_predicated[ctx->qreg_log_idx] =3D is_predicated; ctx->qreg_log_idx++; } =20 @@ -164,8 +162,6 @@ extern TCGv hex_dczero_addr; extern TCGv hex_llsc_addr; extern TCGv hex_llsc_val; extern TCGv_i64 hex_llsc_val_i64; -extern TCGv hex_VRegs_updated; -extern TCGv hex_QRegs_updated; extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index f937a17b24..62e69aa8f7 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -1029,70 +1029,32 @@ static intptr_t vreg_src_off(DisasContext *ctx, int= num) } =20 static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num, - VRegWriteType type, int slot_num, - bool is_predicated) + VRegWriteType type) { - TCGLabel *label_end =3D NULL; intptr_t dstoff; =20 - if (is_predicated) { - TCGv cancelled =3D tcg_temp_local_new(); - label_end =3D gen_new_label(); - - /* Don't do anything if the slot was cancelled */ - tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); - tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); - tcg_temp_free(cancelled); - } - if (type !=3D EXT_TMP) { dstoff =3D ctx_future_vreg_off(ctx, num, 1, true); tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVector)); - tcg_gen_ori_tl(hex_VRegs_updated, hex_VRegs_updated, 1 << num); } else { dstoff =3D ctx_tmp_vreg_off(ctx, num, 1, false); tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVector)); } - - if (is_predicated) { - gen_set_label(label_end); - } } =20 static void gen_log_vreg_write_pair(DisasContext *ctx, intptr_t srcoff, in= t num, - VRegWriteType type, int slot_num, - bool is_predicated) + VRegWriteType type) { - gen_log_vreg_write(ctx, srcoff, num ^ 0, type, slot_num, is_predicated= ); + gen_log_vreg_write(ctx, srcoff, num ^ 0, type); srcoff +=3D sizeof(MMVector); - gen_log_vreg_write(ctx, srcoff, num ^ 1, type, slot_num, is_predicated= ); + gen_log_vreg_write(ctx, srcoff, num ^ 1, type); } =20 -static void gen_log_qreg_write(intptr_t srcoff, int num, int vnew, - int slot_num, bool is_predicated) +static intptr_t get_result_qreg(DisasContext *ctx, int qnum) { - TCGLabel *label_end =3D NULL; - intptr_t dstoff; - - if (is_predicated) { - TCGv cancelled =3D tcg_temp_local_new(); - label_end =3D gen_new_label(); - - /* Don't do anything if the slot was cancelled */ - tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); - tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); - tcg_temp_free(cancelled); - } - - dstoff =3D offsetof(CPUHexagonState, future_QRegs[num]); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMQReg), sizeof(MMQReg)= ); - - if (is_predicated) { - tcg_gen_ori_tl(hex_QRegs_updated, hex_QRegs_updated, 1 << num); - gen_set_label(label_end); - } + return offsetof(CPUHexagonState, future_QRegs[qnum]); } =20 static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src, diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 6ee8784910..59dd721ec3 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -56,8 +56,6 @@ TCGv hex_dczero_addr; TCGv hex_llsc_addr; TCGv hex_llsc_val; TCGv_i64 hex_llsc_val_i64; -TCGv hex_VRegs_updated; -TCGv hex_QRegs_updated; TCGv hex_vstore_addr[VSTORES_MAX]; TCGv hex_vstore_size[VSTORES_MAX]; TCGv hex_vstore_pending[VSTORES_MAX]; @@ -248,12 +246,11 @@ static bool check_for_attrib(Packet *pkt, int attrib) =20 static bool need_slot_cancelled(Packet *pkt) { - /* We only need slot_cancelled for conditional store and HVX instructi= ons */ + /* We only need slot_cancelled for conditional store instructions */ for (int i =3D 0; i < pkt->num_insns; i++) { uint16_t opcode =3D pkt->insn[i].opcode; if (GET_ATTRIB(opcode, A_CONDEXEC) && - (GET_ATTRIB(opcode, A_STORE) || - GET_ATTRIB(opcode, A_CVI))) { + GET_ATTRIB(opcode, A_SCALAR_STORE)) { return true; } } @@ -453,11 +450,6 @@ static void gen_start_packet(DisasContext *ctx) i =3D find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + = 1); } } - - if (pkt->pkt_has_hvx) { - tcg_gen_movi_tl(hex_VRegs_updated, 0); - tcg_gen_movi_tl(hex_QRegs_updated, 0); - } } =20 bool is_gather_store_insn(DisasContext *ctx) @@ -730,67 +722,31 @@ static void gen_commit_hvx(DisasContext *ctx) /* * for (i =3D 0; i < ctx->vreg_log_idx; i++) { * int rnum =3D ctx->vreg_log[i]; - * if (ctx->vreg_is_predicated[i]) { - * if (env->VRegs_updated & (1 << rnum)) { - * env->VRegs[rnum] =3D env->future_VRegs[rnum]; - * } - * } else { - * env->VRegs[rnum] =3D env->future_VRegs[rnum]; - * } + * env->VRegs[rnum] =3D env->future_VRegs[rnum]; * } */ for (i =3D 0; i < ctx->vreg_log_idx; i++) { int rnum =3D ctx->vreg_log[i]; - bool is_predicated =3D ctx->vreg_is_predicated[i]; intptr_t dstoff =3D offsetof(CPUHexagonState, VRegs[rnum]); intptr_t srcoff =3D ctx_future_vreg_off(ctx, rnum, 1, false); size_t size =3D sizeof(MMVector); =20 - if (is_predicated) { - TCGv cmp =3D tcg_temp_new(); - TCGLabel *label_skip =3D gen_new_label(); - - tcg_gen_andi_tl(cmp, hex_VRegs_updated, 1 << rnum); - tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); - tcg_temp_free(cmp); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); - gen_set_label(label_skip); - } else { - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); - } + tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); } =20 /* * for (i =3D 0; i < ctx->qreg_log_idx; i++) { * int rnum =3D ctx->qreg_log[i]; - * if (ctx->qreg_is_predicated[i]) { - * if (env->QRegs_updated) & (1 << rnum)) { - * env->QRegs[rnum] =3D env->future_QRegs[rnum]; - * } - * } else { - * env->QRegs[rnum] =3D env->future_QRegs[rnum]; - * } + * env->QRegs[rnum] =3D env->future_QRegs[rnum]; * } */ for (i =3D 0; i < ctx->qreg_log_idx; i++) { int rnum =3D ctx->qreg_log[i]; - bool is_predicated =3D ctx->qreg_is_predicated[i]; intptr_t dstoff =3D offsetof(CPUHexagonState, QRegs[rnum]); intptr_t srcoff =3D offsetof(CPUHexagonState, future_QRegs[rnum]); size_t size =3D sizeof(MMQReg); =20 - if (is_predicated) { - TCGv cmp =3D tcg_temp_new(); - TCGLabel *label_skip =3D gen_new_label(); - - tcg_gen_andi_tl(cmp, hex_QRegs_updated, 1 << rnum); - tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); - tcg_temp_free(cmp); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); - gen_set_label(label_skip); - } else { - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); - } + tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); } =20 if (pkt_has_hvx_store(ctx->pkt)) { @@ -1125,10 +1081,6 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, llsc_val), "llsc_val"); hex_llsc_val_i64 =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); - hex_VRegs_updated =3D tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, VRegs_updated), "VRegs_updated"); - hex_QRegs_updated =3D tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, QRegs_updated), "QRegs_updated"); for (i =3D 0; i < STORES_MAX; i++) { snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); hex_store_addr[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/hexagon/README b/target/hexagon/README index d92731e346..6a9efb6fcf 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -137,31 +137,25 @@ For HVX vectors, the generator behaves slightly diffe= rently. The wide vectors won't fit in a TCGv or TCGv_i64, so we pass TCGv_ptr variables to pass the address to helper functions. Here's an example for an HVX vector-add-word istruction. - static void generate_V6_vaddw( - CPUHexagonState *env, - DisasContext *ctx, - Insn *insn, - Packet *pkt) + static void generate_V6_vaddw(DisasContext *ctx) { + Insn *insn __attribute__((unused)) =3D ctx->insn; const int VdN =3D insn->regno[0]; const intptr_t VdV_off =3D ctx_future_vreg_off(ctx, VdN, 1, true); - TCGv_ptr VdV =3D tcg_temp_local_new_ptr(); + TCGv_ptr VdV =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr(VdV, cpu_env, VdV_off); const int VuN =3D insn->regno[1]; const intptr_t VuV_off =3D vreg_src_off(ctx, VuN); - TCGv_ptr VuV =3D tcg_temp_local_new_ptr(); + TCGv_ptr VuV =3D tcg_temp_new_ptr(); const int VvN =3D insn->regno[2]; const intptr_t VvV_off =3D vreg_src_off(ctx, VvN); - TCGv_ptr VvV =3D tcg_temp_local_new_ptr(); + TCGv_ptr VvV =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr(VuV, cpu_env, VuV_off); tcg_gen_addi_ptr(VvV, cpu_env, VvV_off); - TCGv slot =3D tcg_constant_tl(insn->slot); - gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV, slot); - tcg_temp_free(slot); - gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false); + gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV); tcg_temp_free_ptr(VdV); tcg_temp_free_ptr(VuV); tcg_temp_free_ptr(VvV); @@ -177,12 +171,9 @@ functions from tcg-op-gvec.h. Here's the override for= this instruction. Finally, we notice that the override doesn't use the TCGv_ptr variables, so we don't generate them when an override is present. Here is what we gener= ate when the override is present. - static void generate_V6_vaddw( - CPUHexagonState *env, - DisasContext *ctx, - Insn *insn, - Packet *pkt) + static void generate_V6_vaddw(DisasContext *ctx) { + Insn *insn __attribute__((unused)) =3D ctx->insn; const int VdN =3D insn->regno[0]; const intptr_t VdV_off =3D ctx_future_vreg_off(ctx, VdN, 1, true); @@ -193,7 +184,6 @@ when the override is present. const intptr_t VvV_off =3D vreg_src_off(ctx, VvN); fGEN_TCG_V6_vaddw({ fHIDE(int i;) fVFOREACH(32, i) { VdV.w[i] =3D = VuV.w[i] + VvV.w[i] ; } }); - gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false); } =20 We also generate an analyze_ function for each instruction. Currentl= y, @@ -286,10 +276,8 @@ For Hexagon Vector eXtensions (HVX), the following fie= lds are used VRegs Vector registers future_VRegs Registers to be stored during packet commit tmp_VRegs Temporary registers *not* stored during co= mmit - VRegs_updated Mask of predicated vector writes QRegs Q (vector predicate) registers future_QRegs Registers to be stored during packet commit - QRegs_updated Mask of predicated vector writes =20 *** Debugging *** =20 diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py index 3a1db46ac3..4c6dba033b 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -110,8 +110,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno): if (regid in {"d", "e", "x"}): f.write(" const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) - f.write(" ctx_log_qreg_write(ctx, %s, %s);\n" % \ - (regN, predicated)) + f.write(" ctx_log_qreg_write(ctx, %s);\n" % (regN)) elif (regid in {"s", "t", "u", "v"}): f.write("// const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index e2fbb50949..f5a2798f9b 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -183,8 +183,7 @@ def genptr_decl(f, tag, regtype, regid, regno): (regtype, regid, regno)) f.write(" const intptr_t %s%sV_off =3D\n" % \ (regtype, regid)) - f.write(" offsetof(CPUHexagonState,\n") - f.write(" future_QRegs[%s%sN]);\n" % \ + f.write(" get_result_qreg(ctx, %s%sN);\n" % \ (regtype, regid)) if (not hex_common.skip_qemu_helper(tag)): f.write(" TCGv_ptr %s%sV =3D tcg_temp_new_ptr();\n" % \ @@ -479,36 +478,18 @@ def genptr_dst_write(f, tag, regtype, regid): =20 def genptr_dst_write_ext(f, tag, regtype, regid, newv=3D"EXT_DFL"): if (regtype =3D=3D "V"): - if (regid in {"dd", "xx", "yy"}): - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - is_predicated =3D "true" - else: - is_predicated =3D "false" + if (regid in {"xx"}): f.write(" gen_log_vreg_write_pair(ctx, %s%sV_off, %s%sN, " = % \ (regtype, regid, regtype, regid)) - f.write("%s, insn->slot, %s);\n" % \ - (newv, is_predicated)) - elif (regid in {"d", "x", "y"}): - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - is_predicated =3D "true" - else: - is_predicated =3D "false" - f.write(" gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s, " %= \ + f.write("%s);\n" % \ + (newv)) + elif (regid in {"y"}): + f.write(" gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s);\n"= % \ (regtype, regid, regtype, regid, newv)) - f.write("insn->slot, %s);\n" % \ - (is_predicated)) - else: + elif (regid not in {"dd", "d", "x"}): print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "Q"): - if (regid in {"d", "e", "x"}): - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - is_predicated =3D "true" - else: - is_predicated =3D "false" - f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \ - (regtype, regid, regtype, regid, newv)) - f.write("insn->slot, %s);\n" % (is_predicated)) - else: + if (regid not in {"d", "e", "x"}): print("Bad register parse: ", regtype, regid) else: print("Bad register parse: ", regtype, regid) --=20 2.17.1