From nobody Tue Apr 23 14:10:30 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675265868; cv=none; d=zohomail.com; s=zohoarc; b=i3rTCHL+pjHa65JwqjBUiVqQSsn4CPDqHexAhoFkZ4RjvzJtPw3GQqcEhPYSNWs1TIbzC0ymRZhn0ByyGZHjZMXTk9IW0b4TFIkKaeiSpw8uMu/zinsubfQ8b286M0E++sO9WsIopig5bdqnAyHfWrXD53H8eurLym3l9dzv4CY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675265868; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=p5oMi4vqXXP60lOEjDof1dT2Hisnu77J0feRmJ3mnDI=; b=fGBoZiEOXvtaf1npDHuD9LVEiTaRxy18Q++Fis0Ap8lg2vQFE0s64mzI23Ehn36LZlqPS2WO8WUdS0qbVMKlJ0bIuoQatS1RZ+0/t2sGf3gczduy3/OUMFF/sdxhzTp95KZo+QSaxvJ73Llr4A3OKzriUaLW6Qh6VXv/RXjDbHQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167526586818238.52746807771791; Wed, 1 Feb 2023 07:37:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNFAZ-0000BO-Vs; Wed, 01 Feb 2023 10:37:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNE33-0007uJ-FG for qemu-devel@nongnu.org; Wed, 01 Feb 2023 09:25:19 -0500 Received: from forward107j.mail.yandex.net ([2a02:6b8:0:801:2::252]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNE30-0001wt-Kc for qemu-devel@nongnu.org; Wed, 01 Feb 2023 09:25:17 -0500 Received: from myt6-265321db07ea.qloud-c.yandex.net (myt6-265321db07ea.qloud-c.yandex.net [IPv6:2a02:6b8:c12:2626:0:640:2653:21db]) by forward107j.mail.yandex.net (Yandex) with ESMTP id D157788508F for ; Wed, 1 Feb 2023 17:24:56 +0300 (MSK) Received: by myt6-265321db07ea.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id uOXl19QY1a61-SdDCngKs; Wed, 01 Feb 2023 17:24:56 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mail; t=1675261496; bh=p5oMi4vqXXP60lOEjDof1dT2Hisnu77J0feRmJ3mnDI=; h=Message-Id:Date:Cc:Subject:To:From; b=D6odFsGwZO8GM05idNieJSHZKrR0QNpiMSBdmniqRMputeDc376c3vkeInGbIXVPi C2UZ72I9KhyAxKm1FVfDJv7ub0QWc4REHb6rVbOXgzkKajVpxZPHegh4+gWWvTZI3w 1sZKRnYZqwKI8txYcs3NYPR9FqdTxJN2O9ljMlBc= Authentication-Results: myt6-265321db07ea.qloud-c.yandex.net; dkim=pass header.i=@syntacore.com From: Ivan Klokov To: qemu-devel@nongnu.org Cc: Ivan Klokov Subject: [PATCH] target/riscv: Add RVV registers to log Date: Wed, 1 Feb 2023 17:24:54 +0300 Message-Id: <20230201142454.109260-1-ivan.klokov@syntacore.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a02:6b8:0:801:2::252; envelope-from=ivan.klokov@syntacore.com; helo=forward107j.mail.yandex.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 01 Feb 2023 10:37:00 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1675265868768100001 Content-Type: text/plain; charset="utf-8" Added QEMU option 'rvv' to add RISC-V RVV registers to log like regular reg= s. Signed-off-by: Ivan Klokov --- accel/tcg/cpu-exec.c | 5 +++++ include/hw/core/cpu.h | 2 ++ include/qemu/log.h | 3 ++- target/riscv/cpu.c | 49 ++++++++++++++++++++++++++++++++++++++++++- util/log.c | 3 +++ 5 files changed, 60 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 04cd1f3092..90e3b79544 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -296,6 +296,11 @@ static void log_cpu_exec(target_ulong pc, CPUState *cp= u, } #if defined(TARGET_I386) flags |=3D CPU_DUMP_CCOP; +#endif +#if defined(TARGET_RISCV) + if (qemu_loglevel_mask(CPU_LOG_RISCV_RVV)) { + flags |=3D CPU_DUMP_RVV; + } #endif cpu_dump_state(cpu, logfile, flags); qemu_log_unlock(logfile); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2417597236..82d90854c5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -543,11 +543,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *c= pu); * @CPU_DUMP_CODE: * @CPU_DUMP_FPU: dump FPU register state, not just integer * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization = state + * @CPU_DUMP_RVV: dump RISC-V RVV registers */ enum CPUDumpFlags { CPU_DUMP_CODE =3D 0x00010000, CPU_DUMP_FPU =3D 0x00020000, CPU_DUMP_CCOP =3D 0x00040000, + CPU_DUMP_RVV =3D 0x00080000, }; =20 /** diff --git a/include/qemu/log.h b/include/qemu/log.h index c5643d8dd5..fb061d75f8 100644 --- a/include/qemu/log.h +++ b/include/qemu/log.h @@ -35,7 +35,8 @@ bool qemu_log_separate(void); /* LOG_STRACE is used for user-mode strace logging. */ #define LOG_STRACE (1 << 19) #define LOG_PER_THREAD (1 << 20) - +/* RISC-V "V" Vector Extension */ +#define CPU_LOG_RISCV_RVV (1 << 21) /* Lock/unlock output. */ =20 FILE *qemu_log_trylock(void) G_GNUC_WARN_UNUSED_RESULT; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 14a7027095..319aac5517 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -154,6 +154,14 @@ const char * const riscv_fpr_regnames[] =3D { "f30/ft10", "f31/ft11" }; =20 +const char * const riscv_rvv_regnames[] =3D { + "v0", "v1", "v2", "v3", "v4", "v5", "v6", + "v7", "v8", "v9", "v10", "v11", "v12", "v13", + "v14", "v15", "v16", "v17", "v18", "v19", "v20", + "v21", "v22", "v23", "v24", "v25", "v26", "v27", + "v28", "v29", "v30", "v31" +}; + static const char * const riscv_excp_names[] =3D { "misaligned_fetch", "fault_fetch", @@ -375,7 +383,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - int i; + int i, j; + uint8_t *p; =20 #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { @@ -459,6 +468,44 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) } } } + if (riscv_has_ext(env, RVV)) { + if (flags & CPU_DUMP_RVV) { + + static const int dump_rvv_csrs[] =3D { + CSR_VSTART, + CSR_VXSAT, + CSR_VXRM, + CSR_VCSR, + CSR_VL, + CSR_VTYPE, + CSR_VLENB, + }; + for (int i =3D 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { + int csrno =3D dump_rvv_csrs[i]; + target_ulong val =3D 0; + RISCVException res =3D riscv_csrrw_debug(env, csrno, &val,= 0, 0); + + /* + * Rely on the smode, hmode, etc, predicates within csr.c + * to do the filtering of the registers that are present. + */ + if (res =3D=3D RISCV_EXCP_NONE) { + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + csr_ops[csrno].name, val); + } + } + uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + + for (i =3D 0; i < 32; i++) { + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); + p =3D (uint8_t *)env->vreg; + for (j =3D 0; j < vlenb; j++) { + qemu_fprintf(f, "%02x", *(p + i * vlenb + j)); + } + qemu_fprintf(f, "\n"); + } + } + } } =20 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/util/log.c b/util/log.c index 7837ff9917..8827109b5c 100644 --- a/util/log.c +++ b/util/log.c @@ -495,6 +495,9 @@ const QEMULogItem qemu_log_items[] =3D { "log every user-mode syscall, its input, and its result" }, { LOG_PER_THREAD, "tid", "open a separate log file per thread; filename must contain '%d'" }, + { CPU_LOG_RISCV_RVV, "rvv", + "RISC-V only: add RISC-V \"V\" Vector Extension registers " + "in the 'cpu' logging" }, { 0, NULL, NULL }, }; =20 --=20 2.34.1