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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id b4-20020a17090a7ac400b0022c35afad5bsm2496763pjl.16.2023.02.01.23.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 23:52:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BC1d9xfabeQA6e7b/ATlm8p465b5RUa/Id8p1TO595Q=; b=EIHgRZHcDMxKy2FpiQwAVVRHI7A4s2kcKcdIHX0zyzFriVxCbPmEBlrH2A7blVjiFU bb7l1GEL7vObvDEma67hT7NuFHfsB+l1K9P7yl/MbYIbx3l1LMj4vwC5wKsc6Dmtn2BP XXcWHnh9UFptfaPO4R2mN2godblZwkdhX1y9SsrRQvbTrKu2H4CaBa3zfh6+BA63hU3a rUf5xBxEiiZJXjx0ynzoyU6881hIziMWrKpcmutK0wHvE8Pn9s6ShNYgVzWljpNGxRcj 93tNQn0XOpoELlwoNj8J86NLbdlJU/oevnV8nVSIsSY0lmjFzBCMtSzHRLvqoopCPG8a TMSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BC1d9xfabeQA6e7b/ATlm8p465b5RUa/Id8p1TO595Q=; b=ns4lYeQJyG8JhO8v7Gp+YWmWqQIIt9DLCz1lNowuk445VZ4xgqTw0kFWnCcpK4RhBg IwRcHZMGtR9QYm4rCxKBJsawno5pGlRA8VtEtaylSpRrfaZ74p5/p0SnvPhI2qNA358v as7XK/oK7BeWlCi3xG+3i0r/qOWtaszml/ZIJnfl4o+QW9OkID7dEHn6R1QxuLvYc+C9 UhrR3O0Z04kFhXi7haJb/fKhsETN/eT4eneIOCAHiw3Pv+eLTrnot6JiuN5fOi92W1p6 TfcZDq3/IpOuCb2C9luYPsaaveYmxLnwiz5U0qPTTXbGIN3sIGJb5icSHLVOhiZbIjZI S9IQ== X-Gm-Message-State: AO0yUKX+VJDUAyHcryNyO/Olg5ZlKXh6ju8dS01m00eNBg6NARR/PjrC Vn4FxVxMQEChgjPG9A9gJnytBelsp4D45HXp X-Google-Smtp-Source: AK7set8IPJj7JNwP6MHgFPexYdKUxFj/DT6Ts8RgK9alxjLYpoeBcQW+5Py5Y6sweQaky8FugtOK9A== X-Received: by 2002:a17:90a:190:b0:22c:8ba1:bd73 with SMTP id 16-20020a17090a019000b0022c8ba1bd73mr5403884pjc.18.1675324372437; Wed, 01 Feb 2023 23:52:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: anders.roxell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 3/4] target/arm: Use FIELD for ARMVAParameters Date: Wed, 1 Feb 2023 21:52:41 -1000 Message-Id: <20230202075242.260793-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202075242.260793-1-richard.henderson@linaro.org> References: <20230202075242.260793-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675324470134100001 Content-Type: text/plain; charset="utf-8" Use hw/registerfields.h instead of bitfields for ARMVAParameters. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 19 ++++++++++++++ target/arm/internals.h | 20 --------------- target/arm/helper.c | 36 +++++++++++++------------- target/arm/pauth_helper.c | 20 +++++++++------ target/arm/ptw.c | 53 +++++++++++++++++++++------------------ 5 files changed, 79 insertions(+), 69 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8cf70693be..e961afe88a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -225,6 +225,25 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; =20 +/* + * Parameters of a given virtual address, as extracted from the + * translation control register (TCR) for a given regime. + */ +typedef uint32_t ARMVAParameters; + FIELD(ARMVAP, SELECT, 0, 1) + FIELD(ARMVAP, TSZ, 1, 8) + FIELD(ARMVAP, TSZ_OOB, 9, 1) /* tsz has been clamped to legal range */ + FIELD(ARMVAP, PS, 10, 3) + FIELD(ARMVAP, SH, 13, 2) + FIELD(ARMVAP, GRAN, 15, 2) + FIELD(ARMVAP, TBID, 17, 1) /* final TBI for data, not TCR TBID fiel= d */ + FIELD(ARMVAP, TBII, 18, 1) /* final TBI for insns */ + FIELD(ARMVAP, EPD, 19, 1) + FIELD(ARMVAP, HPD, 20, 1) + FIELD(ARMVAP, DS, 21, 1) + FIELD(ARMVAP, HA, 22, 1) + FIELD(ARMVAP, HD, 23, 1) + typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; =20 typedef struct CPUArchState { diff --git a/target/arm/internals.h b/target/arm/internals.h index 73b37478bf..2c24c2f39f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1063,26 +1063,6 @@ static inline int arm_granule_bits(ARMGranuleSize gr= an) } } =20 -/* - * Parameters of a given virtual address, as extracted from the - * translation control register (TCR) for a given regime. - */ -typedef struct ARMVAParameters { - unsigned tsz : 8; - unsigned ps : 3; - unsigned sh : 2; - unsigned select : 1; - bool tbid : 1; /* final TBI for data, not the TBID field */ - bool tbii : 1; /* final TBI for insns */ - bool epd : 1; - bool hpd : 1; - bool tsz_oob : 1; /* tsz has been clamped to legal range */ - bool ds : 1; - bool ha : 1; - bool hd : 1; - ARMGranuleSize gran : 2; -} ARMVAParameters; - ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index fda0b9da75..531a4bebb3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4882,7 +4882,7 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env= , ARMMMUIdx mmuidx, gran =3D tlbi_range_tg_to_gran_size(page_size_granule); =20 /* The granule encoded in value must match the granule in use. */ - if (gran !=3D param.gran) { + if (gran !=3D FIELD_EX32(param, ARMVAP, GRAN)) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\= n", page_size_granule); return ret; @@ -4895,12 +4895,12 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *e= nv, ARMMMUIdx mmuidx, =20 ret.length =3D (num + 1) << (exponent + page_shift); =20 - if (param.select) { + if (FIELD_EX32(param, ARMVAP, SELECT)) { ret.base =3D sextract64(value, 0, 37); } else { ret.base =3D extract64(value, 0, 37); } - if (param.ds) { + if (FIELD_EX32(param, ARMVAP, DS)) { /* * With DS=3D1, BaseADDR is always shifted 16 so that it is able * to address all 52 va bits. The input address is perforce @@ -11048,6 +11048,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); bool stage2 =3D regime_is_stage2(mmu_idx); + ARMVAParameters r; =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; @@ -11152,21 +11153,20 @@ ARMVAParameters aa64_va_parameters(CPUARMState *e= nv, uint64_t va, tbid =3D (tbid >> select) & 1; tbii =3D (tbii >> select) & 1; =20 - return (ARMVAParameters) { - .tsz =3D tsz, - .ps =3D ps, - .sh =3D sh, - .select =3D select, - .tbid =3D tbid, - .tbii =3D tbii, - .epd =3D epd, - .hpd =3D hpd, - .tsz_oob =3D tsz_oob, - .ds =3D ds, - .ha =3D ha, - .hd =3D ha && hd, - .gran =3D gran, - }; + r =3D FIELD_DP32(0, ARMVAP, SELECT, select); + r =3D FIELD_DP32(r, ARMVAP, TSZ, tsz); + r =3D FIELD_DP32(r, ARMVAP, TSZ_OOB, tsz_oob); + r =3D FIELD_DP32(r, ARMVAP, PS, ps); + r =3D FIELD_DP32(r, ARMVAP, SH, sh); + r =3D FIELD_DP32(r, ARMVAP, GRAN, gran); + r =3D FIELD_DP32(r, ARMVAP, TBID, tbid); + r =3D FIELD_DP32(r, ARMVAP, TBII, tbii); + r =3D FIELD_DP32(r, ARMVAP, EPD, epd); + r =3D FIELD_DP32(r, ARMVAP, HPD, hpd); + r =3D FIELD_DP32(r, ARMVAP, DS, ds); + r =3D FIELD_DP32(r, ARMVAP, HA, ha); + r =3D FIELD_DP32(r, ARMVAP, HD, ha && hd); + return r; } =20 /* diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index bfed6f9722..1dffcef6c3 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -296,7 +296,9 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t= ptr, uint64_t modifier, ARMVAParameters param =3D aa64_va_parameters(env, ptr, mmu_idx); uint64_t pac, ext_ptr, ext, test; int bot_bit, top_bit; - bool tbi =3D data ? param.tbid : param.tbii; + bool tbi =3D (data ? FIELD_EX32(param, ARMVAP, TBID) + : FIELD_EX32(param, ARMVAP, TBII)); + int tsz =3D FIELD_EX32(param, ARMVAP, TSZ); =20 /* If tagged pointers are in use, use ptr<55>, otherwise ptr<63>. */ if (tbi) { @@ -307,7 +309,7 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t= ptr, uint64_t modifier, =20 /* Build a pointer with known good extension bits. */ top_bit =3D 64 - 8 * tbi; - bot_bit =3D 64 - param.tsz; + bot_bit =3D 64 - tsz; ext_ptr =3D deposit64(ptr, bot_bit, top_bit - bot_bit, ext); =20 pac =3D pauth_computepac(env, ext_ptr, modifier, *key); @@ -355,13 +357,15 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t= ptr, uint64_t modifier, { ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); ARMVAParameters param =3D aa64_va_parameters(env, ptr, mmu_idx); - bool tbi =3D data ? param.tbid : param.tbii; + bool tbi =3D (data ? FIELD_EX32(param, ARMVAP, TBID) + : FIELD_EX32(param, ARMVAP, TBII)); + int tsz =3D FIELD_EX32(param, ARMVAP, TSZ); int bot_bit, top_bit; uint64_t pac, orig_ptr, test; =20 - orig_ptr =3D pauth_original_ptr(ptr, param.tsz, tbi); + orig_ptr =3D pauth_original_ptr(ptr, tsz, tbi); pac =3D pauth_computepac(env, orig_ptr, modifier, *key); - bot_bit =3D 64 - param.tsz; + bot_bit =3D 64 - tsz; top_bit =3D 64 - 8 * tbi; =20 test =3D (pac ^ ptr) & ~MAKE_64BIT_MASK(55, 1); @@ -380,9 +384,11 @@ static uint64_t pauth_strip(CPUARMState *env, uint64_t= ptr, bool data) { ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); ARMVAParameters param =3D aa64_va_parameters(env, ptr, mmu_idx); - bool tbi =3D data ? param.tbid : param.tbii; + bool tbi =3D (data ? FIELD_EX32(param, ARMVAP, TBID) + : FIELD_EX32(param, ARMVAP, TBII)); + int tsz =3D FIELD_EX32(param, ARMVAP, TSZ); =20 - return pauth_original_ptr(ptr, param.tsz, tbi); + return pauth_original_ptr(ptr, tsz, tbi); } =20 static G_NORETURN diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a19d714985..ec3b18e981 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1014,6 +1014,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState= *env, uint32_t va, { uint64_t tcr =3D regime_tcr(env, mmu_idx); uint32_t el =3D regime_el(env, mmu_idx); + ARMVAParameters r; int select, tsz; bool epd, hpd; =20 @@ -1065,12 +1066,11 @@ static ARMVAParameters aa32_va_parameters(CPUARMSta= te *env, uint32_t va, hpd &=3D extract32(tcr, 6, 1); } =20 - return (ARMVAParameters) { - .tsz =3D tsz, - .select =3D select, - .epd =3D epd, - .hpd =3D hpd, - }; + r =3D FIELD_DP32(0, ARMVAP, SELECT, select); + r =3D FIELD_DP32(r, ARMVAP, TSZ, tsz); + r =3D FIELD_DP32(r, ARMVAP, EPD, epd); + r =3D FIELD_DP32(r, ARMVAP, HPD, hpd); + return r; } =20 /* @@ -1205,13 +1205,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, * With FEAT_LVA, fault on less than minimum becomes required, * so our choice is to always raise the fault. */ - if (param.tsz_oob) { + if (FIELD_EX32(param, ARMVAP, TSZ_OOB)) { goto do_translation_fault; } =20 - addrsize =3D access_type =3D=3D MMU_INST_FETCH ? param.tbii : para= m.tbid; + if (access_type =3D=3D MMU_INST_FETCH) { + addrsize =3D FIELD_EX32(param, ARMVAP, TBII); + } else { + addrsize =3D FIELD_EX32(param, ARMVAP, TBID); + } addrsize =3D 64 - 8 * addrsize; - inputsize =3D 64 - param.tsz; + inputsize =3D 64 - FIELD_EX32(param, ARMVAP, TSZ); =20 /* * Bound PS by PARANGE to find the effective output address size. @@ -1219,7 +1223,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * supported mappings can be considered an implementation error. */ ps =3D FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); - ps =3D MIN(ps, param.ps); + ps =3D MIN(ps, FIELD_EX32(param, ARMVAP, PS)); assert(ps < ARRAY_SIZE(pamax_map)); outputsize =3D pamax_map[ps]; =20 @@ -1227,14 +1231,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, * With LPA2, the effective output address (OA) size is at most 48= bits * unless TCR.DS =3D=3D 1 */ - if (!param.ds && param.gran !=3D Gran64K) { + if (!FIELD_EX32(param, ARMVAP, DS) && + FIELD_EX32(param, ARMVAP, GRAN) !=3D Gran64K) { outputsize =3D MIN(outputsize, 48); } } else { param =3D aa32_va_parameters(env, address, mmu_idx); level =3D 1; addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_Stage2 ? 40 : 32); - inputsize =3D addrsize - param.tsz; + inputsize =3D addrsize - FIELD_EX32(param, ARMVAP, TSZ); outputsize =3D 40; } =20 @@ -1250,13 +1255,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, if (inputsize < addrsize) { target_ulong top_bits =3D sextract64(address, inputsize, addrsize - inputsize); - if (-top_bits !=3D param.select) { + if (-top_bits !=3D FIELD_EX32(param, ARMVAP, SELECT)) { /* The gap between the two regions is a Translation fault */ goto do_translation_fault; } } =20 - stride =3D arm_granule_bits(param.gran) - 3; + stride =3D arm_granule_bits(FIELD_EX32(param, ARMVAP, GRAN)) - 3; =20 /* * Note that QEMU ignores shareability and cacheability attributes, @@ -1266,14 +1271,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, * implement any ASID-like capability so we can ignore it (instead * we will always flush the TLB any time the ASID is changed). */ - ttbr =3D regime_ttbr(env, mmu_idx, param.select); + ttbr =3D regime_ttbr(env, mmu_idx, FIELD_EX32(param, ARMVAP, SELECT)); =20 /* * Here we should have set up all the parameters for the translation: * inputsize, ttbr, epd, stride, tbi */ =20 - if (param.epd) { + if (FIELD_EX32(param, ARMVAP, EPD)) { /* * Translation table walk disabled =3D> Translation fault on TLB m= iss * Note: This is always 0 on 64-bit EL2 and EL3. @@ -1306,7 +1311,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, bool ok; =20 /* SL2 is RES0 unless DS=3D1 & 4kb granule. */ - if (param.ds && stride =3D=3D 9 && sl2) { + if (FIELD_EX32(param, ARMVAP, DS) && stride =3D=3D 9 && sl2) { if (sl0 !=3D 0) { level =3D 0; goto do_translation_fault; @@ -1368,7 +1373,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * For AArch64, the address field goes up to bit 47, or 49 with FEAT_L= PA2; * the highest bits of a 52-bit output are placed elsewhere. */ - if (param.ds) { + if (FIELD_EX32(param, ARMVAP, DS)) { descaddrmask =3D MAKE_64BIT_MASK(0, 50); } else if (arm_feature(env, ARM_FEATURE_V8)) { descaddrmask =3D MAKE_64BIT_MASK(0, 48); @@ -1425,7 +1430,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * raise AddressSizeFault. */ if (outputsize > 48) { - if (param.ds) { + if (FIELD_EX32(param, ARMVAP, DS)) { descaddr |=3D extract64(descriptor, 8, 2) << 50; } else { descaddr |=3D extract64(descriptor, 12, 4) << 48; @@ -1470,7 +1475,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * Otherwise, pass the access fault on to software. */ if (!(descriptor & (1 << 10))) { - if (param.ha) { + if (FIELD_EX32(param, ARMVAP, HA)) { new_descriptor |=3D 1 << 10; /* AF */ } else { fi->type =3D ARMFault_AccessFlag; @@ -1484,7 +1489,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * bit for writeback. The actual write protection test may still be * overridden by tableattrs, to be merged below. */ - if (param.hd + if (FIELD_EX32(param, ARMVAP, HD) && extract64(descriptor, 51, 1) /* DBM */ && access_type =3D=3D MMU_DATA_STORE) { if (regime_is_stage2(mmu_idx)) { @@ -1504,7 +1509,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, attrs =3D new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(5= 0, 14)); if (!regime_is_stage2(mmu_idx)) { attrs |=3D nstable << 5; /* NS */ - if (!param.hpd) { + if (!FIELD_EX32(param, ARMVAP, HPD)) { attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* * The sense of AP[1] vs APTable[0] is reversed, as APTable[0]= =3D=3D 1 @@ -1582,8 +1587,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * was re-purposed for output address bits. The SH attribute in * that case comes from TCR_ELx, which we extracted earlier. */ - if (param.ds) { - result->cacheattrs.shareability =3D param.sh; + if (FIELD_EX32(param, ARMVAP, DS)) { + result->cacheattrs.shareability =3D FIELD_EX32(param, ARMVAP, SH); } else { result->cacheattrs.shareability =3D extract32(attrs, 8, 2); } --=20 2.34.1