From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331069; cv=none; d=zohomail.com; s=zohoarc; b=oG6UgtlR7UHfSAyCMBoKAQ6jXQwyxj3uLau6oJSzf3jfPNb2T/noi55+BkquwBfV2XoQpCgG0/3Ae3gekFvvQHm4BeTfAIq8u71ziKiw4UHSp8DT5MmUhTqsVd/QiOSIGKNGYkwzVJ+l0INSAl2fFfDX4Oi2JSzEoCjzwID2dn8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331069; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VTHF01Hm6wbm7Vvnd8N/KqcTL14e1JMdyI53J6BLKd8=; b=E6U+X391dZsK8i2+fNH6APTQBXs97M/fAFq2ayvYn+fmj6FcUnx/PtK4wd/bTNH8qhODP48WK5N4xVU+IMTQNZd0Ll2vzA5ono2W7pXWeSFfdSMEOPoVtLMlJj5FuHi9VdMsMWC0bAduM3MqcZzD8x7jBdLd5C6A0b9HLSW5MfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167533106973297.25556050830448; Thu, 2 Feb 2023 01:44:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW7p-0006Se-7G; Thu, 02 Feb 2023 04:43:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW7m-0006Rm-Of for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:23 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW7k-0006ND-Ow for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:22 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:00 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:41:57 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331000; x=1706867000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=atvZGepej5YcLFtx3mYUNr9UNgjfXy1ME0XpKL0DymQ=; b=baNB6jqnvooBC028OvVj+kV3EURuTfOg3s5P/D3vcQBn4hAHXZRQC/vg 1UsZVPKd2pZXZrdHn4JhrD/koGD56ZKkgDqSQH7bVrN1Cjcg5pVkdhJD+ 0v44vj4q7sHBw9p4o0Ssu/btq352rZ83CDIze91Gt+jPY2qguFGRjs6AJ 2ErzST4DzHFLX3nRgsFLxN9uQYPELIGJ+ecA/VnFhfvUegESZhR/w7/u5 /VU8ej1fWNbieS5jiSPjh7nh/zoJyszC0dZWuG68zeQrVb8LxRsRvx+ri brSCEBJq2VVY5V2R6gomwgpPWHtsBopO/RnwSuGSAxWodOXnBsAJrwPTl Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316401881" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316401881" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909371" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909371" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Robert Hoo Subject: [PATCH 01/18] machine: Fix comment of machine_parse_smp_config() Date: Thu, 2 Feb 2023 17:49:12 +0800 Message-Id: <20230202094929.343799-2-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331070269100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Now smp supports dies and clusters, so add description about these 2 levels in the comment of machine_parse_smp_config(). Fixes: 864c3b5 (hw/core/machine: Introduce CPU cluster topology support) Suggested-by: Robert Hoo Signed-off-by: Zhao Liu --- hw/core/machine-smp.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index c3dab007dadc..3fd9e641efde 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -51,8 +51,8 @@ static char *cpu_hierarchy_to_string(MachineState *ms) * machine_parse_smp_config: Generic function used to parse the given * SMP configuration * - * Any missing parameter in "cpus/maxcpus/sockets/cores/threads" will be - * automatically computed based on the provided ones. + * Any missing parameter in "cpus/maxcpus/sockets/dies/clusters/cores/thre= ads" + * will be automatically computed based on the provided ones. * * In the calculation of omitted sockets/cores/threads: we prefer sockets * over cores over threads before 6.2, while preferring cores over sockets @@ -66,7 +66,8 @@ static char *cpu_hierarchy_to_string(MachineState *ms) * * For compatibility, apart from the parameters that will be computed, new= ly * introduced topology members which are likely to be target specific shou= ld - * be directly set as 1 if they are omitted (e.g. dies for PC since 4.1). + * be directly set as 1 if they are omitted (e.g. dies for PC since v4.1 a= nd + * clusters for arm since v7.0). */ void machine_parse_smp_config(MachineState *ms, const SMPConfiguration *config, Error **errp) --=20 2.34.1 From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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d="scan'208";a="316401903" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909378" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909378" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH 02/18] tests: Rename test-x86-cpuid.c to test-x86-apicid.c Date: Thu, 2 Feb 2023 17:49:13 +0800 Message-Id: <20230202094929.343799-3-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331233869100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu In fact, this unit tests APIC ID other than CPUID. Rename to test-x86-apicid.c to make its name more in line with its actual content. Signed-off-by: Zhao Liu --- MAINTAINERS | 2 +- tests/unit/meson.build | 4 ++-- tests/unit/{test-x86-cpuid.c =3D> test-x86-apicid.c} | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) rename tests/unit/{test-x86-cpuid.c =3D> test-x86-apicid.c} (99%) diff --git a/MAINTAINERS b/MAINTAINERS index c581c11a645a..a6a0c7fe5795 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1674,7 +1674,7 @@ F: include/hw/southbridge/piix.h F: hw/misc/sga.c F: hw/isa/apm.c F: include/hw/isa/apm.h -F: tests/unit/test-x86-cpuid.c +F: tests/unit/test-x86-apicid.c F: tests/qtest/test-x86-cpuid-compat.c =20 PC Chipset diff --git a/tests/unit/meson.build b/tests/unit/meson.build index ffa444f4323c..a9df2843e92e 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -20,8 +20,8 @@ tests =3D { 'test-opts-visitor': [testqapi], 'test-visitor-serialization': [testqapi], 'test-bitmap': [], - # all code tested by test-x86-cpuid is inside topology.h - 'test-x86-cpuid': [], + # all code tested by test-x86-apicid is inside topology.h + 'test-x86-apicid': [], 'test-cutils': [], 'test-div128': [], 'test-shift128': [], diff --git a/tests/unit/test-x86-cpuid.c b/tests/unit/test-x86-apicid.c similarity index 99% rename from tests/unit/test-x86-cpuid.c rename to tests/unit/test-x86-apicid.c index bfabc0403a1a..2b104f86d7c2 100644 --- a/tests/unit/test-x86-cpuid.c +++ b/tests/unit/test-x86-apicid.c @@ -1,5 +1,5 @@ /* - * Test code for x86 CPUID and Topology functions + * Test code for x86 APIC ID and Topology functions * * Copyright (c) 2012 Red Hat Inc. * --=20 2.34.1 From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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d="scan'208";a="316401926" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909388" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909388" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Zhuocheng Ding Subject: [PATCH 03/18] softmmu: Fix CPUSTATE.nr_cores' calculation Date: Thu, 2 Feb 2023 17:49:14 +0800 Message-Id: <20230202094929.343799-4-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331044526100003 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding From CPUState.nr_cores' comment, it represents "number of cores within this CPU package". After 003f230 (machine: Tweak the order of topology members in struct CpuTopology), the meaning of smp.cores changed to "the number of cores in one die", but this commit missed to change CPUState.nr_cores' caculation, so that CPUState.nr_cores became wrong and now it misses to consider numbers of clusters and dies. At present, only i386 is using CPUState.nr_cores. But as for i386, which supports die level, the uses of CPUState.nr_cores are very confusing: Early uses are based on the meaning of "cores per package" (before die is introduced into i386), and later uses are based on "cores per die" (after die's introduction). This difference is due to that commit a94e142 (target/i386: Add CPUID.1F generation support for multi-dies PCMachine) misunderstood that CPUState.nr_cores means "cores per die" when caculated CPUID.1FH.01H:EBX. After that, the changes in i386 all followed this wrong understanding. With the influence of 003f230 and a94e142, for i386 currently the result of CPUState.nr_cores is "cores per die", thus the original uses of CPUState.cores based on the meaning of "cores per package" are wrong when mutiple dies exist: 1. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.01H:EBX[bits 23:16] is incorrect because it expects "cpus per package" but now the result is "cpus per die". 2. In cpu_x86_cpuid() of target/i386/cpu.c, for all leaves of CPUID.04H: EAX[bits 31:26] is incorrect because they expect "cpus per package" but now the result is "cpus per die". The error not only impacts the EAX caculation in cache_info_passthrough case, but also impacts other cases of setting cache topology for Intel CPU according to cpu topology (specifically, the incoming parameter "num_cores" expects "cores per package" in encode_cache_cpuid4()). 3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.0BH.01H:EBX[bits 15:00] is incorrect because the EBX of 0BH.01H (core level) expects "cpus per package", which may be different with 1FH.01H (The reason is 1FH can support more levels. For QEMU, 1FH also supports die, 1FH.01H:EBX[bits 15:00] expects "cpus per die"). 4. In cpu_x86_cpuid() of target/i386/cpu.c, when CPUID.80000001H is caculated, here "cpus per package" is expected to be checked, but in fact, now it checks "cpus per die". Though "cpus per die" also works for this code logic, this isn't consistent with AMD's APM. 5. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.80000008H:ECX expects "cpus per package" but it obtains "cpus per die". 6. In simulate_rdmsr() of target/i386/hvf/x86_emu.c, in kvm_rdmsr_core_thread_count() of target/i386/kvm/kvm.c, and in helper_rdmsr() of target/i386/tcg/sysemu/misc_helper.c, MSR_CORE_THREAD_COUNT expects "cpus per package" and "cores per package", but in these functions, it obtains "cpus per die" and "cores per die". On the other hand, these uses are correct now (they are added in/after a94e142): 1. In cpu_x86_cpuid() of target/i386/cpu.c, topo_info.cores_per_die meets the actual meaning of CPUState.nr_cores ("cores per die"). 2. In cpu_x86_cpuid() of target/i386/cpu.c, vcpus_per_socket (in CPUID. 04H's caculation) considers number of dies, so it's correct. 3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.1FH.01H:EBX[bits 15:00] needs "cpus per die" and it gets the correct result, and CPUID.1FH.02H:EBX[bits 15:00] gets correct "cpus per package". When CPUState.nr_cores is correctly changed to "cores per package" again , the above errors will be fixed without extra work, but the "currently" correct cases will go wrong and need special handling to pass correct "cpus/cores per die" they want. Thus in this patch, we fix CPUState.nr_cores' caculation to fit the original meaning "cores per package", as well as changing caculation of topo_info.cores_per_die, vcpus_per_socket and CPUID.1FH. In addition, in the nr_threads' comment, specify it represents the number of threads in the "core" to avoid confusion. Fixes: a94e142 (target/i386: Add CPUID.1F generation support for multi-dies= PCMachine) Fixes: 003f230 (machine: Tweak the order of topology members in struct CpuT= opology) Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- include/hw/core/cpu.h | 2 +- softmmu/cpus.c | 2 +- target/i386/cpu.c | 9 ++++----- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2417597236bc..5253e4e839bb 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -274,7 +274,7 @@ struct qemu_work_item; * QOM parent. * @tcg_cflags: Pre-computed cflags for this cpu. * @nr_cores: Number of cores within this CPU package. - * @nr_threads: Number of threads within this CPU. + * @nr_threads: Number of threads within this CPU core. * @running: #true if CPU is currently running (lockless). * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; * valid under cpu_list_lock. diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 9cbc8172b5f2..9996e6a3b295 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -630,7 +630,7 @@ void qemu_init_vcpu(CPUState *cpu) { MachineState *ms =3D MACHINE(qdev_get_machine()); =20 - cpu->nr_cores =3D ms->smp.cores; + cpu->nr_cores =3D ms->smp.dies * ms->smp.clusters * ms->smp.cores; cpu->nr_threads =3D ms->smp.threads; cpu->stopped =3D true; cpu->random_seed =3D qemu_guest_random_seed_thread_part1(); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4d2b8d0444df..29afec12c281 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5218,7 +5218,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, X86CPUTopoInfo topo_info; =20 topo_info.dies_per_pkg =3D env->nr_dies; - topo_info.cores_per_die =3D cs->nr_cores; + topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; topo_info.threads_per_core =3D cs->nr_threads; =20 /* Calculate & apply limits for different index ranges */ @@ -5294,8 +5294,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, */ if (*eax & 31) { int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); - int vcpus_per_socket =3D env->nr_dies * cs->nr_cores * - cs->nr_threads; + int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { *eax &=3D ~0xFC000000; *eax |=3D (pow2ceil(cs->nr_cores) - 1) << 26; @@ -5468,12 +5467,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, break; case 1: *eax =3D apicid_die_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D env->nr_dies * cs->nr_cores * cs->nr_threads; + *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; break; default: --=20 2.34.1 From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331260; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Robert Hoo Subject: [PATCH 04/18] i386/cpu: Fix number of addressable IDs in CPUID.04H Date: Thu, 2 Feb 2023 17:49:15 +0800 Message-Id: <20230202094929.343799-5-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331262001100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu For i-cache and d-cache, the maximum IDs for CPUs sharing cache ( CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are both 0, and this means i-cache and d-cache are shared in the SMT level. This is correct if there's single thread per core, but is wrong for the hyper threading case (one core contains multiple threads) since the i-cache and d-cache are shared in the core level other than SMT level. Therefore, in order to be compatible with both multi-threaded and single-threaded situations, we should set i-cache and d-cache be shared at the core level by default. Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the nearest power-of-2 integer. The nearest power-of-2 integer can be caculated by pow2ceil() or by using APIC ID offset (like L3 topology using 1 << die_offset [3]). But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] are associated with APIC ID. For example, in linux kernel, the field "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not matched with actual core numbers and it's caculated by: "(1 << (pkg_offset - core_offset)) - 1". Therefore the offset of APIC ID should be preferred to caculate nearest power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26]: 1. d/i cache is shared in a core, 1 << core_offset should be used instand of "1" in encode_cache_cpuid4() for CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. 2. L2 cache is supposed to be shared in a core as for now, thereby 1 << core_offset should also be used instand of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be replaced by the offsets upper SMT level in APIC ID. And since [1] and [2] are good enough to make cache_into_passthrough work well, its "pow2ceil()" uses are enough so that they're no need to be replaced by APIC ID offset way. [1]: efb3934 (x86: cpu: make sure number of addressable IDs for processor c= ores meets the spec) [2]: d7caf13 (x86: cpu: fixup number of addressable IDs for logical process= ors sharing cache) [3]: d65af28 (i386: Update new x86_apicid parsing rules with die_offset sup= port) Fixes: 7e3482f (i386: Helpers to encode cache information consistently) Suggested-by: Robert Hoo Signed-off-by: Zhao Liu --- target/i386/cpu.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 29afec12c281..7833505092d8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5212,7 +5212,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); - uint32_t die_offset; uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; @@ -5308,27 +5307,38 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; + int addressable_cores_offset =3D apicid_pkg_offset(&topo_info)= - + apicid_core_offset(&topo_info); + int core_offset, die_offset; + switch (count) { case 0: /* L1 dcache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - 1, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - 1, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), cs->nr_cores, + (1 << die_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; } --=20 2.34.1 From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331276; cv=none; d=zohomail.com; s=zohoarc; b=CvtPAhqBxCewg9sGyLCDy1CBaMR1MphGrxiLq1cO87/7m0RDMnAb0ScFN6Mtrr8HAvBiWHjVJT5HldFtrY59uNZQbQFi6DokVq8v7lzcO5t1AlX/6HF6UmTdtIIV+zxYIPR1TQMRGCGR1nMx9dUjxSnAjmhb3KkLdi14y2IFuBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331276; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yE9LxB8Gd766LKE14ItI4CvpjZXkHqmYkNujYZ6Pll4=; b=D/IBX0NCOKg215sllB/FJJxfPG6wKSsCytVdYfOQm2yBRRbpcMtYIJiTm1uszajLOYcC1h0UzWhE/dvGCOPkkoxYhtBNBjj66i3foT9nAfQABQRYFgJ384arR2Ty+Bzx2sMiBRZB4GN6M4auqqrFZKv02tWrFJsFgwekO7HgQzQ= ARC-Authentication-Results: i=1; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Robert Hoo Subject: [PATCH 05/18] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Date: Thu, 2 Feb 2023 17:49:16 +0800 Message-Id: <20230202094929.343799-6-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331278070100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu In cpu_x86_cpuid(), there are many variables in representing the cpu topology, e.g., topo_info, cs->nr_cores/cs->nr_threads. Since the names of cs->nr_cores/cs->nr_threads does not accurately represent its meaning, the use of cs->nr_cores/cs->nr_threads is prone to confusion and mistakes. And the structure X86CPUTopoInfo names its memebers clearly, thus the variable "topo_info" should be preferred. Suggested-by: Robert Hoo Signed-off-by: Zhao Liu --- target/i386/cpu.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7833505092d8..4cda84eb96f1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5215,11 +5215,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; + uint32_t cpus_per_pkg; =20 topo_info.dies_per_pkg =3D env->nr_dies; topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; topo_info.threads_per_core =3D cs->nr_threads; =20 + cpus_per_pkg =3D topo_info.dies_per_pkg * topo_info.cores_per_die * + topo_info.threads_per_core; + /* Calculate & apply limits for different index ranges */ if (index >=3D 0xC0000000) { limit =3D env->cpuid_xlevel2; @@ -5255,8 +5259,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx |=3D CPUID_EXT_OSXSAVE; } *edx =3D env->features[FEAT_1_EDX]; - if (cs->nr_cores * cs->nr_threads > 1) { - *ebx |=3D (cs->nr_cores * cs->nr_threads) << 16; + if (cpus_per_pkg > 1) { + *ebx |=3D cpus_per_pkg << 16; *edx |=3D CPUID_HT; } if (!cpu->enable_pmu) { @@ -5293,10 +5297,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, */ if (*eax & 31) { int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); - int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; - if (cs->nr_cores > 1) { + int vcpus_per_socket =3D cpus_per_pkg; + int cores_per_socket =3D topo_info.cores_per_die * + topo_info.dies_per_pkg; + if (cores_per_socket > 1) { *eax &=3D ~0xFC000000; - *eax |=3D (pow2ceil(cs->nr_cores) - 1) << 26; + *eax |=3D (pow2ceil(cores_per_socket) - 1) << 26; } if (host_vcpus_per_cache > vcpus_per_socket) { *eax &=3D ~0x3FFC000; @@ -5436,12 +5442,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, switch (count) { case 0: *eax =3D apicid_core_offset(&topo_info); - *ebx =3D cs->nr_threads; + *ebx =3D topo_info.threads_per_core; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D cpus_per_pkg; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; default: @@ -5472,7 +5478,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, switch (count) { case 0: *eax =3D apicid_core_offset(&topo_info); - *ebx =3D cs->nr_threads; + *ebx =3D topo_info.threads_per_core; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: @@ -5482,7 +5488,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 2: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D cpus_per_pkg; *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; break; default: @@ -5707,7 +5713,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * discards multiple thread information if it is set. * So don't set it here for Intel to make Linux guests happy. */ - if (cs->nr_cores * cs->nr_threads > 1) { + if (cpus_per_pkg > 1) { if (env->cpuid_vendor1 !=3D CPUID_VENDOR_INTEL_1 || env->cpuid_vendor2 !=3D CPUID_VENDOR_INTEL_2 || env->cpuid_vendor3 !=3D CPUID_VENDOR_INTEL_3) { @@ -5769,7 +5775,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax |=3D (cpu_x86_virtual_addr_width(env) << 8); } *ebx =3D env->features[FEAT_8000_0008_EBX]; - if (cs->nr_cores * cs->nr_threads > 1) { + if (cpus_per_pkg > 1) { /* * Bits 15:12 is "The number of bits in the initial * Core::X86::Apic::ApicId[ApicId] value that indicate @@ -5777,7 +5783,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * Bits 7:0 is "The number of threads in the package is NC+1" */ *ecx =3D (apicid_pkg_offset(&topo_info) << 12) | - ((cs->nr_cores * cs->nr_threads) - 1); + (cpus_per_pkg - 1); } else { *ecx =3D 0; } --=20 2.34.1 From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331059; cv=none; d=zohomail.com; s=zohoarc; b=bKBSem16iU4kv02OwA3uAOWtYG0WNQOKFsblIT/BHhRvhGhfiS6iDwVM5+VQlhdyLFWejVa9BDzo8kOvpV3zFGUVKJ2KXCAx05lE5ulFsvoAQvSig/Zt9E3krxOltQ8KxjYfuZpt5vamC1uGpCVOwQOGLs+Grz3gVsHzlY1/2jI= ARC-Message-Signature: i=1; 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bh=DCitsdkqVqn+K7XTRwzMXR+GwDLS8VcH7odqeMqM8ig=; b=ggyx+NF5x/qepMc3Xf+SWTeaK4SE0C5R4IfFmLbSG5ff8+IBPZATZLkL aJaVXGJ6wHm/NMB9/Kj8rJjpBK7EmcHwU50lV9uncOSyKedw8XSPDm6gh lfTFmPohVujjDCKFN6grH+aNAmpo0n5TgkKB+uJ3MXub0mj3BASp1ki4H mevvc/uJYiRhTo+tfnC/SmJZDtSoQD3W6Nq/9z9EJ9oSsQikiw5kqn6HP KVJ6NKutoMPIi6mOw3mMBn9gSmiKoL2ECulzf2f8ypZCzNT1n0sreqL9i ZOW1voI4LwzTTLHwHRVMk1eosWN/t6mTudnFbGgkdrzq4mYSSdvwU7W96 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316401981" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316401981" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909422" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909422" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Zhuocheng Ding Subject: [PATCH 06/18] i386: Introduce module-level cpu topology to CPUX86State Date: Thu, 2 Feb 2023 17:49:17 +0800 Message-Id: <20230202094929.343799-7-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331060237100001 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding smp command has the "clusters" parameter but x86 hasn't supported that level. Though "clusters" was introduced to help define L2 cache topology [1], using cluster to define x86's L2 cache topology will cause the compatibility problem: Currently, x86 defaults that the L2 cache is shared in one core, which actually implies a default setting "cores per L2 cache is 1" and therefore implicitly defaults to having as many L2 caches as cores. For example (i386 PC machine): -smp 16,sockets=3D2,dies=3D2,cores=3D2,threads=3D2,maxcpus=3D16 (*) Considering the topology of the L2 cache, this (*) implicitly means "1 core per L2 cache" and "2 L2 caches per die". If we use cluster to configure L2 cache topology with the new default setting "clusters per L2 cache is 1", the above semantics will change to "2 cores per cluster" and "1 cluster per L2 cache", that is, "2 cores per L2 cache". So the same command (*) will cause changes in the L2 cache topology, further affecting the performance of the virtual machine. Therefore, x86 should only treat cluster as a cpu topology level and avoid using it to change L2 cache by default for compatibility. "cluster" in smp is the CPU topology level which is between "core" and die. For x86, the "cluster" in smp is corresponding to the module level [2], which is above the core level. So use the "module" other than "cluster" in i386 code. And please note that x86 already has a cpu topology level also named "cluster" [2], this level is at the upper level of the package. Here, the cluster in x86 cpu topology is completely different from the "clusters" as the smp parameter. After the module level is introduced, the cluster as the smp parameter will actually refer to the module level of x86. [1]: 0d87178 (hw/core/machine: Introduce CPU cluster topology support) [2]: SDM, vol.3, ch.9, 9.9.1 Hierarchical Mapping of Shared Resources. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- hw/i386/x86.c | 1 + target/i386/cpu.c | 1 + target/i386/cpu.h | 6 ++++++ 3 files changed, 8 insertions(+) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 78cc131926c8..66902d1c0923 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -305,6 +305,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, init_topo_info(&topo_info, x86ms); =20 env->nr_dies =3D ms->smp.dies; + env->nr_modules =3D ms->smp.clusters; =20 /* * If APIC ID is not set, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4cda84eb96f1..61ec9a7499b8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6781,6 +6781,7 @@ static void x86_cpu_initfn(Object *obj) CPUX86State *env =3D &cpu->env; =20 env->nr_dies =3D 1; + env->nr_modules =3D 1; cpu_set_cpustate_pointers(cpu); =20 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc19577a21..f3afea765982 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1810,7 +1810,13 @@ typedef struct CPUArchState { =20 TPRAccess tpr_access_type; =20 + /* Number of dies per package. */ unsigned nr_dies; + /* + * Number of modules per die. Module level in x86 cpu topology is + * corresponding to smp.clusters. + */ + unsigned nr_modules; } CPUX86State; =20 struct kvm_msrs; --=20 2.34.1 From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331055; cv=none; d=zohomail.com; s=zohoarc; b=LMvIHQtrgXXAaL5oN+2xyp4vKJFPrd+qwshrlb2TkEqwnLdOboGpIet8u1Zxv+HhcWQov+bjeFq37zfH0tUjS1NnlS9L34W9uEBe07oWaeC6T/wZo3QLywKMgTwCYNTyjhgEUleBwewSXL3EmcQqHhC/zf+FMOkmTPn5Fv+8+qg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331055; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kHttYvN0yz5sAsGDKaEU7tqWqaCHjTYwqOXvUj0Bdx4=; b=ZAlDNOJbQmXabFJAwXbgQ6hIqHhiK+roxyORqd+rWk0dhpYO5s43O/nFKPDjl+KKhGClBjvq9pCy0ABplu326XCLOKMezvV6lZ76a8s/k3lX1v5pL7WGiMZUhyMZlb0uYBmcboREbbWv26hQDZcHdeErMhBpfqRZPvARr7MsUxU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16753310549571006.1300981280897; Thu, 2 Feb 2023 01:44:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW7x-0006Vr-ED; Thu, 02 Feb 2023 04:43:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW7v-0006VB-Hy for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:31 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW7t-0006Of-7M for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:31 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:16 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:42:13 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331009; x=1706867009; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8LpJM4YYW9cXnTY41XXzqpE7edulF0GqJwg1J5FaJ+o=; b=lqAHYHuPFdrDQ1eNYpouI0Ke9VcFriZw2X56i4sroRACE3G9Vk94RL2Z g9x17tq+EPKGyfHQMowL00pXdtO1f/UnfRUsVGH+7IlaM0yRtxqzl19HL Pv9GFGuhB1bpDQTSDl+qyyGicQb+MjRUae5KZgKzSYVMm2iI5oEblc9eo BSP/cQiNbeAKDT/0BdFCtLjwOASWW1R5PuVPlKlLCIMYFuwTWJdGikZ+0 KKPpd/IzlUVV04GAHo5SYXupuAN1BVavF75vXDHXSQ7gtytsHFjZWSqjd /qhnjeb2DObACCUjSlnrr/+BJImwz11FShFn4Dlag4n/IhAm0mQx4Suq1 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402002" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402002" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909437" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909437" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Zhuocheng Ding Subject: [PATCH 07/18] i386: Support modules_per_die in X86CPUTopoInfo Date: Thu, 2 Feb 2023 17:49:18 +0800 Message-Id: <20230202094929.343799-8-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331056457100003 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding Support module level in i386 cpu topology structure "X86CPUTopoInfo". Before updating APIC ID parsing rule with module level, the apicid_core_width() temporarily combines the core and module levels together. At present, we don't expose module level in CPUID.1FH because currently linux (v6.2-rc6) doesn't support module level. And exposing module and die levels at the same time in CPUID.1FH will cause linux to calculate the wrong die_id. The module level should be exposed until the real machine has the module level in CPUID.1FH. In addition, update topology structure in test-x86-apicid.c. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- hw/i386/x86.c | 3 ++- include/hw/i386/topology.h | 13 ++++++++--- target/i386/cpu.c | 17 ++++++++------ tests/unit/test-x86-apicid.c | 45 +++++++++++++++++++----------------- 4 files changed, 46 insertions(+), 32 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 66902d1c0923..3f6e0dd7b827 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -70,7 +70,8 @@ inline void init_topo_info(X86CPUTopoInfo *topo_info, MachineState *ms =3D MACHINE(x86ms); =20 topo_info->dies_per_pkg =3D ms->smp.dies; - topo_info->cores_per_die =3D ms->smp.cores; + topo_info->modules_per_die =3D ms->smp.clusters; + topo_info->cores_per_module =3D ms->smp.cores; topo_info->threads_per_core =3D ms->smp.threads; } =20 diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 81573f6cfde0..bbb00dc4aad8 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -54,7 +54,8 @@ typedef struct X86CPUTopoIDs { =20 typedef struct X86CPUTopoInfo { unsigned dies_per_pkg; - unsigned cores_per_die; + unsigned modules_per_die; + unsigned cores_per_module; unsigned threads_per_core; } X86CPUTopoInfo; =20 @@ -78,7 +79,12 @@ static inline unsigned apicid_smt_width(X86CPUTopoInfo *= topo_info) */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(topo_info->cores_per_die); + /* + * TODO: Will separate module info from core_width when update + * APIC ID with module level. + */ + return apicid_bitwidth_for_count(topo_info->cores_per_module * + topo_info->modules_per_die); } =20 /* Bit width of the Die_ID field */ @@ -128,7 +134,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo= *topo_info, X86CPUTopoIDs *topo_ids) { unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_cores =3D topo_info->cores_per_module * + topo_info->modules_per_die; unsigned nr_threads =3D topo_info->threads_per_core; =20 topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 61ec9a7499b8..6f3d114c7d12 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -336,7 +336,9 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->cores_per_die * topo_info->threads_per_c= ore; + l3_threads =3D topo_info->modules_per_die * + topo_info->cores_per_module * + topo_info->threads_per_core; *eax |=3D (l3_threads - 1) << 14; } else { *eax |=3D ((topo_info->threads_per_core - 1) << 14); @@ -5218,11 +5220,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, uint32_t cpus_per_pkg; =20 topo_info.dies_per_pkg =3D env->nr_dies; - topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; + topo_info.modules_per_die =3D env->nr_modules; + topo_info.cores_per_module =3D cs->nr_cores / env->nr_dies / env->nr_m= odules; topo_info.threads_per_core =3D cs->nr_threads; =20 - cpus_per_pkg =3D topo_info.dies_per_pkg * topo_info.cores_per_die * - topo_info.threads_per_core; + cpus_per_pkg =3D topo_info.dies_per_pkg * topo_info.modules_per_die * + topo_info.cores_per_module * topo_info.threads_per_core; =20 /* Calculate & apply limits for different index ranges */ if (index >=3D 0xC0000000) { @@ -5298,8 +5301,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, if (*eax & 31) { int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); int vcpus_per_socket =3D cpus_per_pkg; - int cores_per_socket =3D topo_info.cores_per_die * - topo_info.dies_per_pkg; + int cores_per_socket =3D cpus_per_pkg / + topo_info.threads_per_core; if (cores_per_socket > 1) { *eax &=3D ~0xFC000000; *eax |=3D (pow2ceil(cores_per_socket) - 1) << 26; @@ -5483,7 +5486,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 1: *eax =3D apicid_die_offset(&topo_info); - *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; + *ebx =3D cpus_per_pkg / topo_info.dies_per_pkg; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: diff --git a/tests/unit/test-x86-apicid.c b/tests/unit/test-x86-apicid.c index 2b104f86d7c2..f21b8a5d95c2 100644 --- a/tests/unit/test-x86-apicid.c +++ b/tests/unit/test-x86-apicid.c @@ -30,13 +30,16 @@ static void test_topo_bits(void) { X86CPUTopoInfo topo_info =3D {0}; =20 - /* simple tests for 1 thread per core, 1 core per die, 1 die per packa= ge */ - topo_info =3D (X86CPUTopoInfo) {1, 1, 1}; + /* + * simple tests for 1 thread per core, 1 core per module, + * 1 module per die, 1 die per package + */ + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 1}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); @@ -45,39 +48,39 @@ static void test_topo_bits(void) =20 /* Test field width calculation for multiple values */ - topo_info =3D (X86CPUTopoInfo) {1, 1, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 2}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {1, 1, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {1, 1, 4}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 4}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 14}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 14}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 15}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 15}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 16}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 16}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 17}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 17}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 5); =20 =20 - topo_info =3D (X86CPUTopoInfo) {1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 31, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 31, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 32, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 32, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 33, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 33, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 6); =20 - topo_info =3D (X86CPUTopoInfo) {1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); - topo_info =3D (X86CPUTopoInfo) {2, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {2, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {3, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {3, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {4, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {4, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly @@ -85,18 +88,18 @@ static void test_topo_bits(void) =20 /* This will use 2 bits for thread ID and 3 bits for core ID */ - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_core_offset(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_die_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_pkg_offset(&topo_info), =3D=3D, 5); =20 - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); =20 - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 0), =3D= =3D, (1 << 2) | 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 1), =3D= =3D, --=20 2.34.1 From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331169; cv=none; d=zohomail.com; s=zohoarc; b=Bf6zaVcNCieix1JcqlZZwtXoGI3CnGefBpgkTxqVAYwODk64RPfEsI1jdva5Z5VuO8eLsxo6qQ0nZWvd1qfB3osNUZGYce0xnwjxavddxGW1tCpsPmrLEmnR/72OVaRXSs24QyhMTTvwpIk6oY48hR1FSpR2ZA4brtFdDSe+Nhs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331169; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402011" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402011" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909447" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909447" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Zhuocheng Ding Subject: [PATCH 08/18] i386: Support module_id in X86CPUTopoIDs Date: Thu, 2 Feb 2023 17:49:19 +0800 Message-Id: <20230202094929.343799-9-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331171536100007 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding Add module_id member in X86CPUTopoIDs. module_id can be parsed from APIC ID, so before updating the parsing rule of APIC ID, temporarily set the module_id generated in this way to 0. module_id can be also generated from cpu topology, and before i386 supports "clusters" in smp, the default "clusters per die" is only 1, thus the module_id generated in this way is 0, so that it will not conflict with the module_id generated by APIC ID. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- hw/i386/x86.c | 17 +++++++++++++++++ include/hw/i386/topology.h | 24 ++++++++++++++++++++---- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 3f6e0dd7b827..b66719230d57 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -361,6 +361,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.die_id =3D cpu->die_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; + + /* + * TODO: This is the temporary initialization for topo_ids.module_= id to + * avoid "maybe-uninitialized" compilation errors. Will remove when + * X86CPU supports cluster_id. + */ + topo_ids.module_id =3D 0; + cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); } =20 @@ -369,6 +377,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, MachineState *ms =3D MACHINE(x86ms); =20 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + + /* + * TODO: Before APIC ID supports module level parsing, there's no = need + * to expose module_id info. + */ error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -494,6 +507,10 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(Machine= State *ms) ms->possible_cpus->cpus[i].props.has_die_id =3D true; ms->possible_cpus->cpus[i].props.die_id =3D topo_ids.die_id; } + if (ms->smp.clusters > 1) { + ms->possible_cpus->cpus[i].props.has_cluster_id =3D true; + ms->possible_cpus->cpus[i].props.cluster_id =3D topo_ids.modul= e_id; + } ms->possible_cpus->cpus[i].props.has_core_id =3D true; ms->possible_cpus->cpus[i].props.core_id =3D topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id =3D true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index bbb00dc4aad8..b0174c18b7bd 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -48,6 +48,7 @@ typedef uint32_t apic_id_t; typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; + unsigned module_id; unsigned core_id; unsigned smt_id; } X86CPUTopoIDs; @@ -134,12 +135,21 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoIn= fo *topo_info, X86CPUTopoIDs *topo_ids) { unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_module * - topo_info->modules_per_die; + unsigned nr_modules =3D topo_info->modules_per_die; + unsigned nr_cores =3D topo_info->cores_per_module; unsigned nr_threads =3D topo_info->threads_per_core; =20 - topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); - topo_ids->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + /* + * Currently smp for i386 doesn't support "clusters", modules_per_die = is + * only 1. Therefore, the module_id generated from the module topology= will + * not conflict with the module_id generated according to the apicid. + */ + topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_modules * + nr_cores * nr_threads); + topo_ids->die_id =3D cpu_index / (nr_modules * nr_cores * + nr_threads) % nr_dies; + topo_ids->module_id =3D cpu_index / (nr_cores * nr_threads) % + nr_modules; topo_ids->core_id =3D cpu_index / nr_threads % nr_cores; topo_ids->smt_id =3D cpu_index % nr_threads; } @@ -156,6 +166,12 @@ static inline void x86_topo_ids_from_apicid(apic_id_t = apicid, topo_ids->core_id =3D (apicid >> apicid_core_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); + /* + * TODO: This is the temporary initialization for topo_ids.module_id to + * avoid "maybe-uninitialized" compilation errors. Will remove when AP= IC + * ID supports module level parsing. + */ + topo_ids->module_id =3D 0; topo_ids->die_id =3D (apicid >> apicid_die_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); --=20 2.34.1 From nobody Sat Apr 20 04:11:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331219; cv=none; d=zohomail.com; s=zohoarc; b=kjt90mxB84BLWaH+SK6SIUZEmhMLtZ1+B6LL983t2Y0OATpy9NXvGhYRn9E3Ob6cnejVczpP40LYeHb3EhNRz/SevRHPsIZPYcvcKSPu/T9u7Fx/d/KvbtbN6wYhTn2DdFyW7ClGzSrlRydS1jqxF9zskyTumBIbeqMzqaLngg0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331219; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1HOHVBZvDdsy2DDxzbNKp2fJ7WVHZCErIYgP1DWDCVM=; b=MGj9HNFFyrYuSnhL0UwONWiQi+ZSnJN+y7AP998vl5BSa5j6ZXaEVftwU79TmvauytkTw6HPCsRLEC3dwD5MTVXV4hbtcU8Wp5pXRM3gqmfeDFLL6yWt83nUcoK21zxY7dIBc4VGZXQjBZYACQQ2FmyEhf3Wxi8XYd5ZbJI2i8A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167533121900297.99018337080167; Thu, 2 Feb 2023 01:46:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW7z-0006Wp-4s; Thu, 02 Feb 2023 04:43:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW7x-0006Vj-45 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:33 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW7v-0006Pg-A1 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:32 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:22 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:42:19 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331011; x=1706867011; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xtknp8xKM3EUafI+IMYCkYLlc/7I5Ma96WMYzPwnDyU=; b=asaouKW5bptK8H77GA7e8GLksntzHr4HxF52yvnZJRO5+JlWoKCCwb6m 1CrRFEpRzepeqENeFx0Z32FBLcN+pVUPhDPyryp+UsOMsTni763dfTb+L RkFt8vNZGq0oh6ue/9h8e4TDYXGke12Tbh25yNmSqhbiBlez5mYPIYp40 6V87fqsLCsGC3Dpb54bDmfGcKGe6RIMm3T83AxM+iF4eLpdLmFdkXqkFl pj6N2ugkC3zNdxRllJphN222NeMzg6mLUqrUm8ZzWMDW4gROf+oafQ2AF B9T0aPas6QjEaUUvJF3bwR6/7lmeA3QPt0pPUOV6AYjTCx0FXJxl39O4w A==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402027" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402027" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909451" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909451" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH 09/18] i386: Fix comment style in topology.h Date: Thu, 2 Feb 2023 17:49:20 +0800 Message-Id: <20230202094929.343799-10-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331219815100001 From: Zhao Liu For function comments in this file, keep the comment style consistent with other places. Signed-off-by: Zhao Liu --- include/hw/i386/topology.h | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index b0174c18b7bd..5de905dc00d3 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -24,7 +24,8 @@ #ifndef HW_I386_TOPOLOGY_H #define HW_I386_TOPOLOGY_H =20 -/* This file implements the APIC-ID-based CPU topology enumeration logic, +/* + * This file implements the APIC-ID-based CPU topology enumeration logic, * documented at the following document: * Intel=C2=AE 64 Architecture Processor Topology Enumeration * http://software.intel.com/en-us/articles/intel-64-architecture-proces= sor-topology-enumeration/ @@ -41,7 +42,8 @@ =20 #include "qemu/bitops.h" =20 -/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC suppo= rt +/* + * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC suppo= rt */ typedef uint32_t apic_id_t; =20 @@ -60,8 +62,7 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; =20 -/* Return the bit width needed for 'count' IDs - */ +/* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) { g_assert(count >=3D 1); @@ -69,15 +70,13 @@ static unsigned apicid_bitwidth_for_count(unsigned coun= t) return count ? 32 - clz32(count) : 0; } =20 -/* Bit width of the SMT_ID (thread ID) field on the APIC ID - */ +/* Bit width of the SMT_ID (thread ID) field on the APIC ID */ static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) { return apicid_bitwidth_for_count(topo_info->threads_per_core); } =20 -/* Bit width of the Core_ID field - */ +/* Bit width of the Core_ID field */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { /* @@ -94,8 +93,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *t= opo_info) return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } =20 -/* Bit offset of the Core_ID field - */ +/* Bit offset of the Core_ID field */ static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) { return apicid_smt_width(topo_info); @@ -107,14 +105,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoIn= fo *topo_info) return apicid_core_offset(topo_info) + apicid_core_width(topo_info); } =20 -/* Bit offset of the Pkg_ID (socket ID) field - */ +/* Bit offset of the Pkg_ID (socket ID) field */ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) { return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } =20 -/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID +/* + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ @@ -127,7 +125,8 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPU= TopoInfo *topo_info, topo_ids->smt_id; } =20 -/* Calculate thread/core/package IDs for a specific topology, +/* + * Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, @@ -154,7 +153,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo= *topo_info, topo_ids->smt_id =3D cpu_index % nr_threads; } =20 -/* Calculate thread/core/package IDs for a specific topology, +/* + * Calculate thread/core/package IDs for a specific topology, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, @@ -178,7 +178,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t a= picid, topo_ids->pkg_id =3D apicid >> apicid_pkg_offset(topo_info); } =20 -/* Make APIC ID for the CPU 'cpu_index' +/* + * Make APIC ID for the CPU 'cpu_index' * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331170; cv=none; d=zohomail.com; s=zohoarc; b=C0ZYjvgGhE5qkgsth4pFtVPPqWYtsuKR5QwpEzHwgo4TBUwx0kQxLz8tEnjab0Cu9otGxWRAxyZP5DGLqyFjflCqVHZuUIjTSOSFQVE7hBxsCi/xhZNutjSZuVHdDFXqTXWVqCNxOriQefPRKbTEf6Eh9b7ZSwmqjVsYUV13DOA= ARC-Message-Signature: i=1; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Zhuocheng Ding Subject: [PATCH 10/18] i386: Update APIC ID parsing rule to support module level Date: Thu, 2 Feb 2023 17:49:21 +0800 Message-Id: <20230202094929.343799-11-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331171472100005 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding Add the module level parsing support for APIC ID. With this support, now the conversion between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID is completed. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- hw/i386/x86.c | 19 ++++++++----------- include/hw/i386/topology.h | 36 ++++++++++++++++++------------------ 2 files changed, 26 insertions(+), 29 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index b66719230d57..68fce87d18ac 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -310,11 +310,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 /* * If APIC ID is not set, - * set it based on socket/die/core/thread properties. + * set it based on socket/die/cluster/core/thread properties. */ if (cpu->apic_id =3D=3D UNASSIGNED_APIC_ID) { - int max_socket =3D (ms->smp.max_cpus - 1) / - smp_threads / smp_cores / ms->smp.dies; + int max_socket =3D (ms->smp.max_cpus - 1) / smp_threads / smp_core= s / + ms->smp.clusters / ms->smp.dies; =20 /* * die-id was optional in QEMU 4.0 and older, so keep it optional @@ -378,15 +378,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); =20 - /* - * TODO: Before APIC ID supports module level parsing, there's no = need - * to expose module_id info. - */ error_setg(errp, - "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" - " APIC ID %" PRIu32 ", valid index range 0:%d", - topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.s= mt_id, - cpu->apic_id, ms->possible_cpus->len - 1); + "Invalid CPU [socket: %u, die: %u, module: %u, core: %u, threa= d: %u]" + " with APIC ID %" PRIu32 ", valid index range 0:%d", + topo_ids.pkg_id, topo_ids.die_id, topo_ids.module_id, + topo_ids.core_id, topo_ids.smt_id, cpu->apic_id, + ms->possible_cpus->len - 1); return; } =20 diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 5de905dc00d3..3cec97b377f2 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -79,12 +79,13 @@ static inline unsigned apicid_smt_width(X86CPUTopoInfo = *topo_info) /* Bit width of the Core_ID field */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { - /* - * TODO: Will separate module info from core_width when update - * APIC ID with module level. - */ - return apicid_bitwidth_for_count(topo_info->cores_per_module * - topo_info->modules_per_die); + return apicid_bitwidth_for_count(topo_info->cores_per_module); +} + +/* Bit width of the Module_ID (cluster ID) field */ +static inline unsigned apicid_module_width(X86CPUTopoInfo *topo_info) +{ + return apicid_bitwidth_for_count(topo_info->modules_per_die); } =20 /* Bit width of the Die_ID field */ @@ -99,10 +100,16 @@ static inline unsigned apicid_core_offset(X86CPUTopoIn= fo *topo_info) return apicid_smt_width(topo_info); } =20 +/* Bit offset of the Module_ID (cluster ID) field */ +static inline unsigned apicid_module_offset(X86CPUTopoInfo *topo_info) +{ + return apicid_core_offset(topo_info) + apicid_core_width(topo_info); +} + /* Bit offset of the Die_ID field */ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) { - return apicid_core_offset(topo_info) + apicid_core_width(topo_info); + return apicid_module_offset(topo_info) + apicid_module_width(topo_info= ); } =20 /* Bit offset of the Pkg_ID (socket ID) field */ @@ -121,6 +128,7 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPU= TopoInfo *topo_info, { return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->module_id << apicid_module_offset(topo_info)) | (topo_ids->core_id << apicid_core_offset(topo_info)) | topo_ids->smt_id; } @@ -138,11 +146,6 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInf= o *topo_info, unsigned nr_cores =3D topo_info->cores_per_module; unsigned nr_threads =3D topo_info->threads_per_core; =20 - /* - * Currently smp for i386 doesn't support "clusters", modules_per_die = is - * only 1. Therefore, the module_id generated from the module topology= will - * not conflict with the module_id generated according to the apicid. - */ topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_modules * nr_cores * nr_threads); topo_ids->die_id =3D cpu_index / (nr_modules * nr_cores * @@ -166,12 +169,9 @@ static inline void x86_topo_ids_from_apicid(apic_id_t = apicid, topo_ids->core_id =3D (apicid >> apicid_core_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); - /* - * TODO: This is the temporary initialization for topo_ids.module_id to - * avoid "maybe-uninitialized" compilation errors. Will remove when AP= IC - * ID supports module level parsing. - */ - topo_ids->module_id =3D 0; + topo_ids->module_id =3D + (apicid >> apicid_module_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_module_width(topo_info)); topo_ids->die_id =3D (apicid >> apicid_die_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331075; cv=none; d=zohomail.com; s=zohoarc; b=XKT+0LSeeMh0oDRHRJlQf0VLIHLCsx5tUfBVuEtoescWJSuPjzRWY4tiOrczL6V7UMu7D8BcSMcS6U2JKw5i5+5G9b+OU6+NSh3tEQt1/XkCqwIxuM7rhqrQ2SZ9Id0i+r4PfEVZQg/j9wlRD44yPYBhAFrFJ6AI7mNM7fMPWf8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331075; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PHqfPISlnh/RrBH494jnu461hVNvG3YdDtWZgdx1tuI=; b=GIseAf25FsUQzl3+Zb+fq9wEk84mxM2uY1cqGL4QHDu6ZOsrs4Q0skBvbMTEsxPnDQnR3LzysASHteNef98+usXriwq9Gqirk8lZofS4bQbYbnWdU/G80FJg2oHFyYwMYG/mupEXBGQrmJVLDQM6BRQPg4vZZLCuXFwMso/9ewk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675331075683991.8692578267076; Thu, 2 Feb 2023 01:44:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW8B-0006h7-1F; Thu, 02 Feb 2023 04:43:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW89-0006dT-Fj for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:45 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW87-0006ND-Ih for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:45 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:28 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:42:25 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331023; x=1706867023; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rBNds6uv3sDXqzaX4V/6r/CriEemKNlySKQ+UPO3qKA=; b=A+nJiSvUiDkPev9bVphSTYnCbhMG1HqYDUHDxEBl57Bhxdn7Df0n+D9Y t3L0F5DGH6TcIbZAJRHAH0ykJJgpH89adnOKcmi5yX3zmzXxOj4SIIb7A LGMc2kNcJlUCnHW4CNqyTKoWIaVke4ydZ7ZniFhtgd+MhS4w4K3OrjNT7 OXq07fn2Tluhmh+QX4Zk+m7PcyW8y7SqFpsmeuzyaGQ5UiPlTa3RV7VfE +3daWQHjt3+cwFNimSMgZFOauyNFh896HTBqBhXcwt05E7GUfjrHVJG9F faqzwnA7VXxuEGwMPpEc4rtDPlms1W7BtUk2ZW91kQ7kLR+7ZtJ26rLT8 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402071" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402071" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909463" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909463" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Zhuocheng Ding Subject: [PATCH 11/18] i386/cpu: Introduce cluster-id to X86CPU Date: Thu, 2 Feb 2023 17:49:22 +0800 Message-Id: <20230202094929.343799-12-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331076309100001 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding We introduce cluster-id other than module-id to be consistent with CpuInstanceProperties.cluster-id, and this avoids the confusion of parameter names when hotplugging. Following the legacy smp check rules, also add the cluster_id validity into x86_cpu_pre_plug(). Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- hw/i386/x86.c | 33 +++++++++++++++++++++++++-------- target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 68fce87d18ac..57d646bf360f 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -324,6 +324,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, cpu->die_id =3D 0; } =20 + /* + * cluster-id was optional in QEMU 8.0 and older, so keep it optio= nal + * if there's only one cluster per die. + */ + if (cpu->cluster_id < 0 && ms->smp.clusters =3D=3D 1) { + cpu->cluster_id =3D 0; + } + if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); return; @@ -340,6 +348,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, cpu->die_id, ms->smp.dies - 1); return; } + if (cpu->cluster_id < 0) { + error_setg(errp, "CPU cluster-id is not set"); + return; + } else if (cpu->cluster_id > ms->smp.clusters - 1) { + error_setg(errp, "Invalid CPU cluster-id: %u must be in range = 0:%u", + cpu->cluster_id, ms->smp.clusters - 1); + return; + } if (cpu->core_id < 0) { error_setg(errp, "CPU core-id is not set"); return; @@ -359,16 +375,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 topo_ids.pkg_id =3D cpu->socket_id; topo_ids.die_id =3D cpu->die_id; + topo_ids.module_id =3D cpu->cluster_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; - - /* - * TODO: This is the temporary initialization for topo_ids.module_= id to - * avoid "maybe-uninitialized" compilation errors. Will remove when - * X86CPU supports cluster_id. - */ - topo_ids.module_id =3D 0; - cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); } =20 @@ -415,6 +424,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, } cpu->die_id =3D topo_ids.die_id; =20 + if (cpu->cluster_id !=3D -1 && cpu->cluster_id !=3D topo_ids.module_id= ) { + error_setg(errp, "property cluster-id: %u doesn't match set apic-i= d:" + " 0x%x (cluster-id: %u)", cpu->cluster_id, cpu->apic_id, + topo_ids.module_id); + return; + } + cpu->cluster_id =3D topo_ids.module_id; + if (cpu->core_id !=3D -1 && cpu->core_id !=3D topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6f3d114c7d12..27bbbc36b11c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6980,12 +6980,14 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), + DEFINE_PROP_INT32("cluster-id", X86CPU, cluster_id, 0), DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), + DEFINE_PROP_INT32("cluster-id", X86CPU, cluster_id, -1), DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f3afea765982..8668e74e0c87 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1966,6 +1966,7 @@ struct ArchCPU { int32_t node_id; /* NUMA node this CPU belongs to */ int32_t socket_id; int32_t die_id; + int32_t cluster_id; int32_t core_id; int32_t thread_id; =20 --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331077; cv=none; d=zohomail.com; s=zohoarc; b=WIZOB6t0QSmByI76u4aPdeqErKbKVobMvTtalOdNp68JCjokAlByjVq10SVAELd9S9vtS7hDRruabdXNf/1gdi9XbJ1laoxS3OSZF52JoXB2njN3UWk99FKkWoSF2rVEIFKFaQy++LYkvvZkpOixnu1cFenY9rVxoaXOfHyCaSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331077; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Zhuocheng Ding Subject: [PATCH 12/18] tests: Add test case of APIC ID for module level parsing Date: Thu, 2 Feb 2023 17:49:23 +0800 Message-Id: <20230202094929.343799-13-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331078418100005 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding After i386 supports module level, it's time to add the test for module level's parsing. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- tests/unit/test-x86-apicid.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/tests/unit/test-x86-apicid.c b/tests/unit/test-x86-apicid.c index f21b8a5d95c2..55b731ccae55 100644 --- a/tests/unit/test-x86-apicid.c +++ b/tests/unit/test-x86-apicid.c @@ -37,6 +37,7 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 0); + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); =20 topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; @@ -74,13 +75,22 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 33, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 6); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 6, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 7, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 8, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 9, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 4); + + topo_info =3D (X86CPUTopoInfo) {1, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); - topo_info =3D (X86CPUTopoInfo) {2, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {2, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {3, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {3, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {4, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {4, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly @@ -91,6 +101,7 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_core_offset(&topo_info), =3D=3D, 2); + g_assert_cmpuint(apicid_module_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_die_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_pkg_offset(&topo_info), =3D=3D, 5); =20 --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331195; cv=none; d=zohomail.com; s=zohoarc; b=iGA8eryWPAwW2x4YOZGis7WEje8cRSACpTesGpb57VkOVUpGkogpmW74rDAk9pM3cwRRXupmCaPgyDJucCw5Pw6BBOx7downjYceOLDg3sssu3BQTLYwTDfSOp5MzF2VnGDJIAlRdVnrPZlUUm344bdlIFlI0gQIILznQffLkz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu , Zhuocheng Ding Subject: [PATCH 13/18] hw/i386/pc: Support smp.clusters for x86 PC machine Date: Thu, 2 Feb 2023 17:49:24 +0800 Message-Id: <20230202094929.343799-14-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331195732100001 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding As module-level topology support is added to X86CPU, now we can enable the support for the cluster parameter on PC machines. With this support, we can define a 5-level x86 CPU topology with "-smp": -smp cpus=3D*,maxcpus=3D*,sockets=3D*,dies=3D*,clusters=3D*,cores=3D*,threa= ds=3D*. Additionally, add the 5-level topology example in description of "-smp". Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu --- hw/i386/pc.c | 1 + qemu-options.hx | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 6e592bd969aa..c329df56ebd2 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1929,6 +1929,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) mc->default_cpu_type =3D TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; + mc->smp_props.clusters_supported =3D true; mc->default_ram_id =3D "pc.ram"; =20 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", diff --git a/qemu-options.hx b/qemu-options.hx index d59d19704bc5..3700e1aa97ea 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -312,14 +312,14 @@ SRST -smp 8,sockets=3D2,cores=3D2,threads=3D2,maxcpus=3D8 =20 The following sub-option defines a CPU topology hierarchy (2 sockets - totally on the machine, 2 dies per socket, 2 cores per die, 2 threads - per core) for PC machines which support sockets/dies/cores/threads. - Some members of the option can be omitted but their values will be - automatically computed: + totally on the machine, 2 dies per socket, 2 clusters per die, 2 cores= per + cluster, 2 threads per core) for PC machines which support sockets/dies + /clusters/cores/threads. Some members of the option can be omitted but + their values will be automatically computed: =20 :: =20 - -smp 16,sockets=3D2,dies=3D2,cores=3D2,threads=3D2,maxcpus=3D16 + -smp 32,sockets=3D2,dies=3D2,clusters=3D2,cores=3D2,threads=3D2,ma= xcpus=3D32 =20 The following sub-option defines a CPU topology hierarchy (2 sockets totally on the machine, 2 clusters per socket, 2 cores per cluster, --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331198; cv=none; d=zohomail.com; s=zohoarc; b=koL1R9nYtOF1BtzbX3NPOWd8kqADrpeqbjQVDdiTm5DgwPl+v4plx0IBcwSSG16L041W7KIBVi9I4DKowCKOuSqTziack+AdhuhNiX1IkfRYEUKFqq+lDPUCsx/nRQhC11eoYaXbkkWhuFGH4xPJd9CtdzNnt0UbqtE56Llsblc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331198; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+hM7lV2N72q+7+08kCmy1C15iHAYX8DvBpOmXJbA1O0=; b=AQodvp6slWqzb9zKawNZpm78xO3AEbITWPJZRN8v9yMv0KE/SIN4EvNHavz2FvleOQzS8FKIVJM/Ylae0Y+cn/Zdj0XZOCObbC7rQHVZjqIvvDobCHiPoC2VLr63mhgl11bpuA+KDyNGh8c0+iqqoaMJxicBzywTd8hnMs17wm8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675331198952544.9907228356249; Thu, 2 Feb 2023 01:46:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW8O-0006uj-L2; Thu, 02 Feb 2023 04:44:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8M-0006pG-52 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:58 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8K-0006ND-9B for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:57 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:36 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:42:33 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331036; x=1706867036; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IjmG50bvCSw8vgMEYd9oBawb6EIkhL+/mLrbVfxWlqs=; b=oJIAl0m6OA2Vf4ZcMBnVvRW+9pfdVl0X1OBT8MeCcNQHUsOtPuOpGKoe eQduFktAMuIGmSHKrSZWdNB4KAGB/Tsu714G14zKZ0W2K4Um5RqcbHQ7g p9qWOBQZ0CF5TogPmX8SYsYPMCd6gxjPkN+M6cnEkX73q7aX1J0VMxlAX ss9lQyCh81n5yXTi2GZKXy6PuM+5qfv44WxDh8Rfw8sMAvu96M7WOkJ0D d3hS+KR2ugIAmwrfCbhHRBwp48d93Y+bl3eEW4lRzBp3cCa2EgtLKqF7e duYIPg8XdjeRp2hCS21iIF2RLxT3MFZxgl7SBn3BxyBmv2uC+hsQtZ6wV w==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402124" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402124" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909478" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909478" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH 14/18] i386: Add cache topology info in CPUCacheInfo Date: Thu, 2 Feb 2023 17:49:25 +0800 Message-Id: <20230202094929.343799-15-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331199681100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Currently, by default, the cache topology is encoded as: 1. i/d cache is shared in one core. 2. L2 cache is shared in one core. 3. L3 cache is shared in one die. This default general setting has caused a misunderstanding, that is, the cache topology is completely equated with a specific cpu topology, such as the connection between L2 cache and core level, and the connection between L3 cache and die level. In fact, the settings of these topologies depend on the specific platform and are not static. For example, on Alder Lake-P, every four Atom cores share the same L2 cache. Thus, we should explicitly define the corresponding cache topology for different cache models to increase scalability. Except legacy_l2_cache_cpuid2 (its default topo level is INVALID), explicitly set the corresponding topology level for all other cache models. In order to be compatible with the existing cache topology, set the CORE level for the i/d cache, set the CORE level for L2 cache, and set the DIE level for L3 cache. The field for CPUID[4].EAX[bits 25:14] or CPUID[0x8000001D].EAX[bits 25:14] will be set based on CPUCacheInfo.share_level. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 19 +++++++++++++++++++ target/i386/cpu.h | 16 ++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 27bbbc36b11c..364534e84b1b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -433,6 +433,7 @@ static CPUCacheInfo legacy_l1d_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -447,6 +448,7 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }; =20 /* L1 instruction cache: */ @@ -460,6 +462,7 @@ static CPUCacheInfo legacy_l1i_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -474,6 +477,7 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }; =20 /* Level 2 unified cache: */ @@ -487,6 +491,7 @@ static CPUCacheInfo legacy_l2_cache =3D { .sets =3D 4096, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }; =20 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -509,6 +514,7 @@ static CPUCacheInfo legacy_l2_cache_amd =3D { .associativity =3D 16, .sets =3D 512, .partitions =3D 1, + .share_level =3D CORE, }; =20 /* Level 3 unified cache: */ @@ -524,6 +530,7 @@ static CPUCacheInfo legacy_l3_cache =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D DIE, }; =20 /* TLB definitions: */ @@ -1668,6 +1675,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -1680,6 +1688,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1690,6 +1699,7 @@ static const CPUCaches epyc_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1703,6 +1713,7 @@ static const CPUCaches epyc_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D DIE, }, }; =20 @@ -1718,6 +1729,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -1730,6 +1742,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1740,6 +1753,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1753,6 +1767,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D DIE, }, }; =20 @@ -1768,6 +1783,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -1780,6 +1796,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1790,6 +1807,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1803,6 +1821,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D DIE, }, }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8668e74e0c87..5a955431f759 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1476,6 +1476,15 @@ enum CacheType { UNIFIED_CACHE }; =20 +enum CPUTopoLevel { + INVALID =3D 0, + SMT, + CORE, + MODULE, + DIE, + PACKAGE, +}; + typedef struct CPUCacheInfo { enum CacheType type; uint8_t level; @@ -1517,6 +1526,13 @@ typedef struct CPUCacheInfo { * address bits. CPUID[4].EDX[bit 2]. */ bool complex_indexing; + + /* + * Cache Topology. The level that cache is shared in. + * Used to encode CPUID[4].EAX[bits 25:14] or + * CPUID[0x8000001D].EAX[bits 25:14]. + */ + enum CPUTopoLevel share_level; } CPUCacheInfo; =20 =20 --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331114; cv=none; d=zohomail.com; s=zohoarc; b=X8YhUawkU4Angp+melxxi2v73bO5bP0c1bEh19vDwwl7KIXECDtLsyO1+5piqRaJlKTpdCd46gXyP6X+6zf219lqLlww7GJygE1bUswqizwK2C8tMyW7usE/WWF8iqz97UvE0sziA7EDNdflPXYk/997f02zQItxmEe4Xn7mDOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331114; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vgm/Dq3ZPQUPRkKHeR3odmAmYxRNnhKXbHnKrFtc1eg=; b=Q2rwYmz0DBWbZidS4yD7+Cv5rBa4VYvs8dx3ooyvRApwPuTsREYJ4ImfUqxuE8hI0opCa/0uWC2X5v34BZZ8irZhzzR5M97+LOyyL1Xq2uN4CRNYq/Uy6PPSVdbis+MzrPNDzhQqReyDaSe2/VDB3NFYFWatunU5DrXa0kbGjqw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675331114762659.575839642439; Thu, 2 Feb 2023 01:45:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW8N-0006tR-Qg; Thu, 02 Feb 2023 04:43:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8L-0006oP-Vr for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:58 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8K-0006Pg-9B for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:43:57 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:38 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:42:36 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331036; x=1706867036; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wy/HB9PCBo5jKGh1Soirwp+UxznN/hgvoS723fwEbJU=; b=mXEve/jgnUrWFxbAcpXOKhxEmMIewXvou2uVJH76dujlv6NEO0yY09OW 76D5kvCjkx2ucU4mysR45dy8lYTqE6uMjb+pNGjZ2Md8D3kc17KxKFz8/ DpTe3igxE7YvFFM0EzHYwnk3FRR5kqJruzR9vD3MfdRAGBUogXD3rGrZw gfLKccpo6WcZnLJrtyLGXDdnJOe/9MN6Ry4Wtmfz1F6/awguTVTU/v54u xPr5UcimwWduhQpnGuf9ZbAPAgZr8bz+m6TecL3i7jGxlaeIRq38MmZZm UwzkrSgZVPsMLuNgN5xBj+qeH/GN1qmqTjHN2CXaWt0B0Wpet8jcCHfBc g==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402146" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402146" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909486" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909486" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH 15/18] i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14] Date: Thu, 2 Feb 2023 17:49:26 +0800 Message-Id: <20230202094929.343799-16-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331116557100003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[4].EAX[bits 25:14] is used to represent the cache topology for intel CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[4].EAX[bits 25:14]. Additionally, since maximum_processor_id (original "num_apic_ids") is parsed based on cpu topology levels, which are verified when parsing smp, it's no need to check this value by "assert(num_apic_ids > 0)" again, so remove this assert. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 55 +++++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 19 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 364534e84b1b..96ef96860604 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -231,22 +231,50 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache) ((t) =3D=3D UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 0 /* Invalid value */) =20 +static uint32_t max_processor_ids_for_cache(CPUCacheInfo *cache, + X86CPUTopoInfo *topo_info) +{ + uint32_t num_ids =3D 0; + + switch (cache->share_level) { + case CORE: + num_ids =3D 1 << apicid_core_offset(topo_info); + break; + case DIE: + num_ids =3D 1 << apicid_die_offset(topo_info); + break; + default: + /* + * Currently there is no use case for SMT, MODULE and PACKAGE, so = use + * assert directly to facilitate debugging. + */ + g_assert_not_reached(); + } + + return num_ids - 1; +} + +static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) +{ + uint32_t num_cores =3D 1 << (apicid_pkg_offset(topo_info) - + apicid_core_offset(topo_info)); + return num_cores - 1; +} =20 /* Encode cache info for CPUID[4] */ static void encode_cache_cpuid4(CPUCacheInfo *cache, - int num_apic_ids, int num_cores, + X86CPUTopoInfo *topo_info, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 - assert(num_apic_ids > 0); *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | - ((num_cores - 1) << 26) | - ((num_apic_ids - 1) << 14); + (max_core_ids_in_package(topo_info) << 26) | + (max_processor_ids_for_cache(cache, topo_info) << 14); =20 assert(cache->line_size > 0); assert(cache->partitions > 0); @@ -5335,38 +5363,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; - int addressable_cores_offset =3D apicid_pkg_offset(&topo_info)= - - apicid_core_offset(&topo_info); - int core_offset, die_offset; =20 switch (count) { case 0: /* L1 dcache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; } --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331262; cv=none; d=zohomail.com; s=zohoarc; b=EdcK93YsPJkU08w0SkN11u7kcHxl8M/45FHlXGkiaF9v9UvfT2vwWPi5dljCJlyWEZ3u/saZ2UILQHbbkLCWUjbL84nZerGQGD7akRzI5ia8NRUdDrkyCS7Ogb4DeTYZuUjXsPWLvh9uqghi76vDgl/VL5hZA7AWIpAM9YuaHKk= ARC-Message-Signature: i=1; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH 16/18] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Date: Thu, 2 Feb 2023 17:49:27 +0800 Message-Id: <20230202094929.343799-17-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331264043100007 Content-Type: text/plain; charset="utf-8" From: Zhao Liu From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) means [1]: The number of logical processors sharing this cache is the value of this field incremented by 1. To determine which logical processors are sharing a cache, determine a Share Id for each processor as follows: ShareId =3D LocalApicId >> log2(NumSharingCache+1) Logical processors with the same ShareId then share a cache. If NumSharingCache+1 is not a power of two, round it up to the next power of two. From the description above, the caculation of this feild should be same as CPUID[4].EAX[bits 25:14] for intel cpus. So also use the offsets of APIC ID to caculate this field. Note: I don't have the hardware available, hope someone can help me to confirm whether this calculation is correct, thanks! [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology Information Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 96ef96860604..d691c02e3c06 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -355,7 +355,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t l3_threads; + uint32_t sharing_apic_ids; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -364,13 +364,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->modules_per_die * - topo_info->cores_per_module * - topo_info->threads_per_core; - *eax |=3D (l3_threads - 1) << 14; + sharing_apic_ids =3D 1 << apicid_die_offset(topo_info); } else { - *eax |=3D ((topo_info->threads_per_core - 1) << 14); + sharing_apic_ids =3D 1 << apicid_core_offset(topo_info); } + *eax |=3D (sharing_apic_ids - 1) << 14; =20 assert(cache->line_size > 0); assert(cache->partitions > 0); --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331084; cv=none; d=zohomail.com; s=zohoarc; b=OuIzE4KapsyV3JXFDXR1mJ5fYY9Oz+m6VeY75cpjKO3T49r4WRsvcAFO11uCQZyJ0DA5gsy09Q+S10Z9XRaXX+1H08A6r6CidFjTJW02yYC7xBm/cr/eLcUs6aRBCFmqjuBHtwk0nMrssx1ZjOBz3qe6QJBFbncD9DBfyeqXDCI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331084; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TOLME3hzJslfCIL14XNXopnjG/8NS3gErfJbrHEVjy4=; b=DMI1TP4mVoGq83ed0khJK0BbrHOXCjuG50+J2La22W7O0fqzVAm8Q4NNP4NjHJownfgbiaobN+RESepnoxBYVgmJuArZYUw++3lbr2GFg36uV5UclafXuwZle3tv2Q2RpG7IG7r6hAxj1ohYGRmsvFCSLhVOv9s7/BMQEGWSQv8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675331084850955.0132598377807; Thu, 2 Feb 2023 01:44:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW8a-0007Kc-AB; Thu, 02 Feb 2023 04:44:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8X-0007FR-Uq for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:44:09 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8W-0006Pg-BB for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:44:09 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:43 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:42:41 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331048; x=1706867048; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uLL+NWRhAQrmrOXrW9mrGp0p9bgRS48bvW90TKnZBAM=; b=jOrb500suwK4IYaPCIItGB+irpwlFpMvOCw2B3q6gVJsmJuiVa57LPw2 waNCufiUmJfjXAA+kNu2zhT46WeGLEMM8JtlAa3dgoomX9f9uk1Flg/+i ZEwMdt/66GZiNCd3iSWi+VNmRJ4gEPF1uzA4Yvuqw1Wra3y9UQOASo9zI lsca4Gvpqyq+Sev4bVzKYDeRaD5QVFLf4V9Hg+fKm+Wh+P78krfq/+RGo 27Y9bZwEY6OMZDGSld0FCEcHWoORIhwkfBUMs8M5g52uNto7lUt9st/1z cK1UnoKxjlnu/CiWTw7gB72CJc/iNoPSOwFIxLVU9gabugbBemNDaMypf w==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402169" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402169" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909500" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909500" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH 17/18] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Date: Thu, 2 Feb 2023 17:49:28 +0800 Message-Id: <20230202094929.343799-18-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331086358100003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[0x8000001D].EAX[bits 25:14] is used to represent the cache topology for amd CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[0x8000001D].EAX[bits 25:14]. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d691c02e3c06..5816dc99b1d4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -355,20 +355,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t sharing_apic_ids; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - - /* L3 is shared among multiple cores */ - if (cache->level =3D=3D 3) { - sharing_apic_ids =3D 1 << apicid_die_offset(topo_info); - } else { - sharing_apic_ids =3D 1 << apicid_core_offset(topo_info); - } - *eax |=3D (sharing_apic_ids - 1) << 14; + *eax |=3D max_processor_ids_for_cache(cache, topo_info) << 14; =20 assert(cache->line_size > 0); assert(cache->partitions > 0); --=20 2.34.1 From nobody Sat Apr 20 04:11:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675331191; cv=none; d=zohomail.com; s=zohoarc; b=MgOp0WzIf7oSEWNoVVGbAYe3cu6RzJvWyMK79HexWPHDrHsFLgv2/BmImyVoK1s7VZdzTCIe3i+BrOvGe76d9uPq+icZX4nWnYERbpNqzwX5jU+6rPgE/7YA4jAMEry5bBNbAWZwKwO3kco8HEY8ES9S+DUK1oXZB9stSuiB8jc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675331191; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=va8C7UDZxGD7g+WsXPJXdKVNDUvB048AVjM1/IxH0OY=; b=Pb25+1M595bx3VQG8b+5bJPu3XabTU6TIN2re3pgDPIY6SeWa3fRULosHlmX9FJ62vB+gQ+ZZ4pUaq5DTzd/OkkvOFJt/GSiUM0ojpI8NeaPVHNAchCGoYNx/hV6xzpngJEkVcEZiBYsgfw1Wq5Iy/6nGMALjVQdFsXbU8UycE8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675331191051506.8703516330322; Thu, 2 Feb 2023 01:46:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW8b-0007Op-7l; Thu, 02 Feb 2023 04:44:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8Y-0007Ft-7i for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:44:10 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8W-0006ND-Gc for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:44:09 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:46 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:42:43 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331048; x=1706867048; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h2l32Mxk3IIptSYvwOMjSG7Mq4ltZJOLf/uBlKfJWe8=; b=ekTLezDOi1ylxPQ0Cogp/U5t+W6fftRy2AUjupN68nKZ1aYeQt7d2khh dLxx7FgehJ4Kq89B8i4r9Va2JsAjx9sqIVTvAk0eZrHwUQaaTbJY72WKe SaxAqPkfhjucAI5gVbQRr86E2wv+jT+Dmb4gurVZU9dVSX5OLHxBaM5JW nLlzZvhuBMf47XItIHQAcOM+4S8DEUJpyNW8L79OtLD6yyXV0B/W+GnHs cXmil9HBZ7K33NWxsJ4f2ntKvNw1JB6ZWDFFxjqKrQOP//9LVVaOsqzLo dz3bXyGYT3oPCvFTjMWSm8S1SR722Br/97t3hy3fhZ4h8qzRo22I9DAAD Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402185" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402185" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909505" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909505" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH 18/18] i386: Add new property to control L2 cache topo in CPUID.04H Date: Thu, 2 Feb 2023 17:49:29 +0800 Message-Id: <20230202094929.343799-19-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1675331191520100003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu The property x-l2-cache-topo will be used to change the L2 cache topology in CPUID.04H. Now it allows user to set the L2 cache is shared in core level or cluster level. If user passes "-cpu x-l2-cache-topo=3D[core|cluster]" then older L2 cache topology will be overrided by the new topology setting. Here we expose to user "cluster" instead of "module", to be consistent with "cluster-id" naming. Since CPUID.04H is used by intel CPUs, this property is available on intel CPUs as for now. When necessary, it can be extended to CPUID.8000001DH for amd CPUs. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- target/i386/cpu.h | 2 ++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5816dc99b1d4..cf84c720a431 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -240,12 +240,15 @@ static uint32_t max_processor_ids_for_cache(CPUCacheI= nfo *cache, case CORE: num_ids =3D 1 << apicid_core_offset(topo_info); break; + case MODULE: + num_ids =3D 1 << apicid_module_offset(topo_info); + break; case DIE: num_ids =3D 1 << apicid_die_offset(topo_info); break; default: /* - * Currently there is no use case for SMT, MODULE and PACKAGE, so = use + * Currently there is no use case for SMT and PACKAGE, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -6633,6 +6636,33 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->cache_info_amd.l3_cache =3D &legacy_l3_cache; } =20 + if (cpu->l2_cache_topo_level) { + /* + * FIXME: Currently only supports changing CPUID[4] (for intel), a= nd + * will support changing CPUID[0x8000001D] when necessary. + */ + if (!IS_INTEL_CPU(env)) { + error_setg(errp, "only intel cpus supports x-l2-cache-topo"); + return; + } + + if (!strcmp(cpu->l2_cache_topo_level, "core")) { + env->cache_info_cpuid4.l2_cache->share_level =3D CORE; + } else if (!strcmp(cpu->l2_cache_topo_level, "cluster")) { + /* + * We expose to users "cluster" instead of "module", to be + * consistent with "cluster-id" naming. + */ + env->cache_info_cpuid4.l2_cache->share_level =3D MODULE; + } else { + error_setg(errp, + "x-l2-cache-topo doesn't support '%s', " + "and it only supports 'core' or 'cluster'", + cpu->l2_cache_topo_level); + return; + } + } + #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); qemu_register_reset(x86_cpu_machine_reset_cb, cpu); @@ -7135,6 +7165,7 @@ static Property x86_cpu_properties[] =3D { false), DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), + DEFINE_PROP_STRING("x-l2-cache-topo", X86CPU, l2_cache_topo_level), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5a955431f759..aa7e96c586c7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1987,6 +1987,8 @@ struct ArchCPU { int32_t thread_id; =20 int32_t hv_max_vps; + + char *l2_cache_topo_level; }; =20 =20 --=20 2.34.1