From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167534946681198.69751393155673; Thu, 2 Feb 2023 06:51:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqt-0005OB-OE; Thu, 02 Feb 2023 09:46:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvQ-00074o-Tp for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:49 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvM-0000el-Bi for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:47 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvD-004Q6t-GN; Thu, 02 Feb 2023 12:42:36 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 01/39] target/riscv: add zvkb cpu property Date: Thu, 2 Feb 2023 12:41:52 +0000 Message-Id: <20230202124230.295997-2-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349467963100003 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 12 ++++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..bd34119c75 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -100,6 +100,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), @@ -792,6 +793,17 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) return; } =20 + /* + * In principle zve*{x,d} would also suffice here, were they suppo= rted + * in qemu + */ + if (cpu->cfg.ext_zvkb && + !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v= )) { + error_setg( + errp, "Vector crypto extensions require V or Zve* extensio= ns"); + return; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || cpu->cfg.ext_zhinxmin) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..d4824ad0bb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -461,6 +461,7 @@ struct RISCVCPUConfig { bool ext_zhinxmin; bool ext_zve32f; bool ext_zve64f; + bool ext_zvkb; bool ext_zmmul; bool ext_smaia; bool ext_ssaia; --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16753521338225.154820517231315; Thu, 2 Feb 2023 07:35:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqv-0005Q4-No; Thu, 02 Feb 2023 09:46:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvR-000753-61 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:49 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvM-0000eo-15 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:47 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvD-004Q6t-P2; Thu, 02 Feb 2023 12:42:36 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter , Max Chou Subject: [PATCH 02/39] target/riscv: Add vclmul.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:41:53 +0000 Message-Id: <20230202124230.295997-3-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675352135276100001 Content-Type: text/plain; charset="utf-8" Co-authored-by: Nazar Kazakov Co-authored-by: Kiran Ostrolenk Co-authored-by: Max Chou Signed-off-by: Max Chou Signed-off-by: Kiran Ostrolenk Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 3 + target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 41 +++++++ target/riscv/meson.build | 4 +- target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 23 ++++ target/riscv/vector_helper.c | 120 +-------------------- target/riscv/vector_internals.c | 39 +++++++ target/riscv/vector_internals.h | 116 ++++++++++++++++++++ 9 files changed, 230 insertions(+), 120 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc create mode 100644 target/riscv/vcrypto_helper.c create mode 100644 target/riscv/vector_internals.c create mode 100644 target/riscv/vector_internals.h diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 227c7122ef..e9127c9ccb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1136,3 +1136,6 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, t= l) =20 DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) + +/* Vector crypto functions */ +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b7e7613ea2..5ddee69d60 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -890,3 +890,6 @@ sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2 # *** RV32 Zksed Standard Extension *** sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes + +# *** RV64 Zvkb vector crypto extension *** +vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn= _trans/trans_rvzvkb.c.inc new file mode 100644 index 0000000000..fb1995f737 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -0,0 +1,41 @@ +#define GEN_VV_MASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr * a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data =3D 0; \ + TCGLabel *over =3D gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ + gen_helper_##NAME); \ + \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool zvkb_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + s->cfg_ptr->ext_zvkb =3D=3D true; +} + +static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) +{ + return zvkb_vv_check(s, a) && s->sew =3D=3D MO_64; +} + +GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index ba25164d74..5313b01e5f 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -15,10 +15,12 @@ riscv_ss.add(files( 'gdbstub.c', 'op_helper.c', 'vector_helper.c', + 'vector_internals.c', 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', - 'crypto_helper.c' + 'crypto_helper.c', + 'vcrypto_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index df38db7553..71684c10f3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1063,6 +1063,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzawrs.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" +#include "insn_trans/trans_rvzvkb.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c new file mode 100644 index 0000000000..8a11e56754 --- /dev/null +++ b/target/riscv/vcrypto_helper.c @@ -0,0 +1,23 @@ +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "exec/memop.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-gvec-desc.h" +#include "internals.h" +#include "vector_internals.h" + +static void do_vclmul_vv(void *vd, void *vs1, void *vs2, int i) +{ + uint64_t result =3D 0; + for (int j =3D 63; j >=3D 0; j--) { + if ((((uint64_t *)vs1)[i] >> j) & 1) { + result ^=3D (((uint64_t *)vs2)[i] << j); + } + } + ((uint64_t *)vd)[i] =3D result; +} + +GEN_VEXT_VV(vclmul_vv, 8) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 00de879787..def1b21414 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -26,6 +26,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" #include "internals.h" +#include "vector_internals.h" #include =20 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, @@ -95,48 +96,6 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, #define H8(x) (x) #endif =20 -static inline uint32_t vext_nf(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, NF); -} - -static inline uint32_t vext_vm(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VM); -} - -/* - * Encode LMUL to lmul as following: - * LMUL vlmul lmul - * 1 000 0 - * 2 001 1 - * 4 010 2 - * 8 011 3 - * - 100 - - * 1/8 101 -3 - * 1/4 110 -2 - * 1/2 111 -1 - */ -static inline int32_t vext_lmul(uint32_t desc) -{ - return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); -} - -static inline uint32_t vext_vta(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA); -} - -static inline uint32_t vext_vma(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VMA); -} - -static inline uint32_t vext_vta_all_1s(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); -} - /* * Get the maximum number of elements can be operated. * @@ -155,21 +114,6 @@ static inline uint32_t vext_max_elems(uint32_t desc, u= int32_t log2_esz) return scale < 0 ? vlenb >> -scale : vlenb << scale; } =20 -/* - * Get number of total elements, including prestart, body and tail element= s. - * Note that when LMUL < 1, the tail includes the elements past VLMAX that - * are held in the same vector register. - */ -static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t d= esc, - uint32_t esz) -{ - uint32_t vlenb =3D simd_maxsz(desc); - uint32_t sew =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); - int8_t emul =3D ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : - ctzl(esz) - ctzl(sew) + vext_lmul(desc); - return (vlenb << emul) / esz; -} - static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { return (addr & env->cur_pmmask) | env->cur_pmbase; @@ -202,20 +146,6 @@ static void probe_pages(CPURISCVState *env, target_ulo= ng addr, } } =20 -/* set agnostic elements to 1s */ -static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t c= nt, - uint32_t tot) -{ - if (is_agnostic =3D=3D 0) { - /* policy undisturbed */ - return; - } - if (tot - cnt =3D=3D 0) { - return; - } - memset(base + cnt, -1, tot - cnt); -} - static inline void vext_set_elem_mask(void *v0, int index, uint8_t value) { @@ -225,18 +155,6 @@ static inline void vext_set_elem_mask(void *v0, int in= dex, ((uint64_t *)v0)[idx] =3D deposit64(old, pos, 1, value); } =20 -/* - * Earlier designs (pre-0.9) had a varying number of bits - * per mask value (MLEN). In the 0.9 design, MLEN=3D1. - * (Section 4.5) - */ -static inline int vext_elem_mask(void *v0, int index) -{ - int idx =3D index / 64; - int pos =3D index % 64; - return (((uint64_t *)v0)[idx] >> pos) & 1; -} - /* elements operations for load and store */ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, uint32_t idx, void *vd, uintptr_t retaddr); @@ -800,8 +718,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t =20 -/* operation of two vector elements */ -typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); =20 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ @@ -822,40 +738,6 @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SU= B) RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB) RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) =20 -static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivv2_fn *fn, uint32_t esz) -{ - uint32_t vm =3D vext_vm(desc); - uint32_t vl =3D env->vl; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); - uint32_t vma =3D vext_vma(desc); - uint32_t i; - - for (i =3D env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, vs1, vs2, i); - } - env->vstart =3D 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVV */ -#define GEN_VEXT_VV(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vv(vd, v0, vs1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VV(vadd_vv_b, 1) GEN_VEXT_VV(vadd_vv_h, 2) GEN_VEXT_VV(vadd_vv_w, 4) diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internal= s.c new file mode 100644 index 0000000000..a264797882 --- /dev/null +++ b/target/riscv/vector_internals.c @@ -0,0 +1,39 @@ +#include "vector_internals.h" + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot) +{ + if (is_agnostic =3D=3D 0) { + /* policy undisturbed */ + return; + } + if (tot - cnt =3D=3D 0) { + return ; + } + memset(base + cnt, -1, tot - cnt); +} + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + for (i =3D env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, vs1, vs2, i); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h new file mode 100644 index 0000000000..f61803acc0 --- /dev/null +++ b/target/riscv/vector_internals.h @@ -0,0 +1,116 @@ +/* + * RISC-V Vector Extension Internals + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef TARGET_RISCV_VECTOR_INTERNAL_H +#define TARGET_RISCV_VECTOR_INTERNAL_H + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "tcg/tcg-gvec-desc.h" +#include "internals.h" + +static inline uint32_t vext_nf(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, NF); +} + +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) +{ + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); +} + +static inline uint32_t vext_vm(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VM); +} + +static inline uint32_t vext_vma(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VMA); +} + +static inline uint32_t vext_vta(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA); +} + +static inline uint32_t vext_vta_all_1s(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); +} + +/* + * Earlier designs (pre-0.9) had a varying number of bits + * per mask value (MLEN). In the 0.9 design, MLEN=3D1. + * (Section 4.5) + */ +static inline int vext_elem_mask(void *v0, int index) +{ + int idx =3D index / 64; + int pos =3D index % 64; + return (((uint64_t *)v0)[idx] >> pos) & 1; +} + +/* + * Get number of total elements, including prestart, body and tail element= s. + * Note that when LMUL < 1, the tail includes the elements past VLMAX that + * are held in the same vector register. + */ +static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t d= esc, + uint32_t esz) +{ + uint32_t vlenb =3D simd_maxsz(desc); + uint32_t sew =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); + int8_t emul =3D ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : + ctzl(esz) - ctzl(sew) + vext_lmul(desc); + return (vlenb << emul) / esz; +} + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot); + +/* operation of two vector elements */ +typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz); + +/* generate the helpers for OPIVV */ +#define GEN_VEXT_VV(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vv(vd, v0, vs1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + +#endif /* TARGET_RISCV_VECTOR_INTERNAL_H */ --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675351268741182.616728658341; Thu, 2 Feb 2023 07:21:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqy-0005Rt-3c; Thu, 02 Feb 2023 09:46:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvR-000754-DW for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:49 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvM-0000en-Ev for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:49 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvE-004Q6t-1a; Thu, 02 Feb 2023 12:42:36 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 03/39] target/riscv: Add vclmul.vx decoding, translation and execution support Date: Thu, 2 Feb 2023 12:41:54 +0000 Message-Id: <20230202124230.295997-4-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675351270110100007 Content-Type: text/plain; charset="utf-8" Co-authored-by: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 54 ++++++++++++++++++++++ target/riscv/vcrypto_helper.c | 12 +++++ target/riscv/vector_helper.c | 36 --------------- target/riscv/vector_internals.c | 24 ++++++++++ target/riscv/vector_internals.h | 16 +++++++ 7 files changed, 108 insertions(+), 36 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e9127c9ccb..6c786ef6f3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1139,3 +1139,4 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl,= tl, tl) =20 /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5ddee69d60..4a7421354d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -893,3 +893,4 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_a= es =20 # *** RV64 Zvkb vector crypto extension *** vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm +vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn= _trans/trans_rvzvkb.c.inc index fb1995f737..6e8b81136c 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -39,3 +39,57 @@ static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) } =20 GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) + +#define GEN_VX_MASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + TCGv_ptr rd_v, v0_v, rs2_v; \ + TCGv rs1; \ + TCGv_i32 desc; \ + uint32_t data =3D 0; \ + \ + TCGLabel *over =3D gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + \ + rd_v =3D tcg_temp_new_ptr(); \ + v0_v =3D tcg_temp_new_ptr(); \ + rs1 =3D get_gpr(s, a->rs1, EXT_ZERO); \ + rs2_v =3D tcg_temp_new_ptr(); \ + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data)); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ + tcg_gen_addi_ptr(v0_v, cpu_env, vreg_ofs(s, 0)); \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ + gen_helper_##NAME(rd_v, v0_v, rs1, rs2_v, cpu_env, desc); \ + tcg_temp_free_ptr(rd_v); \ + tcg_temp_free_ptr(v0_v); \ + tcg_temp_free_ptr(rs2_v); \ + \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool zvkb_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && + s->cfg_ptr->ext_zvkb =3D=3D true; +} + +static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) +{ + return zvkb_vx_check(s, a) && + s->sew =3D=3D MO_64; +} + +GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 8a11e56754..c453d348ad 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -20,4 +20,16 @@ static void do_vclmul_vv(void *vd, void *vs1, void *vs2,= int i) ((uint64_t *)vd)[i] =3D result; } =20 +static void do_vclmul_vx(void *vd, target_long rs1, void *vs2, int i) +{ + uint64_t result =3D 0; + for (int j =3D 63; j >=3D 0; j--) { + if ((rs1 >> j) & 1) { + result ^=3D (((uint64_t *)vs2)[i] << j); + } + } + ((uint64_t *)vd)[i] =3D result; +} + GEN_VEXT_VV(vclmul_vv, 8) +GEN_VEXT_VX(vclmul_vx, 8) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index def1b21414..ab470092f6 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -747,8 +747,6 @@ GEN_VEXT_VV(vsub_vv_h, 2) GEN_VEXT_VV(vsub_vv_w, 4) GEN_VEXT_VV(vsub_vv_d, 8) =20 -typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); - /* * (T1)s1 gives the real operator type. * (TX1)(T1)s1 expands the operator type of widen or narrow operations. @@ -773,40 +771,6 @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) =20 -static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivx2_fn fn, uint32_t esz) -{ - uint32_t vm =3D vext_vm(desc); - uint32_t vl =3D env->vl; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); - uint32_t vma =3D vext_vma(desc); - uint32_t i; - - for (i =3D env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, s1, vs2, i); - } - env->vstart =3D 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVX */ -#define GEN_VEXT_VX(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vx(vd, v0, s1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VX(vadd_vx_b, 1) GEN_VEXT_VX(vadd_vx_h, 2) GEN_VEXT_VX(vadd_vx_w, 4) diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internal= s.c index a264797882..b23fa4dd74 100644 --- a/target/riscv/vector_internals.c +++ b/target/riscv/vector_internals.c @@ -37,3 +37,27 @@ void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); } + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + for (i =3D env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, s1, vs2, i); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h index f61803acc0..49529d2379 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -113,4 +113,20 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ do_##NAME, ESZ); \ } =20 +typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz); + +/* generate the helpers for OPIVX */ +#define GEN_VEXT_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vx(vd, v0, s1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + #endif /* TARGET_RISCV_VECTOR_INTERNAL_H */ --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16753492983915.63036925434551; Thu, 2 Feb 2023 06:48:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqz-0005TN-MJ; Thu, 02 Feb 2023 09:46:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvO-000748-Ur for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:47 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvM-0000eq-15 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:46 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvE-004Q6t-A8; Thu, 02 Feb 2023 12:42:37 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 04/39] target/riscv: Add vclmulh.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:41:55 +0000 Message-Id: <20230202124230.295997-5-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349300092100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 12 ++++++++++++ 4 files changed, 15 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6c786ef6f3..a155272701 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1140,3 +1140,4 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl,= tl, tl) /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4a7421354d..e26ea1df08 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -894,3 +894,4 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_a= es # *** RV64 Zvkb vector crypto extension *** vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm +vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn= _trans/trans_rvzvkb.c.inc index 6e8b81136c..19ce4c7431 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -39,6 +39,7 @@ static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) } =20 GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) +GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check) =20 #define GEN_VX_MASKED_TRANS(NAME, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index c453d348ad..022b941131 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -31,5 +31,17 @@ static void do_vclmul_vx(void *vd, target_long rs1, void= *vs2, int i) ((uint64_t *)vd)[i] =3D result; } =20 +static void do_vclmulh_vv(void *vd, void *vs1, void *vs2, int i) +{ + __uint128_t result =3D 0; + for (int j =3D 63; j >=3D 0; j--) { + if ((((uint64_t *)vs1)[i] >> j) & 1) { + result ^=3D (((__uint128_t)(((uint64_t *)vs2)[i])) << j); + } + } + ((uint64_t *)vd)[i] =3D (result >> 64); +} + GEN_VEXT_VV(vclmul_vv, 8) GEN_VEXT_VX(vclmul_vx, 8) +GEN_VEXT_VV(vclmulh_vv, 8) --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16753503888441023.6902766861741; Thu, 2 Feb 2023 07:06:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqu-0005OV-BY; Thu, 02 Feb 2023 09:46:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvO-000749-V5 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:47 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvM-0000es-16 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:46 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvE-004Q6t-IG; Thu, 02 Feb 2023 12:42:37 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 05/39] target/riscv: Add vclmulh.vx decoding, translation and execution support Date: Thu, 2 Feb 2023 12:41:56 +0000 Message-Id: <20230202124230.295997-6-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350391534100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 12 ++++++++++++ 4 files changed, 15 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a155272701..32f1179e29 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1141,3 +1141,4 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl,= tl, tl) DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e26ea1df08..b4d88dd1cb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -895,3 +895,4 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_a= es vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm +vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn= _trans/trans_rvzvkb.c.inc index 19ce4c7431..533141e559 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -94,3 +94,4 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) } =20 GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) +GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 022b941131..46e2e510c5 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -42,6 +42,18 @@ static void do_vclmulh_vv(void *vd, void *vs1, void *vs2= , int i) ((uint64_t *)vd)[i] =3D (result >> 64); } =20 +static void do_vclmulh_vx(void *vd, target_long rs1, void *vs2, int i) +{ + __uint128_t result =3D 0; + for (int j =3D 63; j >=3D 0; j--) { + if ((rs1 >> j) & 1) { + result ^=3D (((__uint128_t)(((uint64_t *)vs2)[i])) << j); + } + } + ((uint64_t *)vd)[i] =3D (result >> 64); +} + GEN_VEXT_VV(vclmul_vv, 8) GEN_VEXT_VX(vclmul_vx, 8) GEN_VEXT_VV(vclmulh_vv, 8) +GEN_VEXT_VX(vclmulh_vx, 8) --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675351266351416.90700290117195; Thu, 2 Feb 2023 07:21:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarC-0005XY-7O; Thu, 02 Feb 2023 09:46:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0007B8-8N for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:55 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvT-0000ep-Mc for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:54 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvE-004Q6t-Pk; Thu, 02 Feb 2023 12:42:37 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support Date: Thu, 2 Feb 2023 12:41:57 +0000 Message-Id: <20230202124230.295997-7-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675351268591100003 Content-Type: text/plain; charset="utf-8" From: Dickon Hood Add an initial implementation of the vrol.* and vror.* instructions, with mappings between the RISC-V instructions and their internal TCG accelerated implmentations. There are some missing ror helpers, so I've bodged it by converting them to rols. Co-authored-by: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk Signed-off-by: Dickon Hood --- target/riscv/helper.h | 20 ++++++++ target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvzvkb.c.inc | 20 ++++++++ target/riscv/vcrypto_helper.c | 58 ++++++++++++++++++++++ target/riscv/vector_helper.c | 45 ----------------- target/riscv/vector_internals.h | 52 +++++++++++++++++++ 6 files changed, 156 insertions(+), 45 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 32f1179e29..e5b6b3360f 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1142,3 +1142,23 @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, en= v, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b4d88dd1cb..725f907ad1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -896,3 +896,9 @@ vclmul_vv 001100 . ..... ..... 010 ..... 1010111 = @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm +vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm +vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm +vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm +vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm +vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm +vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn= _trans/trans_rvzvkb.c.inc index 533141e559..d2a7a92d42 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -95,3 +95,23 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) =20 GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) + +GEN_OPIVV_TRANS(vror_vv, zvkb_vv_check) +GEN_OPIVX_TRANS(vror_vx, zvkb_vx_check) +GEN_OPIVV_TRANS(vrol_vv, zvkb_vv_check) +GEN_OPIVX_TRANS(vrol_vx, zvkb_vx_check) + +GEN_OPIVI_TRANS(vror_vi, IMM_TRUNC_SEW, vror_vx, zvkb_vx_check) + +/* + * Immediates are 5b long, and we need six for the rotate-immediate. The + * decision has been taken to remove the vrol.vi instruction -- you can + * emulate it with a ror, after all -- and use the bottom bit of the funct6 + * part of the opcode to encode the extra bit. I've chosen to implement it + * like this because it's easy and reasonably clean. + */ +static bool trans_vror_vi2(DisasContext *s, arg_rmrr *a) +{ + a->rs1 +=3D 32; + return trans_vror_vi(s, a); +} diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 46e2e510c5..7ec75c5589 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -57,3 +57,61 @@ GEN_VEXT_VV(vclmul_vv, 8) GEN_VEXT_VX(vclmul_vx, 8) GEN_VEXT_VV(vclmulh_vv, 8) GEN_VEXT_VX(vclmulh_vx, 8) + +/* + * Looks a mess, but produces reasonable (aarch32) code on clang: + * https://godbolt.org/z/jchjsTda8 + */ +#define DO_ROR(x, n) \ + ((x >> (n & ((sizeof(x) << 3) - 1))) | \ + (x << ((sizeof(x) << 3) - (n & ((sizeof(x) << 3) - 1))))) +#define DO_ROL(x, n) \ + ((x << (n & ((sizeof(x) << 3) - 1))) | \ + (x >> ((sizeof(x) << 3) - (n & ((sizeof(x) << 3) - 1))))) + +RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, DO_ROR) +RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, DO_ROR) +RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, DO_ROR) +RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, DO_ROR) +GEN_VEXT_VV(vror_vv_b, 1) +GEN_VEXT_VV(vror_vv_h, 2) +GEN_VEXT_VV(vror_vv_w, 4) +GEN_VEXT_VV(vror_vv_d, 8) + +/* + * There's a missing tcg_gen_gvec_rotrs() helper function. + */ +#define GEN_VEXT_VX_RTOL(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + do_vext_vx(vd, v0, (ESZ << 3) - s1, vs2, env, desc, do_##NAME, ESZ); \ +} + +/* DO_ROL because GEN_VEXT_VX_RTOL() converts from R to L */ +RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, DO_ROL) +RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, DO_ROL) +RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, DO_ROL) +RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, DO_ROL) +GEN_VEXT_VX_RTOL(vror_vx_b, 1) +GEN_VEXT_VX_RTOL(vror_vx_h, 2) +GEN_VEXT_VX_RTOL(vror_vx_w, 4) +GEN_VEXT_VX_RTOL(vror_vx_d, 8) + +RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, DO_ROL) +RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, DO_ROL) +RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, DO_ROL) +RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, DO_ROL) +GEN_VEXT_VV(vrol_vv_b, 1) +GEN_VEXT_VV(vrol_vv_h, 2) +GEN_VEXT_VV(vrol_vv_w, 4) +GEN_VEXT_VV(vrol_vv_d, 8) + +RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, DO_ROL) +RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, DO_ROL) +RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, DO_ROL) +RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, DO_ROL) +GEN_VEXT_VX(vrol_vx_b, 1) +GEN_VEXT_VX(vrol_vx_h, 2) +GEN_VEXT_VX(vrol_vx_w, 4) +GEN_VEXT_VX(vrol_vx_d, 8) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ab470092f6..ff7b03cbe3 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -76,26 +76,6 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, return vl; } =20 -/* - * Note that vector data is stored in host-endian 64-bit chunks, - * so addressing units smaller than that needs a host-endian fixup. - */ -#if HOST_BIG_ENDIAN -#define H1(x) ((x) ^ 7) -#define H1_2(x) ((x) ^ 6) -#define H1_4(x) ((x) ^ 4) -#define H2(x) ((x) ^ 3) -#define H4(x) ((x) ^ 1) -#define H8(x) ((x)) -#else -#define H1(x) (x) -#define H1_2(x) (x) -#define H1_4(x) (x) -#define H2(x) (x) -#define H4(x) (x) -#define H8(x) (x) -#endif - /* * Get the maximum number of elements can be operated. * @@ -683,18 +663,11 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) *** Vector Integer Arithmetic Instructions */ =20 -/* expand macro args before macro */ -#define RVVCALL(macro, ...) macro(__VA_ARGS__) - /* (TD, T1, T2, TX1, TX2) */ #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t -#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t -#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t -#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t -#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t @@ -718,14 +691,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t =20 - -#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ -static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ -{ \ - TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2, s1); \ -} #define DO_SUB(N, M) (N - M) #define DO_RSUB(N, M) (M - N) =20 @@ -747,16 +712,6 @@ GEN_VEXT_VV(vsub_vv_h, 2) GEN_VEXT_VV(vsub_vv_w, 4) GEN_VEXT_VV(vsub_vv_d, 8) =20 -/* - * (T1)s1 gives the real operator type. - * (TX1)(T1)s1 expands the operator type of widen or narrow operations. - */ -#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1); \ -} =20 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD) RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD) diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h index 49529d2379..a0fbac7bf3 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -28,6 +28,26 @@ static inline uint32_t vext_nf(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, NF); } =20 +/* + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing units smaller than that needs a host-endian fixup. + */ +#if HOST_BIG_ENDIAN +#define H1(x) ((x) ^ 7) +#define H1_2(x) ((x) ^ 6) +#define H1_4(x) ((x) ^ 4) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#define H8(x) ((x)) +#else +#define H1(x) (x) +#define H1_2(x) (x) +#define H1_4(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#define H8(x) (x) +#endif + /* * Encode LMUL to lmul as following: * LMUL vlmul lmul @@ -96,9 +116,30 @@ static inline uint32_t vext_get_total_elems(CPURISCVSta= te *env, uint32_t desc, void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, uint32_t tot); =20 +/* + *** Vector Integer Arithmetic Instructions + */ + +/* expand macro args before macro */ +#define RVVCALL(macro, ...) macro(__VA_ARGS__) + +/* (TD, T1, T2, TX1, TX2) */ +#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t +#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t +#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t +#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t + /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); =20 +#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ +{ \ + TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2, s1); \ +} + void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc, opivv2_fn *fn, uint32_t esz); @@ -115,6 +156,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ =20 typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); =20 +/* + * (T1)s1 gives the real operator type. + * (TX1)(T1)s1 expands the operator type of widen or narrow operations. + */ +#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1); \ +} + void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, uint32_t desc, opivx2_fn fn, uint32_t esz); --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349424997950.284913902874; Thu, 2 Feb 2023 06:50:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqt-0005Nv-HJ; Thu, 02 Feb 2023 09:46:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvP-00074C-7i for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:47 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvM-0000f2-19 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:46 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvF-004Q6t-1v; Thu, 02 Feb 2023 12:42:37 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, William Salmon Subject: [PATCH 07/39] target/riscv: Add vbrev8.v decoding, translation and execution support Date: Thu, 2 Feb 2023 12:41:58 +0000 Message-Id: <20230202124230.295997-8-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349425685100001 Content-Type: text/plain; charset="utf-8" From: William Salmon Co-authored-by: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk Signed-off-by: William Salmon --- include/qemu/bitops.h | 32 +++++++++++++++++ target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 39 ++++++++++++++++++++ target/riscv/vcrypto_helper.c | 10 ++++++ target/riscv/vector_helper.c | 41 --------------------- target/riscv/vector_internals.h | 42 ++++++++++++++++++++++ 7 files changed, 129 insertions(+), 41 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 03213ce952..dfce1cb10c 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -618,4 +618,36 @@ static inline uint64_t half_unshuffle64(uint64_t x) return x; } =20 +static inline uint8_t reverse_bits_byte(uint8_t x) +{ + x =3D (((x & 0b10101010) >> 1) | ((x & 0b01010101) << 1)); + x =3D (((x & 0b11001100) >> 2) | ((x & 0b00110011) << 2)); + return ((x & 0b11110000) >> 4) | ((x & 0b00001111) << 4); +} + +static inline uint16_t reverse_bits_byte_2(uint16_t x) +{ + return (uint16_t)reverse_bits_byte(x & 0xFF) | \ + (uint16_t)reverse_bits_byte((x >> 8) & 0xFF) << 8; +} + +static inline uint32_t reverse_bits_byte_4(uint32_t x) +{ + return (uint32_t)reverse_bits_byte(x & 0xFF) | \ + (uint32_t)reverse_bits_byte((x >> 8) & 0xFF) << 8 | \ + (uint32_t)reverse_bits_byte((x >> 16) & 0xFF) << 16 | \ + (uint32_t)reverse_bits_byte((x >> 24) & 0xFF) << 24; +} + +static inline uint64_t reverse_bits_byte_8(uint64_t x) +{ + return (uint64_t)reverse_bits_byte(x & 0xFF) | \ + (uint64_t)reverse_bits_byte((x >> 8) & 0xFF) << 8 | \ + (uint64_t)reverse_bits_byte((x >> 16) & 0xFF) << 16 | \ + (uint64_t)reverse_bits_byte((x >> 24) & 0xFF) << 24 | \ + (uint64_t)reverse_bits_byte((x >> 32) & 0xFF) << 32 | \ + (uint64_t)reverse_bits_byte((x >> 40) & 0xFF) << 40 | \ + (uint64_t)reverse_bits_byte((x >> 48) & 0xFF) << 48 | \ + (uint64_t)reverse_bits_byte((x >> 56) & 0xFF) << 56; +} #endif diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e5b6b3360f..c94627d8a4 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1162,3 +1162,8 @@ DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env,= i32) DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 725f907ad1..782632a165 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -902,3 +902,4 @@ vror_vv 010100 . ..... ..... 000 ..... 1010111 = @r_vm vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm +vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn= _trans/trans_rvzvkb.c.inc index d2a7a92d42..591980459a 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -115,3 +115,42 @@ static bool trans_vror_vi2(DisasContext *s, arg_rmrr *= a) a->rs1 +=3D 32; return trans_vror_vi(s, a); } + +#define GEN_OPIV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmr * a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[4] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + TCGLabel *over =3D gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \ + data, fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool vxrev8_check(DisasContext *s, arg_rmr *a) +{ + return s->cfg_ptr->ext_zvkb =3D=3D true && vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_OPIV_TRANS(vbrev8_v, vxrev8_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 7ec75c5589..303a656141 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "qemu/bitops.h" +#include "qemu/bswap.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -115,3 +116,12 @@ GEN_VEXT_VX(vrol_vx_b, 1) GEN_VEXT_VX(vrol_vx_h, 2) GEN_VEXT_VX(vrol_vx_w, 4) GEN_VEXT_VX(vrol_vx_d, 8) + +RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, reverse_bits_byte) +RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, reverse_bits_byte_2) +RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, reverse_bits_byte_4) +RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, reverse_bits_byte_8) +GEN_VEXT_V(vbrev8_v_b, 1) +GEN_VEXT_V(vbrev8_v_h, 2) +GEN_VEXT_V(vbrev8_v_w, 4) +GEN_VEXT_V(vbrev8_v_d, 8) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ff7b03cbe3..07da4b5e16 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3437,12 +3437,6 @@ RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fw= nmsac32) GEN_VEXT_VF(vfwnmsac_vf_h, 4) GEN_VEXT_VF(vfwnmsac_vf_w, 8) =20 -/* Vector Floating-Point Square-Root Instruction */ -/* (TD, T2, TX2) */ -#define OP_UU_H uint16_t, uint16_t, uint16_t -#define OP_UU_W uint32_t, uint32_t, uint32_t -#define OP_UU_D uint64_t, uint64_t, uint64_t - #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i, \ CPURISCVState *env) \ @@ -4134,41 +4128,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) =20 -/* Vector Floating-Point Classify Instruction */ -#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, void *vs2, int i) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2); \ -} - -#define GEN_VEXT_V(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D \ - vext_get_total_elems(env, desc, ESZ); \ - uint32_t vta =3D vext_vta(desc); \ - uint32_t vma =3D vext_vma(desc); \ - uint32_t i; \ - \ - for (i =3D env->vstart; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - /* set masked-off elements to 1s */ \ - vext_set_elems_1s(vd, vma, i * ESZ, \ - (i + 1) * ESZ); \ - continue; \ - } \ - do_##NAME(vd, vs2, i); \ - } \ - env->vstart =3D 0; \ - /* set tail elements to 1s */ \ - vext_set_elems_1s(vd, vta, vl * ESZ, \ - total_elems * ESZ); \ -} - target_ulong fclass_h(uint64_t frs1) { float16 f =3D frs1; diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h index a0fbac7bf3..f1f16453dc 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -123,12 +123,54 @@ void vext_set_elems_1s(void *base, uint32_t is_agnost= ic, uint32_t cnt, /* expand macro args before macro */ #define RVVCALL(macro, ...) macro(__VA_ARGS__) =20 +/* Vector Floating-Point Square-Root Instruction */ +/* (TD, T2, TX2) */ +#define OP_UU_B uint8_t, uint8_t, uint8_t +#define OP_UU_H uint16_t, uint16_t, uint16_t +#define OP_UU_W uint32_t, uint32_t, uint32_t +#define OP_UU_D uint64_t, uint64_t, uint64_t + /* (TD, T1, T2, TX1, TX2) */ #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t =20 +/* Vector Floating-Point Classify Instruction */ +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, void *vs2, int i) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2); \ +} + +#define GEN_VEXT_V(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t total_elems =3D \ + vext_get_total_elems(env, desc, ESZ); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ + uint32_t i; \ + \ + for (i =3D env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * ESZ, \ + total_elems * ESZ); \ +} + /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); =20 --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350406469488.0964206403204; Thu, 2 Feb 2023 07:06:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqu-0005OI-5X; Thu, 02 Feb 2023 09:46:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvO-00074A-TV for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:47 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvM-0000f3-17 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:46 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvF-004Q6t-9B; Thu, 02 Feb 2023 12:42:38 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 08/39] target/riscv: Add vrev8.v decoding, translation and execution support Date: Thu, 2 Feb 2023 12:41:59 +0000 Message-Id: <20230202124230.295997-9-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350407211100003 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 4 ++++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 10 ++++++++++ 4 files changed, 16 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c94627d8a4..c980d52828 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1163,6 +1163,10 @@ DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env= , i32) DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 782632a165..342199abc0 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -903,3 +903,4 @@ vror_vx 010100 . ..... ..... 100 ..... 1010111 = @r_vm vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn= _trans/trans_rvzvkb.c.inc index 591980459a..18b362db92 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -154,3 +154,4 @@ static bool vxrev8_check(DisasContext *s, arg_rmr *a) } =20 GEN_OPIV_TRANS(vbrev8_v, vxrev8_check) +GEN_OPIV_TRANS(vrev8_v, vxrev8_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 303a656141..b09fe5fa2a 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -125,3 +125,13 @@ GEN_VEXT_V(vbrev8_v_b, 1) GEN_VEXT_V(vbrev8_v_h, 2) GEN_VEXT_V(vbrev8_v_w, 4) GEN_VEXT_V(vbrev8_v_d, 8) + +#define DO_VREV8_B(a) (a) +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_VREV8_B) +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) +GEN_VEXT_V(vrev8_v_b, 1) +GEN_VEXT_V(vrev8_v_h, 2) +GEN_VEXT_V(vrev8_v_w, 4) +GEN_VEXT_V(vrev8_v_d, 8) --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349244009784.024067311862; Thu, 2 Feb 2023 06:47:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqy-0005Rz-65; Thu, 02 Feb 2023 09:46:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvN-00073x-Qa for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:45 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvL-0000f9-Vu for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:45 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvF-004Q6t-H4; Thu, 02 Feb 2023 12:42:38 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 09/39] target/riscv: Add vandn.[vv, vx, vi] decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:00 +0000 Message-Id: <20230202124230.295997-10-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349245622100004 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 9 +++++++++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvzvkb.c.inc | 5 +++++ target/riscv/vcrypto_helper.c | 19 +++++++++++++++++++ 4 files changed, 36 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c980d52828..5de615ea78 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1171,3 +1171,12 @@ DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i= 32) DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 342199abc0..d6f5e4d198 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -904,3 +904,6 @@ vror_vi 010100 . ..... ..... 011 ..... 1010111 = @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm +vandn_vi 000001 . ..... ..... 011 ..... 1010111 @r_vm +vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm +vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn= _trans/trans_rvzvkb.c.inc index 18b362db92..a973b27bdd 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -147,6 +147,11 @@ static bool trans_##NAME(DisasContext *s, arg_rmr * a)= \ return false; \ } =20 + +GEN_OPIVV_TRANS(vandn_vv, zvkb_vv_check) +GEN_OPIVX_TRANS(vandn_vx, zvkb_vx_check) +GEN_OPIVI_TRANS(vandn_vi, IMM_SX, vandn_vx, zvkb_vx_check) + static bool vxrev8_check(DisasContext *s, arg_rmr *a) { return s->cfg_ptr->ext_zvkb =3D=3D true && vext_check_isa_ill(s) && diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index b09fe5fa2a..900e68dfb0 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -135,3 +135,22 @@ GEN_VEXT_V(vrev8_v_b, 1) GEN_VEXT_V(vrev8_v_h, 2) GEN_VEXT_V(vrev8_v_w, 4) GEN_VEXT_V(vrev8_v_d, 8) + +#define DO_ANDN(a, b) ((b) & ~(a)) +RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN) +GEN_VEXT_VV(vandn_vv_b, 1) +GEN_VEXT_VV(vandn_vv_h, 2) +GEN_VEXT_VV(vandn_vv_w, 4) +GEN_VEXT_VV(vandn_vv_d, 8) + +RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN) +GEN_VEXT_VX(vandn_vx_b, 1) +GEN_VEXT_VX(vandn_vx_h, 2) +GEN_VEXT_VX(vandn_vx_w, 4) +GEN_VEXT_VX(vandn_vx_d, 8) --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350399860713.78715321234; Thu, 2 Feb 2023 07:06:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqx-0005RS-BU; Thu, 02 Feb 2023 09:46:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvN-00073q-CB for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:45 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvL-0000fJ-VU for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:45 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvF-004Q6t-Of; Thu, 02 Feb 2023 12:42:38 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 10/39] target/riscv: expose zvkb cpu property Date: Thu, 2 Feb 2023 12:42:01 +0000 Message-Id: <20230202124230.295997-11-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350401196100002 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov Reviewed-by: Philipp Tomsich --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bd34119c75..35790befc0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1082,6 +1082,8 @@ static Property riscv_cpu_extensions[] =3D { =20 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), =20 + DEFINE_PROP_BOOL("zvkb", RISCVCPU, cfg.ext_zvkb, false), + /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16753492691221020.030818751551; Thu, 2 Feb 2023 06:47:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarF-0005Zi-Vu; Thu, 02 Feb 2023 09:46:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvQ-00074n-TG for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:49 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvM-0000fB-8u for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:47 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvF-004Q6t-WE; Thu, 02 Feb 2023 12:42:38 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 11/39] target/riscv: add zvkns cpu property Date: Thu, 2 Feb 2023 12:42:02 +0000 Message-Id: <20230202124230.295997-12-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349269704100001 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 35790befc0..fd09822b4f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb), + ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), @@ -797,7 +798,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) * In principle zve*{x,d} would also suffice here, were they suppo= rted * in qemu */ - if (cpu->cfg.ext_zvkb && + if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns) && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v= )) { error_setg( errp, "Vector crypto extensions require V or Zve* extensio= ns"); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d4824ad0bb..56008ef9b9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -462,6 +462,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zvkb; + bool ext_zvkns; bool ext_zmmul; bool ext_smaia; bool ext_ssaia; --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167534921139456.33720860760343; Thu, 2 Feb 2023 06:46:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqv-0005Q7-TF; Thu, 02 Feb 2023 09:46:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvW-00079X-Qp for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:55 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvU-0000fZ-1m for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:54 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvG-004Q6t-8W; Thu, 02 Feb 2023 12:42:39 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 12/39] target/riscv: Add vaesef.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:03 +0000 Message-Id: <20230202124230.295997-13-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349214400100006 Content-Type: text/plain; charset="utf-8" Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvzvkns.c.inc | 40 +++++++++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 75 +++++++++++++++++++++ 5 files changed, 122 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5de615ea78..bdfa63302e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1180,3 +1180,5 @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env= , i32) DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d6f5e4d198..fdaab9a189 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -74,6 +74,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=3D1 %rs2 %rd @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd @@ -907,3 +908,6 @@ vrev8_v 010010 . ..... 01001 010 ..... 1010111 = @r2_vm vandn_vi 000001 . ..... ..... 011 ..... 1010111 @r_vm vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm + +# *** RV64 Zvkns vector crypto extension *** +vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc new file mode 100644 index 0000000000..16e2c58001 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -0,0 +1,40 @@ +#define GEN_V_UNMASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (CHECK(s, a)) { \ + TCGv_ptr rd_v, rs2_v; \ + TCGv_i32 desc; \ + uint32_t data =3D 0; = \ + \ + TCGLabel *over =3D gen_new_label(); = \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); = \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, = \ + s->cfg_ptr->vlen / 8, data)); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ + gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); \ + tcg_temp_free_ptr(rd_v); \ + tcg_temp_free_ptr(rs2_v); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + + +static bool vaes_check_vv(DisasContext *s, arg_rmr *a) +{ + return s->cfg_ptr->ext_zvkns =3D=3D true && vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul)= && + s->vstart % 4 =3D=3D 0 && s->sew =3D=3D MO_32; +} +GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 71684c10f3..8d39743de2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1064,6 +1064,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_rvzvkb.c.inc" +#include "insn_trans/trans_rvzvkns.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 900e68dfb0..59d7d32a05 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -3,6 +3,7 @@ #include "qemu/bitops.h" #include "qemu/bswap.h" #include "cpu.h" +#include "crypto/aes.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -154,3 +155,77 @@ GEN_VEXT_VX(vandn_vx_b, 1) GEN_VEXT_VX(vandn_vx_h, 2) GEN_VEXT_VX(vandn_vx_w, 4) GEN_VEXT_VX(vandn_vx_d, 8) + +static inline void aes_sub_bytes(uint8_t round_state[4][4]) +{ + for (int j =3D 0; j < 16; j++) { + round_state[j / 4][j % 4] =3D AES_sbox[round_state[j / 4][j % 4]]; + } +} + +static inline void aes_shift_bytes(uint8_t round_state[4][4]) +{ + uint8_t temp; + temp =3D round_state[0][1]; + round_state[0][1] =3D round_state[1][1]; + round_state[1][1] =3D round_state[2][1]; + round_state[2][1] =3D round_state[3][1]; + round_state[3][1] =3D temp; + temp =3D round_state[0][2]; + round_state[0][2] =3D round_state[2][2]; + round_state[2][2] =3D temp; + temp =3D round_state[1][2]; + round_state[1][2] =3D round_state[3][2]; + round_state[3][2] =3D temp; + temp =3D round_state[0][3]; + round_state[0][3] =3D round_state[3][3]; + round_state[3][3] =3D round_state[2][3]; + round_state[2][3] =3D round_state[1][3]; + round_state[1][3] =3D temp; +} + +static inline void xor_round_key(uint8_t round_state[4][4], uint8_t *round= _key) +{ + for (int j =3D 0; j < 16; j++) { + round_state[j / 4][j % 4] =3D round_state[j / 4][j % 4] ^ (round_k= ey)[j]; + } +} + +#define GEN_ZVKNS_HELPER_VV(NAME, ...) \ +void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint64_t *vd =3D vd_vptr; = \ + uint64_t *vs2 =3D vs2_vptr; = \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + if (env->vl % 4 !=3D 0) { = \ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); \ + } \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + uint64_t round_key[2] =3D { = \ + cpu_to_le64(vs2[i * 2 + 0]), \ + cpu_to_le64(vs2[i * 2 + 1]), \ + }; \ + uint8_t round_state[4][4]; \ + cpu_to_le64s(vd + i * 2 + 0); \ + cpu_to_le64s(vd + i * 2 + 1); \ + for (int j =3D 0; j < 16; j++) { = \ + round_state[j / 4][j % 4] =3D ((uint8_t *)(vd + i * 2))[j]; = \ + } \ + __VA_ARGS__; \ + for (int j =3D 0; j < 16; j++) { = \ + ((uint8_t *)(vd + i * 2))[j] =3D round_state[j / 4][j % 4]; = \ + } \ + le64_to_cpus(vd + i * 2 + 0); \ + le64_to_cpus(vd + i * 2 + 1); \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ +} + +GEN_ZVKNS_HELPER_VV(vaesef_vv, aes_sub_bytes(round_state); + aes_shift_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349211391516.6363992672724; Thu, 2 Feb 2023 06:46:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqz-0005T8-Hc; Thu, 02 Feb 2023 09:46:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvW-00079G-Kw for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:54 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvU-0000fl-Le for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:54 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvG-004Q6t-Gk; Thu, 02 Feb 2023 12:42:39 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 13/39] target/riscv: Add vaesef.vs decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:04 +0000 Message-Id: <20230202124230.295997-14-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349213763100004 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 16 +++++++++ target/riscv/vcrypto_helper.c | 38 +++++++++++++++++++++ 4 files changed, 56 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index bdfa63302e..42349837ef 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1182,3 +1182,4 @@ DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env= , i32) DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index fdaab9a189..0d65c2ea27 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -911,3 +911,4 @@ vandn_vx 000001 . ..... ..... 100 ..... 1010111 = @r_vm =20 # *** RV64 Zvkns vector crypto extension *** vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index 16e2c58001..2317af02a9 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -37,4 +37,20 @@ static bool vaes_check_vv(DisasContext *s, arg_rmr *a) require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul)= && s->vstart % 4 =3D=3D 0 && s->sew =3D=3D MO_32; } + +static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) +{ + int8_t op_size =3D s->lmul <=3D 0 ? 1 : 1 << s->lmul; + return !is_overlapped(vd, op_size, vs2, op_size); +} + +static bool vaes_check_vs(DisasContext *s, arg_rmr *a) +{ + return vaes_check_overlap(s, a->rd, a->rs2) && + s->cfg_ptr->ext_zvkns =3D=3D true && vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && s->vstart % 4 =3D=3D 0 && + s->sew =3D=3D MO_32; +} + GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 59d7d32a05..f59e090c03 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -226,6 +226,44 @@ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURI= SCVState *env, \ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ } =20 +#define GEN_ZVKNS_HELPER_VS(NAME, ...) \ +void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint64_t *vd =3D vd_vptr; = \ + uint64_t *vs2 =3D vs2_vptr; = \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + if (env->vl % 4 !=3D 0) { = \ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); \ + } \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + uint64_t round_key[2] =3D { = \ + cpu_to_le64(vs2[0]), \ + cpu_to_le64(vs2[1]), \ + }; \ + uint8_t round_state[4][4]; \ + cpu_to_le64s(vd + i * 2 + 0); \ + cpu_to_le64s(vd + i * 2 + 1); \ + for (int j =3D 0; j < 16; j++) { = \ + round_state[j / 4][j % 4] =3D ((uint8_t *)(vd + i * 2))[j]; = \ + } \ + __VA_ARGS__; \ + for (int j =3D 0; j < 16; j++) { = \ + ((uint8_t *)(vd + i * 2))[j] =3D round_state[j / 4][j % 4]; = \ + } \ + le64_to_cpus(vd + i * 2 + 0); \ + le64_to_cpus(vd + i * 2 + 1); \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ +} + GEN_ZVKNS_HELPER_VV(vaesef_vv, aes_sub_bytes(round_state); aes_shift_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VS(vaesef_vs, aes_sub_bytes(round_state); + aes_shift_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) --=20 2.39.1 From nobody Fri Apr 26 03:46:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16753493880301020.6043862239742; Thu, 2 Feb 2023 06:49:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarg-0006AO-E0; Thu, 02 Feb 2023 09:47:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0007Em-Ut for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:56 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvV-0000fh-0l for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:55 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvG-004Q6t-Ow; Thu, 02 Feb 2023 12:42:39 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 14/39] target/riscv: Add vaesdf.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:05 +0000 Message-Id: <20230202124230.295997-15-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349389616100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 31 +++++++++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 42349837ef..b7696cb6c4 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1183,3 +1183,4 @@ DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env= , i32) =20 DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0d65c2ea27..ca907dac85 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -912,3 +912,4 @@ vandn_vx 000001 . ..... ..... 100 ..... 1010111 = @r_vm # *** RV64 Zvkns vector crypto extension *** vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index 2317af02a9..2e09deeb84 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -54,3 +54,4 @@ static bool vaes_check_vs(DisasContext *s, arg_rmr *a) =20 GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index f59e090c03..24b5336fa7 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -191,6 +191,34 @@ static inline void xor_round_key(uint8_t round_state[4= ][4], uint8_t *round_key) } } =20 +static inline void aes_inv_sub_bytes(uint8_t round_state[4][4]) +{ + for (int j =3D 0; j < 16; j++) { + round_state[j / 4][j % 4] =3D AES_isbox[round_state[j / 4][j % 4]]; + } +} + +static inline void aes_inv_shift_bytes(uint8_t round_state[4][4]) +{ + uint8_t temp; + temp =3D round_state[3][1]; + round_state[3][1] =3D round_state[2][1]; + round_state[2][1] =3D round_state[1][1]; + round_state[1][1] =3D round_state[0][1]; + round_state[0][1] =3D temp; + temp =3D round_state[0][2]; + round_state[0][2] =3D round_state[2][2]; + round_state[2][2] =3D temp; + temp =3D round_state[1][2]; + round_state[1][2] =3D round_state[3][2]; + round_state[3][2] =3D temp; + temp =3D round_state[0][3]; + round_state[0][3] =3D round_state[1][3]; + round_state[1][3] =3D round_state[2][3]; + round_state[2][3] =3D round_state[3][3]; + round_state[3][3] =3D temp; +} + #define GEN_ZVKNS_HELPER_VV(NAME, ...) \ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ uint32_t desc) \ @@ -267,3 +295,6 @@ GEN_ZVKNS_HELPER_VV(vaesef_vv, aes_sub_bytes(round_stat= e); GEN_ZVKNS_HELPER_VS(vaesef_vs, aes_sub_bytes(round_state); aes_shift_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675352142514947.2364696190798; Thu, 2 Feb 2023 07:35:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqv-0005PU-4W; Thu, 02 Feb 2023 09:46:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvW-00079F-HJ for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:54 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvU-0000fg-B1 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:54 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvH-004Q6t-0K; Thu, 02 Feb 2023 12:42:39 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 15/39] target/riscv: Add vaesdf.vs decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:06 +0000 Message-Id: <20230202124230.295997-16-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675352143162100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 3 +++ 4 files changed, 6 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b7696cb6c4..020b9861cf 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1184,3 +1184,4 @@ DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env= , i32) DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ca907dac85..33e5883937 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -913,3 +913,4 @@ vandn_vx 000001 . ..... ..... 100 ..... 1010111 = @r_vm vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index 2e09deeb84..2d6a92c153 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -55,3 +55,4 @@ static bool vaes_check_vs(DisasContext *s, arg_rmr *a) GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 24b5336fa7..d3ba5e9cb8 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -298,3 +298,6 @@ GEN_ZVKNS_HELPER_VS(vaesef_vs, aes_sub_bytes(round_stat= e); GEN_ZVKNS_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349243836344.49334342949874; Thu, 2 Feb 2023 06:47:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarR-0005ut-AN; Thu, 02 Feb 2023 09:46:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvW-00079Z-RE for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:55 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvU-0000fo-Ua for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:54 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvH-004Q6t-8L; Thu, 02 Feb 2023 12:42:40 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 16/39] target/riscv: Add vaesdm.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:07 +0000 Message-Id: <20230202124230.295997-17-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349245620100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 36 +++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 020b9861cf..328a026039 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1185,3 +1185,4 @@ DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 33e5883937..e5f3af999d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -914,3 +914,4 @@ vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 = @r2_vm_1 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index 2d6a92c153..6cb25d0d88 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -56,3 +56,4 @@ GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index d3ba5e9cb8..bac21b5623 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -219,6 +219,38 @@ static inline void aes_inv_shift_bytes(uint8_t round_s= tate[4][4]) round_state[3][3] =3D temp; } =20 +static inline uint8_t xtime(uint8_t x) +{ + return (x << 1) ^ (((x >> 7) & 1) * 0x1b); +} + +static inline uint8_t multiply(uint8_t x, uint8_t y) +{ + return (((y & 1) * x) ^ ((y >> 1 & 1) * xtime(x)) ^ + ((y >> 2 & 1) * xtime(xtime(x))) ^ + ((y >> 3 & 1) * xtime(xtime(xtime(x)))) ^ + ((y >> 4 & 1) * xtime(xtime(xtime(xtime(x)))))); +} + +static inline void aes_inv_mix_cols(uint8_t round_state[4][4]) +{ + uint8_t a, b, c, d; + for (int j =3D 0; j < 4; ++j) { + a =3D round_state[j][0]; + b =3D round_state[j][1]; + c =3D round_state[j][2]; + d =3D round_state[j][3]; + round_state[j][0] =3D multiply(a, 0x0e) ^ multiply(b, 0x0b) ^ + multiply(c, 0x0d) ^ multiply(d, 0x09); + round_state[j][1] =3D multiply(a, 0x09) ^ multiply(b, 0x0e) ^ + multiply(c, 0x0b) ^ multiply(d, 0x0d); + round_state[j][2] =3D multiply(a, 0x0d) ^ multiply(b, 0x09) ^ + multiply(c, 0x0e) ^ multiply(d, 0x0b); + round_state[j][3] =3D multiply(a, 0x0b) ^ multiply(b, 0x0d) ^ + multiply(c, 0x09) ^ multiply(d, 0x0e); + } +} + #define GEN_ZVKNS_HELPER_VV(NAME, ...) \ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ uint32_t desc) \ @@ -301,3 +333,7 @@ GEN_ZVKNS_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(roun= d_state); GEN_ZVKNS_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key); + aes_inv_mix_cols(round_state);) --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349372902862.2426140077912; Thu, 2 Feb 2023 06:49:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqu-0005Og-Jw; Thu, 02 Feb 2023 09:46:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0007F3-Vi for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:56 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvV-0000ft-0r for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:55 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvH-004Q6t-Gv; Thu, 02 Feb 2023 12:42:40 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 17/39] target/riscv: Add vaesdm.vs decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:08 +0000 Message-Id: <20230202124230.295997-18-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349373320100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 4 ++++ 4 files changed, 7 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 328a026039..9895bf5712 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1186,3 +1186,4 @@ DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e5f3af999d..753039e954 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -915,3 +915,4 @@ vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 = @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index 6cb25d0d88..1459cb6d26 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -57,3 +57,4 @@ GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index bac21b5623..699bf25bbd 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -337,3 +337,7 @@ GEN_ZVKNS_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(roun= d_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key); aes_inv_mix_cols(round_state);) +GEN_ZVKNS_HELPER_VS(vaesdm_vs, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key); + aes_inv_mix_cols(round_state);) --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675352175117869.5324628600423; Thu, 2 Feb 2023 07:36:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarO-0005tK-5f; Thu, 02 Feb 2023 09:46:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvY-0007GQ-9b for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:57 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvV-0000fw-6K for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:55 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvH-004Q6t-PN; Thu, 02 Feb 2023 12:42:40 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 18/39] target/riscv: Add vaesz.vs decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:09 +0000 Message-Id: <20230202124230.295997-19-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675352176985100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 13 ++++++++----- target/riscv/vcrypto_helper.c | 2 ++ 4 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9895bf5712..def126a59b 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1187,3 +1187,4 @@ DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 753039e954..b4ddc2586c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -916,3 +916,4 @@ vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 = @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index 1459cb6d26..022fdeec00 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -41,15 +41,17 @@ static bool vaes_check_vv(DisasContext *s, arg_rmr *a) static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) { int8_t op_size =3D s->lmul <=3D 0 ? 1 : 1 << s->lmul; - return !is_overlapped(vd, op_size, vs2, op_size); + return !is_overlapped(vd, op_size, vs2, 1); } =20 static bool vaes_check_vs(DisasContext *s, arg_rmr *a) { - return vaes_check_overlap(s, a->rd, a->rs2) && - s->cfg_ptr->ext_zvkns =3D=3D true && vext_check_isa_ill(s) && - require_align(a->rd, s->lmul) && s->vstart % 4 =3D=3D 0 && - s->sew =3D=3D MO_32; + return require_rvv(s) && + vaes_check_overlap(s, a->rd, a->rs2) && + s->cfg_ptr->ext_zvkns =3D=3D true && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + s->vstart % 4 =3D=3D 0 && s->sew =3D=3D MO_32; } =20 GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) @@ -58,3 +60,4 @@ GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 699bf25bbd..39e2498b7d 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -341,3 +341,5 @@ GEN_ZVKNS_HELPER_VS(vaesdm_vs, aes_inv_shift_bytes(roun= d_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key); aes_inv_mix_cols(round_state);) +GEN_ZVKNS_HELPER_VS(vaesz_vs, + xor_round_key(round_state, (uint8_t *)round_key);) --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350423907763.5465883058732; Thu, 2 Feb 2023 07:07:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqx-0005RU-Dc; Thu, 02 Feb 2023 09:46:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvY-0007GP-8n for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:57 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvV-0000g0-F8 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:55 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvI-004Q6t-1X; Thu, 02 Feb 2023 12:42:40 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, William Salmon Subject: [PATCH 19/39] target/riscv: Add vaesem.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:10 +0000 Message-Id: <20230202124230.295997-20-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350425534100003 Content-Type: text/plain; charset="utf-8" From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 17 +++++++++++++++++ 4 files changed, 20 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index def126a59b..4bfc9a3387 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1185,6 +1185,7 @@ DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b4ddc2586c..f31414f72c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -914,6 +914,7 @@ vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 = @r2_vm_1 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index 022fdeec00..e9080c61d2 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -61,3 +61,4 @@ GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 39e2498b7d..a1d66a64aa 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -251,6 +251,20 @@ static inline void aes_inv_mix_cols(uint8_t round_stat= e[4][4]) } } =20 +static inline void aes_mix_cols(uint8_t round_state[4][4]) +{ + uint8_t a, b; + for (int j =3D 0; j < 4; ++j) { + a =3D round_state[j][0]; + b =3D round_state[j][0] ^ round_state[j][1] ^ round_state[j][2] ^ + round_state[j][3]; + round_state[j][0] ^=3D xtime(round_state[j][0] ^ round_state[j][1]= ) ^ b; + round_state[j][1] ^=3D xtime(round_state[j][1] ^ round_state[j][2]= ) ^ b; + round_state[j][2] ^=3D xtime(round_state[j][2] ^ round_state[j][3]= ) ^ b; + round_state[j][3] ^=3D xtime(round_state[j][3] ^ a) ^ b; + } +} + #define GEN_ZVKNS_HELPER_VV(NAME, ...) \ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ uint32_t desc) \ @@ -333,6 +347,9 @@ GEN_ZVKNS_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(roun= d_state); GEN_ZVKNS_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VV(vaesem_vv, aes_shift_bytes(round_state); + aes_sub_bytes(round_state); aes_mix_cols(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) GEN_ZVKNS_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key); --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675351744501399.09058808322004; Thu, 2 Feb 2023 07:29:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaro-0006DR-28; Thu, 02 Feb 2023 09:47:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007HO-C8 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvV-0000g3-Vv for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:56 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvI-004Q6t-9x; Thu, 02 Feb 2023 12:42:41 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, William Salmon Subject: [PATCH 20/39] target/riscv: Add vaesem.vs decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:11 +0000 Message-Id: <20230202124230.295997-21-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675351745631100001 Content-Type: text/plain; charset="utf-8" From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 3 +++ 4 files changed, 6 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4bfc9a3387..85981f2cad 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1186,6 +1186,7 @@ DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f31414f72c..cc91ca8794 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -915,6 +915,7 @@ vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 = @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 +vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index e9080c61d2..fd79b384ac 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -62,3 +62,4 @@ GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index a1d66a64aa..883739f4ac 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -350,6 +350,9 @@ GEN_ZVKNS_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(roun= d_state); GEN_ZVKNS_HELPER_VV(vaesem_vv, aes_shift_bytes(round_state); aes_sub_bytes(round_state); aes_mix_cols(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VS(vaesem_vs, aes_shift_bytes(round_state); + aes_sub_bytes(round_state); aes_mix_cols(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) GEN_ZVKNS_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key); --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675351276037912.4971137912189; Thu, 2 Feb 2023 07:21:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqy-0005SU-CY; Thu, 02 Feb 2023 09:46:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007HR-D2 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvV-0000gA-U4 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:56 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvI-004Q6t-HZ; Thu, 02 Feb 2023 12:42:41 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 21/39] target/riscv: Add vaeskf1.vi decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:12 +0000 Message-Id: <20230202124230.295997-22-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675351278063100001 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 45 +++++++++++++++++++++ target/riscv/vcrypto_helper.c | 42 +++++++++++++++++++ 4 files changed, 89 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 85981f2cad..2ac02dde01 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1190,3 +1190,4 @@ DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) +DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index cc91ca8794..325e2401c8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -919,3 +919,4 @@ vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 = @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 +vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index fd79b384ac..27ff4f097c 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -63,3 +63,48 @@ GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs) + +#define GEN_VI_UNMASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (CHECK(s, a)) { \ + TCGv_ptr rd_v, rs2_v; \ + TCGv_i32 uimm_v, desc; \ + uint32_t data =3D 0; = \ + \ + TCGLabel *over =3D gen_new_label(); = \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); = \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + uimm_v =3D tcg_constant_i32(a->rs1); = \ + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, = \ + s->cfg_ptr->vlen / 8, data)); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ + gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \ + tcg_temp_free_ptr(rd_v); \ + tcg_temp_free_ptr(rs2_v); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi * a) +{ + return s->cfg_ptr->ext_zvkns =3D=3D true && vext_check_isa_ill(s) && + s->vstart % 4 =3D=3D 0 && s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul)= && + a->rs1 >=3D 1 && a->rs1 <=3D 10; +} + +GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 883739f4ac..13ceb705cd 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -363,3 +363,45 @@ GEN_ZVKNS_HELPER_VS(vaesdm_vs, aes_inv_shift_bytes(rou= nd_state); aes_inv_mix_cols(round_state);) GEN_ZVKNS_HELPER_VS(vaesz_vs, xor_round_key(round_state, (uint8_t *)round_key);) + +void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + if (vl % 4 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[8]; + static const uint32_t rcon[] =3D { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] =3D bswap32(vs2[i * 4 + H4(0)]); + rk[1] =3D bswap32(vs2[i * 4 + H4(1)]); + rk[2] =3D bswap32(vs2[i * 4 + H4(2)]); + rk[3] =3D bswap32(vs2[i * 4 + H4(3)]); + + rk[4] =3D rk[0] ^ (AES_Te4[(rk[3] >> 16) & 0xff] & 0xff000000) ^ + (AES_Te4[(rk[3] >> 8) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[3] >> 0) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[3] >> 24) & 0xff] & 0x000000ff) ^ rcon[uimm -= 1]; + rk[5] =3D rk[1] ^ rk[4]; + rk[6] =3D rk[2] ^ rk[5]; + rk[7] =3D rk[3] ^ rk[6]; + + vd[i * 4 + H4(0)] =3D bswap32(rk[4]); + vd[i * 4 + H4(1)] =3D bswap32(rk[5]); + vd[i * 4 + H4(2)] =3D bswap32(rk[6]); + vd[i * 4 + H4(3)] =3D bswap32(rk[7]); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349365017603.9495780026406; Thu, 2 Feb 2023 06:49:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarU-00063g-Fj; Thu, 02 Feb 2023 09:46:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007HM-9v for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvW-0000gF-8F for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:57 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvI-004Q6t-PG; Thu, 02 Feb 2023 12:42:41 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 22/39] target/riscv: Add vaeskf2.vi decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:13 +0000 Message-Id: <20230202124230.295997-23-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349365482100001 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 9 ++++ target/riscv/vcrypto_helper.c | 56 +++++++++++++++++++++ 4 files changed, 67 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 2ac02dde01..312f59bb38 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1191,3 +1191,4 @@ DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 325e2401c8..1eed0a6b26 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -920,3 +920,4 @@ vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 = @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/ins= n_trans/trans_rvzvkns.c.inc index 27ff4f097c..7daac1de5d 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -107,4 +107,13 @@ static bool vaeskf1_check(DisasContext *s, arg_vaeskf1= _vi * a) a->rs1 >=3D 1 && a->rs1 <=3D 10; } =20 +static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a) +{ + return s->cfg_ptr->ext_zvkns =3D=3D true && vext_check_isa_ill(s) && + s->vstart % 4 =3D=3D 0 && s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul)= && + a->rs1 >=3D 2 && a->rs1 <=3D 14; +} + GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check) +GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 13ceb705cd..50207b4ff0 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -405,3 +405,59 @@ void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr,= uint32_t uimm, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); } + +void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + if (env->vl % 4 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[12]; + static const uint32_t rcon[] =3D { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] =3D bswap32(vd[i * 4 + H4(0)]); + rk[1] =3D bswap32(vd[i * 4 + H4(1)]); + rk[2] =3D bswap32(vd[i * 4 + H4(2)]); + rk[3] =3D bswap32(vd[i * 4 + H4(3)]); + rk[4] =3D bswap32(vs2[i * 4 + H4(0)]); + rk[5] =3D bswap32(vs2[i * 4 + H4(1)]); + rk[6] =3D bswap32(vs2[i * 4 + H4(2)]); + rk[7] =3D bswap32(vs2[i * 4 + H4(3)]); + + if (uimm % 2 =3D=3D 0) { + rk[8] =3D rk[0] ^ (AES_Te4[(rk[7] >> 16) & 0xff] & 0xff000000)= ^ + (AES_Te4[(rk[7] >> 8) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[7] >> 0) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[7] >> 24) & 0xff] & 0x000000ff) ^ + rcon[(uimm - 1) / 2]; + rk[9] =3D rk[1] ^ rk[8]; + rk[10] =3D rk[2] ^ rk[9]; + rk[11] =3D rk[3] ^ rk[10]; + } else { + rk[8] =3D rk[0] ^ (AES_Te4[(rk[7] >> 24) & 0xff] & 0xff000000)= ^ + (AES_Te4[(rk[7] >> 16) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[7] >> 8) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[7] >> 0) & 0xff] & 0x000000ff); + rk[9] =3D rk[1] ^ rk[8]; + rk[10] =3D rk[2] ^ rk[9]; + rk[11] =3D rk[3] ^ rk[10]; + } + + vd[i * 4 + H4(0)] =3D bswap32(rk[8]); + vd[i * 4 + H4(1)] =3D bswap32(rk[9]); + vd[i * 4 + H4(2)] =3D bswap32(rk[10]); + vd[i * 4 + H4(3)] =3D bswap32(rk[11]); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167534936827170.16746030519732; Thu, 2 Feb 2023 06:49:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqw-0005QC-Hs; Thu, 02 Feb 2023 09:46:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007HN-B5 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvW-0000gf-Ua for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:57 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvJ-004Q6t-10; Thu, 02 Feb 2023 12:42:41 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 23/39] target/riscv: expose zvkns cpu property Date: Thu, 2 Feb 2023 12:42:14 +0000 Message-Id: <20230202124230.295997-24-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349369347100003 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd09822b4f..0da04d0be1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1084,6 +1084,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), =20 DEFINE_PROP_BOOL("zvkb", RISCVCPU, cfg.ext_zvkb, false), + DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), =20 /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349330211391.44282065890263; Thu, 2 Feb 2023 06:48:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarW-00065d-6R; Thu, 02 Feb 2023 09:46:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007HQ-Co for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvW-0000gW-Hd for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:56 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvJ-004Q6t-8z; Thu, 02 Feb 2023 12:42:42 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 24/39] target/riscv: add zvknh cpu properties Date: Thu, 2 Feb 2023 12:42:15 +0000 Message-Id: <20230202124230.295997-25-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349332265100001 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 10 +++++++++- target/riscv/cpu.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0da04d0be1..a78d9ae120 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb), + ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), + ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), @@ -798,13 +800,19 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) * In principle zve*{x,d} would also suffice here, were they suppo= rted * in qemu */ - if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns) && + if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns || cpu->cfg.ext_zvknh= a) && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v= )) { error_setg( errp, "Vector crypto extensions require V or Zve* extensio= ns"); return; } =20 + if (cpu->cfg.ext_zvknhb && !(cpu->cfg.ext_zve64f || cpu->cfg.ext_v= )) { + error_setg(errp, + "Zvknhb extension requires V or Zve64f extensions"); + return; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || cpu->cfg.ext_zhinxmin) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 56008ef9b9..ebee902806 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -462,6 +462,8 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zvkb; + bool ext_zvknha; + bool ext_zvknhb; bool ext_zvkns; bool ext_zmmul; bool ext_smaia; --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350560000415.26193925382086; Thu, 2 Feb 2023 07:09:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqw-0005QD-M5; Thu, 02 Feb 2023 09:46:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007HP-A2 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvW-0000gb-PK for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:57 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvJ-004Q6t-GU; Thu, 02 Feb 2023 12:42:42 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:16 +0000 Message-Id: <20230202124230.295997-26-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350561252100003 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 45 ++++++++++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 80 +++++++++++++++++++++ 5 files changed, 131 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 312f59bb38..6e7777c879 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1192,3 +1192,5 @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1eed0a6b26..57fbd63d91 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -921,3 +921,6 @@ vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 = @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvknh vector crypto extension *** +vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvknh.c.inc b/target/riscv/ins= n_trans/trans_rvzvknh.c.inc new file mode 100644 index 0000000000..ff30400100 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvknh.c.inc @@ -0,0 +1,45 @@ +#define GEN_VV_UNMASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr * a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data =3D 0; \ + TCGLabel *over =3D gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ + gen_helper_##NAME); \ + \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool vsha_check_sew(DisasContext *s) +{ + return (s->cfg_ptr->ext_zvknha =3D=3D true && s->sew =3D=3D MO_32) || + (s->cfg_ptr->ext_zvknhb =3D=3D true && + (s->sew =3D=3D MO_32 || s->sew =3D=3D MO_64)); +} + +static bool vsha_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + vsha_check_sew(s) && + s->vstart % 4 =3D=3D 0 && + s->lmul >=3D 0; +} + +GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8d39743de2..924a89de9f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1065,6 +1065,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_rvzvkb.c.inc" #include "insn_trans/trans_rvzvkns.c.inc" +#include "insn_trans/trans_rvzvknh.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 50207b4ff0..af596cce09 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -461,3 +461,83 @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr,= uint32_t uimm, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); } + +static inline uint32_t sig0_sha256(uint32_t x) +{ + return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3); +} + +static inline uint32_t sig1_sha256(uint32_t x) +{ + return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); +} + +static inline uint64_t sig0_sha512(uint64_t x) +{ + return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); +} + +static inline uint64_t sig1_sha512(uint64_t x) +{ + return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); +} + +static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) +{ + uint32_t res[4]; + res[0] =3D sig1_sha256(vs2[H4(2)]) + vs1[H4(1)] + sig0_sha256(vd[H4(1)= ]) + + vd[H4(0)]; + res[1] =3D sig1_sha256(vs2[H4(3)]) + vs1[H4(2)] + sig0_sha256(vd[H4(2)= ]) + + vd[H4(1)]; + res[2] =3D sig1_sha256(res[0]) + vs1[H4(3)] + sig0_sha256(vd[H4(3)]) + + vd[H4(2)]; + res[3] =3D sig1_sha256(res[1]) + vs2[H4(0)] + sig0_sha256(vs1[H4(0)]) + + vd[H4(3)]; + vd[H4(3)] =3D res[3]; + vd[H4(2)] =3D res[2]; + vd[H4(1)] =3D res[1]; + vd[H4(0)] =3D res[0]; +} + +static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2) +{ + uint64_t res[4]; + res[0] =3D sig1_sha512(vs2[2]) + vs1[1] + sig0_sha512(vd[1]) + vd[0]; + res[1] =3D sig1_sha512(vs2[3]) + vs1[2] + sig0_sha512(vd[2]) + vd[1]; + res[2] =3D sig1_sha512(res[0]) + vs1[3] + sig0_sha512(vd[3]) + vd[2]; + res[3] =3D sig1_sha512(res[1]) + vs2[0] + sig0_sha512(vs1[0]) + vd[3]; + vd[3] =3D res[3]; + vd[2] =3D res[2]; + vd[1] =3D res[1]; + vd[0] =3D res[0]; +} + +void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D 0; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + if (env->vl % 4 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_32) { + esz =3D 4; + vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * = 4, + ((uint32_t *)vs2) + i * 4); + } else { + /* If not 32 then SEW should be 64 */ + esz =3D 8; + vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * = 4, + ((uint64_t *)vs2) + i * 4); + } + } + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350442164641.0863694740771; Thu, 2 Feb 2023 07:07:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaru-0006tT-2q; Thu, 02 Feb 2023 09:47:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007IM-KB for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:59 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0000gj-9L for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvJ-004Q6t-Ot; Thu, 02 Feb 2023 12:42:42 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:17 +0000 Message-Id: <20230202124230.295997-27-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350444972100007 Content-Type: text/plain; charset="utf-8" Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 2 + target/riscv/vcrypto_helper.c | 153 ++++++++++++++++++++ 4 files changed, 159 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6e7777c879..911270c387 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1194,3 +1194,5 @@ DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i3= 2) DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) =20 DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 57fbd63d91..2387bc179c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -924,3 +924,5 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 = @r_vm_1 =20 # *** RV64 Zvknh vector crypto extension *** vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvknh.c.inc b/target/riscv/ins= n_trans/trans_rvzvknh.c.inc index ff30400100..4d4d26eae5 100644 --- a/target/riscv/insn_trans/trans_rvzvknh.c.inc +++ b/target/riscv/insn_trans/trans_rvzvknh.c.inc @@ -43,3 +43,5 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a) } =20 GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check) +GEN_VV_UNMASKED_TRANS(vsha2cl_vv, vsha_check) +GEN_VV_UNMASKED_TRANS(vsha2ch_vv, vsha_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index af596cce09..b73581641a 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -541,3 +541,156 @@ void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +static inline uint64_t sum0_64(uint64_t x) +{ + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); +} + +static inline uint32_t sum0_32(uint32_t x) +{ + return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22); +} + +static inline uint64_t sum1_64(uint64_t x) +{ + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); +} + +static inline uint32_t sum1_32(uint32_t x) +{ + return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25); +} + +#define ch(x, y, z) ((x & y) ^ ((~x) & z)) + +#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1) +{ + uint64_t a =3D vs2[3], b =3D vs2[2], e =3D vs2[1], f =3D vs2[0]; + uint64_t c =3D vd[3], d =3D vd[2], g =3D vd[1], h =3D vd[0]; + uint64_t W0 =3D vs1[0], W1 =3D vs1[1]; + uint64_t T1 =3D h + sum1_64(e) + ch(e, f, g) + W0; + uint64_t T2 =3D sum0_64(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_64(e) + ch(e, f, g) + W1; + T2 =3D sum0_64(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[0] =3D f; + vd[1] =3D e; + vd[2] =3D b; + vd[3] =3D a; +} + +static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1) +{ + uint32_t a =3D vs2[H4(3)], b =3D vs2[H4(2)], e =3D vs2[H4(1)], f =3D v= s2[H4(0)]; + uint32_t c =3D vd[H4(3)], d =3D vd[H4(2)], g =3D vd[H4(1)], h =3D vd[H= 4(0)]; + uint32_t W0 =3D vs1[H4(0)], W1 =3D vs1[H4(1)]; + uint32_t T1 =3D h + sum1_32(e) + ch(e, f, g) + W0; + uint32_t T2 =3D sum0_32(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_32(e) + ch(e, f, g) + W1; + T2 =3D sum0_32(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[H4(0)] =3D f; + vd[H4(1)] =3D e; + vd[H4(2)] =3D b; + vd[H4(3)] =3D a; + +} + +void HELPER(vsha2ch_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D 0; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + if (env->vl % 4 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_64) { + esz =3D 8; + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + ((uint64_t *)vs1) + 4 * i + 2); + } else { + esz =3D 4; + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + ((uint32_t *)vs1) + 4 * i + 2); + } + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D 0; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + if (env->vl % 4 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_64) { + esz =3D 8; + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + (((uint64_t *)vs1) + 4 * i)); + } else { + esz =3D 4; + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + (((uint32_t *)vs1) + 4 * i)); + } + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350393032458.21929519161176; Thu, 2 Feb 2023 07:06:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaqx-0005RR-9A; Thu, 02 Feb 2023 09:46:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007Hb-DK for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0000gl-9c for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvK-004Q6t-0r; Thu, 02 Feb 2023 12:42:42 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 27/39] target/riscv: expose zvknh cpu properties Date: Thu, 2 Feb 2023 12:42:18 +0000 Message-Id: <20230202124230.295997-28-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350394941100001 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a78d9ae120..5076699226 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1092,6 +1092,8 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), =20 DEFINE_PROP_BOOL("zvkb", RISCVCPU, cfg.ext_zvkb, false), + DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), + DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), =20 /* Vendor-specific custom extensions */ --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349389799851.5300969804211; Thu, 2 Feb 2023 06:49:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarr-0006l3-UX; Thu, 02 Feb 2023 09:47:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007I8-Ia for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:59 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0000gr-Cf for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvK-004Q6t-92; Thu, 02 Feb 2023 12:42:43 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 28/39] target/riscv: add zvksh cpu property Date: Thu, 2 Feb 2023 12:42:19 +0000 Message-Id: <20230202124230.295997-29-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349391395100007 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 4 +++- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5076699226..9a412d9d53 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -104,6 +104,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), + ISA_EXT_DATA_ENTRY(zvksh, true, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), @@ -800,7 +801,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) * In principle zve*{x,d} would also suffice here, were they suppo= rted * in qemu */ - if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns || cpu->cfg.ext_zvknh= a) && + if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns || cpu->cfg.ext_zvknh= a || + cpu->cfg.ext_zvksh) && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v= )) { error_setg( errp, "Vector crypto extensions require V or Zve* extensio= ns"); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ebee902806..92624bfc57 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -465,6 +465,7 @@ struct RISCVCPUConfig { bool ext_zvknha; bool ext_zvknhb; bool ext_zvkns; + bool ext_zvksh; bool ext_zmmul; bool ext_smaia; bool ext_ssaia; --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167534924392422.972111647971246; Thu, 2 Feb 2023 06:47:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNar2-0005Th-UN; Thu, 02 Feb 2023 09:46:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvb-0007Ji-0c for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:59 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0000gx-RT for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvK-004Q6t-HL; Thu, 02 Feb 2023 12:42:43 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:20 +0000 Message-Id: <20230202124230.295997-30-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349245627100005 Content-Type: text/plain; charset="utf-8" Co-authored-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvksh.c.inc | 12 ++++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 43 +++++++++++++++++++++ 5 files changed, 61 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 911270c387..36e0d8eff3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1196,3 +1196,5 @@ DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i3= 2) DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2387bc179c..671614e354 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -926,3 +926,6 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 = @r_vm_1 vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvksh vector crypto extensions *** +vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvksh.c.inc b/target/riscv/ins= n_trans/trans_rvzvksh.c.inc new file mode 100644 index 0000000000..ad7105b3ed --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvksh.c.inc @@ -0,0 +1,12 @@ +static inline bool vsm3_check(DisasContext *s) +{ + return s->cfg_ptr->ext_zvksh =3D=3D true && vext_check_isa_ill(s) && + s->vstart % 8 =3D=3D 0 && s->sew =3D=3D MO_32; +} + +static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm= ); +} + +GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 924a89de9f..9ca2cec23a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1066,6 +1066,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzvkb.c.inc" #include "insn_trans/trans_rvzvkns.c.inc" #include "insn_trans/trans_rvzvknh.c.inc" +#include "insn_trans/trans_rvzvksh.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index b73581641a..4dd5920aa4 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -694,3 +694,46 @@ void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2= , CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +static inline uint32_t p1(uint32_t x) +{ + return (x) ^ rol32((x), 15) ^ rol32((x), 23); +} + +static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3, + uint32_t m13, uint32_t m6) +{ + return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6; +} + +void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs1 =3D vs1_vptr; + uint32_t *vs2 =3D vs2_vptr; + + if (env->vl % 8 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + uint32_t w[24]; + for (int j =3D 0; j < 8; j++) { + w[j] =3D bswap32(vs1[H4((i * 8) + j)]); + w[j + 8] =3D bswap32(vs2[H4((i * 8) + j)]); + } + for (int j =3D 0; j < 8; j++) { + w[j + 16] =3D + zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]); + } + for (int j =3D 0; j < 8; j++) { + vd[(i * 8) + j] =3D bswap32(w[H4(j + 16)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350511178935.091199427147; Thu, 2 Feb 2023 07:08:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNasu-0000L6-1d; Thu, 02 Feb 2023 09:48:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2X-0002rU-7v for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:09 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2V-0003b7-HU for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:08 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvK-004Q6t-Pu; Thu, 02 Feb 2023 12:42:43 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 30/39] target/riscv: Add vsm3c.vi decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:21 +0000 Message-Id: <20230202124230.295997-31-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350512694100003 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvksh.c.inc | 8 ++ target/riscv/vcrypto_helper.c | 90 +++++++++++++++++++++ 4 files changed, 100 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 36e0d8eff3..a82103ead9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1198,3 +1198,4 @@ DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i3= 2) DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) =20 DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 671614e354..4a50114e92 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -929,3 +929,4 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 = @r_vm_1 =20 # *** RV64 Zvksh vector crypto extensions *** vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvksh.c.inc b/target/riscv/ins= n_trans/trans_rvzvksh.c.inc index ad7105b3ed..f11dfb24ff 100644 --- a/target/riscv/insn_trans/trans_rvzvksh.c.inc +++ b/target/riscv/insn_trans/trans_rvzvksh.c.inc @@ -9,4 +9,12 @@ static inline bool vsm3me_check(DisasContext *s, arg_rmrr = *a) return vsm3_check(s) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm= ); } =20 + +static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s) && a->rs1 < 32 && + vext_check_ss(s, a->rd, a->rs2, a->vm); +} + GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check) +GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 4dd5920aa4..478e652c9b 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -737,3 +737,93 @@ void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, = void *vs2_vptr, vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +}; +static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (x & z) | (y & z); +}; +static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <=3D 15) ? ff1(x, y, z) : ff2(x, y, z); +}; +static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +}; +static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (~x & z); +}; +static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <=3D 15) ? gg1(x, y, z) : gg2(x, y, z); +}; +static inline uint32_t t_j(uint32_t j) +{ + return (j <=3D 15) ? 0x79cc4519 : 0x7a879d8a; +}; +static inline uint32_t p_0(uint32_t x) +{ + return x ^ rol32(x, 9) ^ rol32(x, 17); +}; +static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm) +{ + uint32_t x0, x1; + uint32_t j; + uint32_t ss1, ss2, tt1, tt2; + x0 =3D vs2[0] ^ vs2[4]; + x1 =3D vs2[1] ^ vs2[5]; + j =3D 2 * uimm; + ss1 =3D rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7); + ss2 =3D ss1 ^ rol32(vs1[0], 12); + tt1 =3D ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0; + tt2 =3D gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0]; + vs1[3] =3D vs1[2]; + vd[3] =3D rol32(vs1[1], 9); + vs1[1] =3D vs1[0]; + vd[1] =3D tt1; + vs1[7] =3D vs1[6]; + vd[7] =3D rol32(vs1[5], 19); + vs1[5] =3D vs1[4]; + vd[5] =3D p_0(tt2); + j =3D 2 * uimm + 1; + ss1 =3D rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7); + ss2 =3D ss1 ^ rol32(vd[1], 12); + tt1 =3D ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1; + tt2 =3D gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1]; + vd[2] =3D rol32(vs1[1], 9); + vd[0] =3D tt1; + vd[6] =3D rol32(vs1[5], 19); + vd[4] =3D p_0(tt2); +} +void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t v1[8], v2[8], v3[8]; + + if (env->vl % 8 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + for (int k =3D 0; k < 8; k++) { + v2[k] =3D bswap32(vd[H4(i * 8 + k)]); + v3[k] =3D bswap32(vs2[H4(i * 8 + k)]); + } + sm3c(v1, v2, v3, uimm); + for (int k =3D 0; k < 8; k++) { + vd[i * 8 + k] =3D bswap32(v1[H4(k)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675352006781652.976089049851; Thu, 2 Feb 2023 07:33:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarS-0005yV-IK; Thu, 02 Feb 2023 09:46:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2e-0002sf-9H for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:16 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2c-0003cq-PR for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:15 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvL-004Q6t-2O; Thu, 02 Feb 2023 12:42:43 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 31/39] target/riscv: expose zvksh cpu property Date: Thu, 2 Feb 2023 12:42:22 +0000 Message-Id: <20230202124230.295997-32-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675352007911100002 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9a412d9d53..a3b08e9d27 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1097,6 +1097,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), + DEFINE_PROP_BOOL("zvksh", RISCVCPU, cfg.ext_zvksh, false), =20 /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350693932176.60707816454055; Thu, 2 Feb 2023 07:11:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarw-00075q-Lv; Thu, 02 Feb 2023 09:47:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2l-0002tt-Hl for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:23 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2j-0003eC-NG for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:22 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvL-004Q6t-Az; Thu, 02 Feb 2023 12:42:44 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 32/39] target/riscv: add zvkg cpu property Date: Thu, 2 Feb 2023 12:42:23 +0000 Message-Id: <20230202124230.295997-33-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350695751100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a3b08e9d27..6fded328f8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb), + ISA_EXT_DATA_ENTRY(zvkg, true, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), @@ -802,7 +803,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) * in qemu */ if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns || cpu->cfg.ext_zvknh= a || - cpu->cfg.ext_zvksh) && + cpu->cfg.ext_zvksh || cpu->cfg.ext_zvkg) && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v= )) { error_setg( errp, "Vector crypto extensions require V or Zve* extensio= ns"); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 92624bfc57..b3b1174d74 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -462,6 +462,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zvkb; + bool ext_zvkg; bool ext_zvknha; bool ext_zvknhb; bool ext_zvkns; --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675352188301136.80398133609594; Thu, 2 Feb 2023 07:36:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarq-0006Yn-7y; Thu, 02 Feb 2023 09:47:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2D-0002cO-43 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:49:50 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2A-0003LO-V0 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:49:48 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvM-004Q6t-2g; Thu, 02 Feb 2023 12:42:44 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:24 +0000 Message-Id: <20230202124230.295997-34-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675352189193100001 Content-Type: text/plain; charset="utf-8" Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkg.c.inc | 9 +++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 45 ++++++++++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a82103ead9..6272294d50 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1199,3 +1199,5 @@ DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i3= 2) =20 DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vghmac_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4a50114e92..ff044f8288 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -930,3 +930,6 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 = @r_vm_1 # *** RV64 Zvksh vector crypto extensions *** vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvkg vector crypto extension *** +vghmac_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkg.c.inc b/target/riscv/insn= _trans/trans_rvzvkg.c.inc new file mode 100644 index 0000000000..aa2004fb44 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvkg.c.inc @@ -0,0 +1,9 @@ +static bool vghmac_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + s->cfg_ptr->ext_zvkg =3D=3D true && + s->vstart % 4 =3D=3D 0 && + s->sew =3D=3D MO_32; +} + +GEN_VV_UNMASKED_TRANS(vghmac_vv, vghmac_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9ca2cec23a..0bc1c9db65 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1067,6 +1067,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzvkns.c.inc" #include "insn_trans/trans_rvzvknh.c.inc" #include "insn_trans/trans_rvzvksh.c.inc" +#include "insn_trans/trans_rvzvkg.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 478e652c9b..a309ac3f03 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -827,3 +827,48 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, u= int32_t uimm, vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +void HELPER(vghmac_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint64_t *vd =3D vd_vptr; + uint64_t *vs1 =3D vs1_vptr; + uint64_t *vs2 =3D vs2_vptr; + uint32_t vta =3D vext_vta(desc); + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + + if (env->vl % 4 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + __uint128_t Y =3D reverse_bits_byte_8(vd[i * 2 + 0]) | + ((__uint128_t)reverse_bits_byte_8(vd[i * 2 + 1]) <= < 64); + __uint128_t H =3D reverse_bits_byte_8(vs1[i * 2 + 0]) | + ((__uint128_t)reverse_bits_byte_8(vs1[i * 2 + 1]) = << 64); + __uint128_t X =3D vs2[i * 2 + 0] | ((__uint128_t)vs2[i * 2 + 1] <<= 64); + __uint128_t Z =3D 0; + + for (uint j =3D 0; j < 128; j++) { + if ((Y >> j) & 1) { + Z ^=3D H; + } + bool reduce =3D ((H >> 127) & 1); + H =3D H << 1; + if (reduce) { + H ^=3D 0x87; + } + } + + Z =3D reverse_bits_byte_8(Z & UINT64_MAX) | + ((__uint128_t)reverse_bits_byte_8((Z >> 64) & UINT64_MAX) << 6= 4); + + Z =3D Z ^ X; + + vd[i * 2 + 0] =3D Z & UINT64_MAX; + vd[i * 2 + 1] =3D (Z >> 64) & UINT64_MAX; + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart =3D 0; +} --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349340554212.5220108611154; Thu, 2 Feb 2023 06:49:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarp-0006Vs-Kt; Thu, 02 Feb 2023 09:47:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2P-0002oo-Sv for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:01 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2O-0003Nx-5e for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:01 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvM-004Q6t-BU; Thu, 02 Feb 2023 12:42:45 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 34/39] target/riscv: expose zvkg cpu property Date: Thu, 2 Feb 2023 12:42:25 +0000 Message-Id: <20230202124230.295997-35-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349342321100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6fded328f8..48701e118f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1095,6 +1095,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), =20 DEFINE_PROP_BOOL("zvkb", RISCVCPU, cfg.ext_zvkb, false), + DEFINE_PROP_BOOL("zvkg", RISCVCPU, cfg.ext_zvkg, false), DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675351718079269.5808042782122; Thu, 2 Feb 2023 07:28:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarr-0006fQ-Br; Thu, 02 Feb 2023 09:47:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ32-0002vo-G8 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:40 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2y-0003jZ-CY for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:37 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvM-004Q6t-LH; Thu, 02 Feb 2023 12:42:45 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Max Chou Subject: [PATCH 35/39] crypto: Move SM4_SBOXWORD from target/riscv Date: Thu, 2 Feb 2023 12:42:26 +0000 Message-Id: <20230202124230.295997-36-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675351720382100002 Content-Type: text/plain; charset="utf-8" From: Max Chou - Share SM4_SBOXWORD between target/riscv and target/arm. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- include/crypto/sm4.h | 7 +++++++ target/arm/crypto_helper.c | 10 ++-------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index 9bd3ebc62e..33478562a4 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -1,6 +1,13 @@ #ifndef QEMU_SM4_H #define QEMU_SM4_H =20 +#define SM4_SBOXWORD(WORD) ( \ + sm4_sbox[((WORD) >> 24) & 0xff] << 24 | \ + sm4_sbox[((WORD) >> 16) & 0xff] << 16 | \ + sm4_sbox[((WORD) >> 8) & 0xff] << 8 | \ + sm4_sbox[((WORD) >> 0) & 0xff] << 0 \ +) + extern const uint8_t sm4_sbox[256]; =20 #endif diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index d28690321f..4e97af9879 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -707,10 +707,7 @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn,= uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(n, i); =20 - t =3D sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t =3D SM4_SBOXWORD(t); =20 CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18= ) ^ rol32(t, 24); @@ -744,10 +741,7 @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *= rn, uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(m, i); =20 - t =3D sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t =3D SM4_SBOXWORD(t); =20 CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 13) ^ rol32(t, 23); } --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675352189569613.0853335244775; Thu, 2 Feb 2023 07:36:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarq-0006aN-C7; Thu, 02 Feb 2023 09:47:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2J-0002lp-35 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:49:55 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2H-0003NT-Lq for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:49:54 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvM-004Q6t-U4; Thu, 02 Feb 2023 12:42:45 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Max Chou Subject: [PATCH 36/39] crypto: Add SM4 constant parameter CK. Date: Thu, 2 Feb 2023 12:42:27 +0000 Message-Id: <20230202124230.295997-37-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675352191196100007 Content-Type: text/plain; charset="utf-8" From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++++++++++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c7..2987306cf7 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3 +47,13 @@ uint8_t const sm4_sbox[] =3D { 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48, }; =20 +uint32_t const sm4_ck[] =3D { + 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269, + 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9, + 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249, + 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9, + 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229, + 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299, + 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209, + 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 +}; diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index 33478562a4..d0df6e473c 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -9,5 +9,6 @@ ) =20 extern const uint8_t sm4_sbox[256]; +extern const uint32_t sm4_ck[32]; =20 #endif --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675349332018729.2247852055318; Thu, 2 Feb 2023 06:48:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarv-00072N-EP; Thu, 02 Feb 2023 09:47:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2s-0002us-Ou for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:30 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ2r-0003f8-2T for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:50:30 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvN-004Q6t-Df; Thu, 02 Feb 2023 12:42:46 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Max Chou Subject: [PATCH 37/39] target/riscv: Add zvksed cfg property Date: Thu, 2 Feb 2023 12:42:28 +0000 Message-Id: <20230202124230.295997-38-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349332267100002 Content-Type: text/plain; charset="utf-8" From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 48701e118f..0fa7049c3b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -105,6 +105,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), + ISA_EXT_DATA_ENTRY(zvksed, true, PRIV_VERSION_1_12_0, ext_zvksed), ISA_EXT_DATA_ENTRY(zvksh, true, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), @@ -803,7 +804,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) * in qemu */ if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns || cpu->cfg.ext_zvknh= a || - cpu->cfg.ext_zvksh || cpu->cfg.ext_zvkg) && + cpu->cfg.ext_zvksh || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkse= d) && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v= )) { error_setg( errp, "Vector crypto extensions require V or Zve* extensio= ns"); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b3b1174d74..89e9fd61da 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -466,6 +466,7 @@ struct RISCVCPUConfig { bool ext_zvknha; bool ext_zvknhb; bool ext_zvkns; + bool ext_zvksed; bool ext_zvksh; bool ext_zmmul; bool ext_smaia; --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350440297123.80704472348407; Thu, 2 Feb 2023 07:07:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarx-00078d-Ch; Thu, 02 Feb 2023 09:47:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ24-0002aF-FB for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:49:46 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ22-0003KZ-E0 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:49:40 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvN-004Q6t-Ln; Thu, 02 Feb 2023 12:42:46 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Max Chou Subject: [PATCH 38/39] target/riscv: Add Zvksed support Date: Thu, 2 Feb 2023 12:42:29 +0000 Message-Id: <20230202124230.295997-39-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350442485100003 Content-Type: text/plain; charset="utf-8" From: Max Chou - add vsm4k, vsm4r instructions Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hunter@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor style changes] --- target/riscv/crypto_helper.c | 1 + target/riscv/helper.h | 4 + target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvzvksed.c.inc | 35 +++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 139 +++++++++++++++++++ 6 files changed, 185 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index 2ef30281b1..760ce22570 100644 --- a/target/riscv/crypto_helper.c +++ b/target/riscv/crypto_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "crypto/aes.h" #include "crypto/sm4.h" +#include "vector_internals.h" =20 #define AES_XTIME(a) \ ((a << 1) ^ ((a & 0x80) ? 0x1b : 0)) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6272294d50..07fad2568c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1201,3 +1201,7 @@ DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) =20 DEF_HELPER_5(vghmac_vv, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ff044f8288..3e83884f43 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -933,3 +933,8 @@ vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 = @r_vm_1 =20 # *** RV64 Zvkg vector crypto extension *** vghmac_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvksed Standart Extension *** +vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 +vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvksed.c.inc b/target/riscv/in= sn_trans/trans_rvzvksed.c.inc new file mode 100644 index 0000000000..a30e0862e0 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvksed.c.inc @@ -0,0 +1,35 @@ +#define ZVKSED_EGS 4 + +static bool zvksed_check(DisasContext *s) +{ + return s->cfg_ptr->ext_zvksed =3D=3D true && vext_check_isa_ill(s) && + s->vstart % ZVKSED_EGS =3D=3D 0 && s->sew =3D=3D MO_32; +} + +static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + a->rs1 >=3D 0 && a->rs1 <=3D 7; +} + +GEN_VI_UNMASKED_TRANS(vsm4k_vi, vsm4k_vi_check) + +static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vv, vsm4r_vv_check) + +static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && + require_align(a->rd, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vs, vsm4r_vs_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0bc1c9db65..2ffb1827c5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1068,6 +1068,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzvknh.c.inc" #include "insn_trans/trans_rvzvksh.c.inc" #include "insn_trans/trans_rvzvkg.c.inc" +#include "insn_trans/trans_rvzvksed.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index a309ac3f03..fd9fc3c6d7 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -4,6 +4,7 @@ #include "qemu/bswap.h" #include "cpu.h" #include "crypto/aes.h" +#include "crypto/sm4.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -872,3 +873,141 @@ void HELPER(vghmac_vv)(void *vd_vptr, void *vs1_vptr,= void *vs2_vptr, vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); env->vstart =3D 0; } + +void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uimm5, + CPURISCVState *env, uint32_t desc) +{ + const uint32_t egs =3D 4; + uint32_t rnd =3D uimm5; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + if (env->vl % egs !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D vstart; j < vend; ++j) { + rk[j - vstart] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D 0; j < egs; ++j) { + tmp[j] =3D rk[j]; + } + + for (uint32_t j =3D 0; j < egs; ++j) { + uint32_t b, s; + b =3D tmp[j + 1] ^ tmp[j + 2] ^ tmp[j + 3] ^ sm4_ck[rnd * 4 + = j]; + + s =3D SM4_SBOXWORD(b); + + tmp[j + 4] =3D tmp[j] ^ (s ^ rol32(s, 13) ^ rol32(s, 23)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} + +static void do_sm4_round(uint32_t *rk, uint32_t *buf) +{ + const uint32_t egs =3D 4; + uint32_t s, b; + + for (uint32_t j =3D egs; j < egs * 2; ++j) { + b =3D buf[j - 3] ^ buf[j - 2] ^ buf[j - 1] ^ rk[j - 4]; + + s =3D SM4_SBOXWORD(b); + + buf[j] =3D buf[j - 4] ^ (s ^ rol32(s, 2) ^ rol32(s, 10) ^ + rol32(s, 18) ^ rol32(s, 24)); + } +} + +void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVState *env, uint32_t de= sc) +{ + const uint32_t egs =3D 4; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + if (env->vl % egs !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D vstart; j < vend; ++j) { + rk[j - vstart] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + tmp[j - vstart] =3D *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} + +void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVState *env, uint32_t de= sc) +{ + const uint32_t egs =3D 4; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + if (env->vl % egs !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D 0; j < egs; ++j) { + rk[j] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + tmp[j - vstart] =3D *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} --=20 2.39.1 From nobody Fri Apr 26 03:46:44 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350522681219.10036848809386; Thu, 2 Feb 2023 07:08:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNarN-0005pY-Nx; Thu, 02 Feb 2023 09:46:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ1w-0002ZR-28 for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:49:46 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNZ1t-0003JX-Va for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:49:31 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvN-004Q6t-VZ; Thu, 02 Feb 2023 12:42:46 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Max Chou Subject: [PATCH 39/39] target/riscv: Expose Zvksed property Date: Thu, 2 Feb 2023 12:42:30 +0000 Message-Id: <20230202124230.295997-40-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350524455100003 Content-Type: text/plain; charset="utf-8" From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0fa7049c3b..a4e8347d5f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1100,6 +1100,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), + DEFINE_PROP_BOOL("zvksed", RISCVCPU, cfg.ext_zvksed, false), DEFINE_PROP_BOOL("zvksh", RISCVCPU, cfg.ext_zvksh, false), =20 /* Vendor-specific custom extensions */ --=20 2.39.1