From nobody Tue May 13 11:42:40 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675350442164641.0863694740771; Thu, 2 Feb 2023 07:07:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNaru-0006tT-2q; Thu, 02 Feb 2023 09:47:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYva-0007IM-KB for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:59 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0000gj-9L for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvJ-004Q6t-Ot; Thu, 02 Feb 2023 12:42:42 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:17 +0000 Message-Id: <20230202124230.295997-27-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675350444972100007 Content-Type: text/plain; charset="utf-8" Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 2 + target/riscv/vcrypto_helper.c | 153 ++++++++++++++++++++ 4 files changed, 159 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6e7777c879..911270c387 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1194,3 +1194,5 @@ DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i3= 2) DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) =20 DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 57fbd63d91..2387bc179c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -924,3 +924,5 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 = @r_vm_1 =20 # *** RV64 Zvknh vector crypto extension *** vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvknh.c.inc b/target/riscv/ins= n_trans/trans_rvzvknh.c.inc index ff30400100..4d4d26eae5 100644 --- a/target/riscv/insn_trans/trans_rvzvknh.c.inc +++ b/target/riscv/insn_trans/trans_rvzvknh.c.inc @@ -43,3 +43,5 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a) } =20 GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check) +GEN_VV_UNMASKED_TRANS(vsha2cl_vv, vsha_check) +GEN_VV_UNMASKED_TRANS(vsha2ch_vv, vsha_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index af596cce09..b73581641a 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -541,3 +541,156 @@ void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +static inline uint64_t sum0_64(uint64_t x) +{ + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); +} + +static inline uint32_t sum0_32(uint32_t x) +{ + return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22); +} + +static inline uint64_t sum1_64(uint64_t x) +{ + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); +} + +static inline uint32_t sum1_32(uint32_t x) +{ + return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25); +} + +#define ch(x, y, z) ((x & y) ^ ((~x) & z)) + +#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1) +{ + uint64_t a =3D vs2[3], b =3D vs2[2], e =3D vs2[1], f =3D vs2[0]; + uint64_t c =3D vd[3], d =3D vd[2], g =3D vd[1], h =3D vd[0]; + uint64_t W0 =3D vs1[0], W1 =3D vs1[1]; + uint64_t T1 =3D h + sum1_64(e) + ch(e, f, g) + W0; + uint64_t T2 =3D sum0_64(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_64(e) + ch(e, f, g) + W1; + T2 =3D sum0_64(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[0] =3D f; + vd[1] =3D e; + vd[2] =3D b; + vd[3] =3D a; +} + +static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1) +{ + uint32_t a =3D vs2[H4(3)], b =3D vs2[H4(2)], e =3D vs2[H4(1)], f =3D v= s2[H4(0)]; + uint32_t c =3D vd[H4(3)], d =3D vd[H4(2)], g =3D vd[H4(1)], h =3D vd[H= 4(0)]; + uint32_t W0 =3D vs1[H4(0)], W1 =3D vs1[H4(1)]; + uint32_t T1 =3D h + sum1_32(e) + ch(e, f, g) + W0; + uint32_t T2 =3D sum0_32(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_32(e) + ch(e, f, g) + W1; + T2 =3D sum0_32(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[H4(0)] =3D f; + vd[H4(1)] =3D e; + vd[H4(2)] =3D b; + vd[H4(3)] =3D a; + +} + +void HELPER(vsha2ch_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D 0; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + if (env->vl % 4 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_64) { + esz =3D 8; + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + ((uint64_t *)vs1) + 4 * i + 2); + } else { + esz =3D 4; + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + ((uint32_t *)vs1) + 4 * i + 2); + } + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D 0; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + if (env->vl % 4 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_64) { + esz =3D 8; + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + (((uint64_t *)vs1) + 4 * i)); + } else { + esz =3D 4; + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + (((uint32_t *)vs1) + 4 * i)); + } + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.39.1