From nobody Tue May 13 11:49:26 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167534924392422.972111647971246; Thu, 2 Feb 2023 06:47:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNar2-0005Th-UN; Thu, 02 Feb 2023 09:46:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvb-0007Ji-0c for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:59 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNYvX-0000gx-RT for qemu-devel@nongnu.org; Thu, 02 Feb 2023 07:42:58 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvK-004Q6t-HL; Thu, 02 Feb 2023 12:42:43 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:20 +0000 Message-Id: <20230202124230.295997-30-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Feb 2023 09:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675349245627100005 Content-Type: text/plain; charset="utf-8" Co-authored-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvksh.c.inc | 12 ++++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 43 +++++++++++++++++++++ 5 files changed, 61 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 911270c387..36e0d8eff3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1196,3 +1196,5 @@ DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i3= 2) DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2387bc179c..671614e354 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -926,3 +926,6 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 = @r_vm_1 vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvksh vector crypto extensions *** +vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvksh.c.inc b/target/riscv/ins= n_trans/trans_rvzvksh.c.inc new file mode 100644 index 0000000000..ad7105b3ed --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvksh.c.inc @@ -0,0 +1,12 @@ +static inline bool vsm3_check(DisasContext *s) +{ + return s->cfg_ptr->ext_zvksh =3D=3D true && vext_check_isa_ill(s) && + s->vstart % 8 =3D=3D 0 && s->sew =3D=3D MO_32; +} + +static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm= ); +} + +GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 924a89de9f..9ca2cec23a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1066,6 +1066,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzvkb.c.inc" #include "insn_trans/trans_rvzvkns.c.inc" #include "insn_trans/trans_rvzvknh.c.inc" +#include "insn_trans/trans_rvzvksh.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index b73581641a..4dd5920aa4 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -694,3 +694,46 @@ void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2= , CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +static inline uint32_t p1(uint32_t x) +{ + return (x) ^ rol32((x), 15) ^ rol32((x), 23); +} + +static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3, + uint32_t m13, uint32_t m6) +{ + return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6; +} + +void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs1 =3D vs1_vptr; + uint32_t *vs2 =3D vs2_vptr; + + if (env->vl % 8 !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + uint32_t w[24]; + for (int j =3D 0; j < 8; j++) { + w[j] =3D bswap32(vs1[H4((i * 8) + j)]); + w[j + 8] =3D bswap32(vs2[H4((i * 8) + j)]); + } + for (int j =3D 0; j < 8; j++) { + w[j + 16] =3D + zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]); + } + for (int j =3D 0; j < 8; j++) { + vd[(i * 8) + j] =3D bswap32(w[H4(j + 16)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.39.1