From nobody Fri Mar 29 04:58:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675346047; cv=none; d=zohomail.com; s=zohoarc; b=M7qBrxD2TuNOx1moN86o0X7zSGbuD5eS6IuGdSRWtg0xwl9GNmMYFz3Nb6Lf+/7MyqgwVNpi2idjKtrz88G//3xdfVyJHvFwsjT1PV01J04UdlQjJJRggoNZnDZicsfH6IM5nRYXbg/HNDNHuxS4xo0+/auLAzDPkHZzCJyinv4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675346047; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=l8MFiuXQ/g3MbPgHOjlwsj1LmKvLQxTFmOdqR/jzwkI=; b=kXf8Bp9ZaZ9W1hoME5kwRYDmjoVEKwHKERr2bVYNtCiTDILKpumkwQ3Npg08Fg0GmOUCjbR5NKI7iGrPiErvmVvFtmg+XR32mRdWSCVCYfO/C2zoJ0y45lBUJvHpIul1SznVAQVOsa3SEc7ht/Vun0fMaf3ANQ15AyZmPiGg0XM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675346047508351.66550679789304; Thu, 2 Feb 2023 05:54:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNa1k-0001Zv-Jf; Thu, 02 Feb 2023 08:53:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNa1d-0001WW-3H for qemu-devel@nongnu.org; Thu, 02 Feb 2023 08:53:17 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNa1Z-0007Xb-SX for qemu-devel@nongnu.org; Thu, 02 Feb 2023 08:53:16 -0500 Received: by mail-ot1-x341.google.com with SMTP id p24-20020a056830131800b0068d4b30536aso467298otq.9 for ; Thu, 02 Feb 2023 05:53:08 -0800 (PST) Received: from grind.. ([177.102.69.207]) by smtp.gmail.com with ESMTPSA id 45-20020a9d0330000000b00684e55f4541sm6547416otv.70.2023.02.02.05.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:53:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l8MFiuXQ/g3MbPgHOjlwsj1LmKvLQxTFmOdqR/jzwkI=; b=K9ro37ipgBhTpYDCF3zGqueoYp/ImFhCS84j272QKIiRRtEsD161uXF/y8rD92RTFc gYmYOVwTpH5DGAMWpg/3NDZ85akD8qfC2aeNAqgpaagXCQO99uhhDWk1p56LorT3WxhV oIhLDFt/6tFwILTyWYet0Y95TFVj+O/rXWXqr7GGGrN7Cs5dBS2cDebDSw8nzTYw843Z SivxIDwBysQgVD5ftsFmKUWwDhjdfdZl+TSa+A3VapMrG17h57Xx6J0ckxrFAv1eK25p ws5eWJo9AdJ1C/Pdc5AIJxzJ4o56CAc1NqkAtGkawkFIR8mye2kFJn2tDVgVLCy82sE4 8V3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l8MFiuXQ/g3MbPgHOjlwsj1LmKvLQxTFmOdqR/jzwkI=; b=JLnHOJYCkSf8c8Zwlt56DF8D53pupthL/mylYsuX+kzGdk8Y85blKY+e3w222UABJ8 3AePcAEIghWOpf++dsQFjZFR2i0Yj8bvYqzcCU0TdP6sHnwNtXfgPrLRyWsOIF0kNvBr Lea8jiLJWLxo8waq5mPqetikVGoCRKmOHVfSYIPpQ/SS/i1/o8IanGbaumoWmbIuH+Ds oQ957SJFcnjzCfopvRPbrd1i0sZsXFF5R81Lr4jgWNU4nP926bYv88JP8XSoqBHV756E zDqbi1646IZFNP1wYs/14r/yXW4NK9Lq78pVeyKc55+Nn7U0y2f47sMEitokpI6EGxeu v0GQ== X-Gm-Message-State: AO0yUKXDfdHvoFfWJRE4XK0SzDxEqVec+QhaClvG2UErWLNJ8Zr5gIgQ gNEGItf3hU+5d8+i0joJz2X4KrZLiXOn+FwFDF0= X-Google-Smtp-Source: AK7set8FRhvdduGZgrbpT/Iag6OXRUvsPIZ1e48WBin6pP8H/Dmfmza/aF/cPmI9IcCATacZfkI8Ew== X-Received: by 2002:a9d:644e:0:b0:68b:d30e:7a9f with SMTP id m14-20020a9d644e000000b0068bd30e7a9fmr2709587otl.28.1675345987681; Thu, 02 Feb 2023 05:53:07 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel() Date: Thu, 2 Feb 2023 10:52:55 -0300 Message-Id: <20230202135257.1657482-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202135257.1657482-1-dbarboza@ventanamicro.com> References: <20230202135257.1657482-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1675346048760100001 Content-Type: text/plain; charset="utf-8" load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU guest happens to be running in a hypervisor that are using 64 bits to encode its address, kernel_entry can be padded with '1's and create problems [1]. Using a translate_fn() callback in load_elf_ram_sym() to filter the padding from the address doesn't work. A more detailed explanation can be found in [2]. The short version is that glue(load_elf, SZ), from include/hw/elf_ops.h, will calculate 'pentry' (mapped into the 'kernel_load_base' var in riscv_load_Kernel()) before using translate_fn(), and will not recalculate it after executing it. This means that the callback does not prevent the padding from kernel_load_base to appear. Let's instead use a kernel_low var to capture the 'lowaddr' value from load_elf_ram_sim(), and return it when we're dealing with 32 bit CPUs. [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html [2] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg00099.html Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 15 +++++++++++---- hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 3 ++- include/hw/riscv/boot.h | 1 + 8 files changed, 24 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c7e0e50bd8..5ec6d32165 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -174,11 +174,12 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, } =20 target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { const char *kernel_filename =3D machine->kernel_filename; - uint64_t kernel_load_base, kernel_entry; + uint64_t kernel_load_base, kernel_entry, kernel_low; =20 g_assert(kernel_filename !=3D NULL); =20 @@ -189,10 +190,16 @@ target_ulong riscv_load_kernel(MachineState *machine, * the (expected) load address load address. This allows kernels to ha= ve * separate SBI and ELF entry points (used by FreeBSD, for example). */ - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, - NULL, &kernel_load_base, NULL, NULL, 0, + if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, + &kernel_load_base, &kernel_low, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry =3D kernel_load_base; + + if (riscv_is_32bit(harts)) { + kernel_entry =3D kernel_low; + } + + return kernel_entry; } =20 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 2b91e49561..712625d2a4 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,7 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, NULL); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 353f030d80..7fe4fb5628 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[IBEX_DEV_RAM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..1a7d381514 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d3ab7a9cda..71be442a50 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,7 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, NULL); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index cc3f6dac17..1fa91167ab 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -305,7 +305,8 @@ static void spike_board_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, htif_symbol_callback); =20 if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a061151a6f..d0531cc641 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1277,7 +1277,8 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, NULL); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 511390f60e..6295316afb 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong firmware_end_addr, symbol_fn_t sym_cb); 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([177.102.69.207]) by smtp.gmail.com with ESMTPSA id 45-20020a9d0330000000b00684e55f4541sm6547416otv.70.2023.02.02.05.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:53:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hyw0kbB3HyL6dvLAEEgzaKLD1f2gu7L09y3BM2ynCAM=; b=D2OYufoXYLsqriW1X7f5mM/tmCYUdNYe7FM6BcuuHZH5bIAHrJmiDDd4Or8TYToTHy aawmRCLQHuqmBfBld0i3Dhbrc59+eS4nzFo1dN1BAADGkegzCPeKwjm1V2FVzBzoW7kE dXUfDKC9T9cHAaWC5u3rxTvbA1E0+GAhd+U8yyFLaSL+XW16im/lGHML5JC5J32e1ccI wqdXVgaDEmEmg5U2rMqXGf4B6h0Ru+L6Q8UT2y8TdlRPkTPNHmRxNjz4H6nySUCEYxTX PwenubWkEzUStTINoORux+l+B8aiRxd8JV4vQC7Z/EmqSckJi1C33+IGQCZglWNIXLs7 QkFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hyw0kbB3HyL6dvLAEEgzaKLD1f2gu7L09y3BM2ynCAM=; b=5CCt5oLC5E0x7aeAZi9UtR8zzX/HRaelHQt8r8dnjBFxsqZaN1T7+alv7OC6aeyP9Z KIGOnSKgnr7gS7PwPCMs355cNDr0XjZ7VTPUZfGkthqYuIZ7jOxr6z+zaQRT1+mpuhYG /FB+ePH7ST+kmzFrkaCqBuG3I4CbNqIPLFfIjHFa52BEL0qQ6bT9jqHGlUnXeaJ/d+OD QiCw1e+hHdch2IWi3k1HBKv7PUy8qDufNIByux9gAm6Efu4bFtS3zRvpe9bWYVLObVHl 35W6cPUdyzH7UjmpS37/HHumqv6iBJlQyyS632w0TtSnkoaD4v3NVdFbSXe8BRKC6nqQ KPLg== X-Gm-Message-State: AO0yUKWbRMq52xENCmB/qNgnDLPQgIRgcMhR/VMIRkrpl9Kt9DDakQ1o qpIsuMqOt90S0KZc5st1kJfCps6oKQ+/a8BvIVE= X-Google-Smtp-Source: AK7set8JUZry+QKvdXZ/CCoVP51sWXOMJKP4Z1uaD8UomAmb9IbX2ZS1/ffYikSQq99a3HZaeVorKg== X-Received: by 2002:a05:6870:9129:b0:169:b676:d643 with SMTP id o41-20020a056870912900b00169b676d643mr2930832oae.59.1675345990097; Thu, 02 Feb 2023 05:53:10 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt , Bin Meng Subject: [PATCH v10 2/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Thu, 2 Feb 2023 10:52:56 -0300 Message-Id: <20230202135257.1657482-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202135257.1657482-1-dbarboza@ventanamicro.com> References: <20230202135257.1657482-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1675346035473100002 Content-Type: text/plain; charset="utf-8" The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren't calling riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and allow these boards to opt out from initrd loading. Cc: Palmer Dabbelt Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 21 ++++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 11 +---------- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 11 +---------- hw/riscv/spike.c | 11 +---------- hw/riscv/virt.c | 11 +---------- include/hw/riscv/boot.h | 1 + 8 files changed, 27 insertions(+), 45 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 5ec6d32165..1e32ce1e10 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -176,10 +176,12 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong kernel_start_addr, + bool load_initrd, symbol_fn_t sym_cb) { const char *kernel_filename =3D machine->kernel_filename; uint64_t kernel_load_base, kernel_entry, kernel_low; + void *fdt =3D machine->fdt; =20 g_assert(kernel_filename !=3D NULL); =20 @@ -199,21 +201,34 @@ target_ulong riscv_load_kernel(MachineState *machine, kernel_entry =3D kernel_low; } =20 - return kernel_entry; + goto out; } =20 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } =20 if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry =3D kernel_start_addr; + goto out; } =20 error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } =20 void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 712625d2a4..e81bbd12df 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -630,16 +630,7 @@ static void microchip_icicle_kit_machine_init(MachineS= tate *machine) firmware_end_addr= ); =20 kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DR= AM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 7fe4fb5628..b06944d382 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -102,7 +102,8 @@ static void opentitan_board_init(MachineState *machine) =20 if (machine->kernel_filename) { riscv_load_kernel(machine, &s->soc.cpus, - memmap[IBEX_DEV_RAM].base, NULL); + memmap[IBEX_DEV_RAM].base, + false, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1a7d381514..04939b60c3 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -115,7 +115,8 @@ static void sifive_e_machine_init(MachineState *machine) =20 if (machine->kernel_filename) { riscv_load_kernel(machine, &s->soc.cpus, - memmap[SIFIVE_E_DEV_DTIM].base, NULL); + memmap[SIFIVE_E_DEV_DTIM].base, + false, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 71be442a50..ad3bb35b34 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -599,16 +599,7 @@ static void sifive_u_machine_init(MachineState *machin= e) firmware_end_addr= ); =20 kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 1fa91167ab..a584d5b3a2 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -307,16 +307,7 @@ static void spike_board_init(MachineState *machine) =20 kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], kernel_start_addr, - htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + true, htif_symbol_callback); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d0531cc641..2f2c82e8df 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1278,16 +1278,7 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) firmware_end_addr= ); =20 kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 6295316afb..ea1de8b020 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,6 +46,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong firmware_end_addr, + bool load_initrd, symbol_fn_t sym_cb); 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([177.102.69.207]) by smtp.gmail.com with ESMTPSA id 45-20020a9d0330000000b00684e55f4541sm6547416otv.70.2023.02.02.05.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:53:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hdzoMAEBJTe3nsL3itLXWDGswEM52iM44T0PgtSJ3ls=; b=TH9cuEoDGyyx6tYwNozH5kaJ3J4PqmadwN1YmweYS4BDEh6z/aCRiG4XAjs0MbMlA3 +7gXiy9Y0D6FMHSVb8HsnDMfwRLRghf/npdlwUgQMDetp6xli54AuCaiguUbwZXsH9mi Eir9Yw6o9B421xGjXvKzqFkb6UG3Um8JeTeMbheC6riOuUE5WLvFiW8Ezc5Fq89oTy80 Cj52LAV815D4RTAZpB7esfMaOk9Ie09EJM2SUvAFKM0o1QHQaRvkZlV4uhxIv16VGFIl hvQPf1+YPRA+laKynYpbLp4f+3YTVPH2FVrrsoq6NL9NcTlO7nzujYI9ms/W6VF1oFqJ k7Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hdzoMAEBJTe3nsL3itLXWDGswEM52iM44T0PgtSJ3ls=; b=EbUpMXABUoOICJ9v7q/Fa5IiNyscFCVkucIqTJkmY39FaJKIuS/TMxehnLsXfZe4jm fr/mj7RZoSLs0WnTbS5dIwlAoKEpV2+FRR/Rwl9DtemXVK3NdI+OellAV1nMKRMFlvOs hX7GgUqkoj5KVn6inQ1/zbdqb21O/9KCgjmR474G2UH0GbZv8cfykH6gAWVkhW5GYryr Fj7+4Qi6Gfj5YsehYfbvbfTGkrzOYN/iiQcE9bDnIecMIUSvNdTvlgbMOubh84x3XTum Ks8syGAD83QLm14qr8gDZDW46AnW+LWM0mrI3aPeeJulXdse/Ixo10czf3Za4JV4Fae0 YzKg== X-Gm-Message-State: AO0yUKUjbXbnz11ZhJaa/WSzQircn+PGxTB56a94Z9asVS9ZPyQ9EQVJ 4h2vncoViZco9UNquTC6eQOVDPhyUfDwCewuZ1w= X-Google-Smtp-Source: AK7set9LAANoyKMcqAlVOVUZ+8N3vTSYn1WcfEZTZr4Q2FWai8lbwqNpT0XFtJGcdBuEHNMlR0mgOw== X-Received: by 2002:a05:6808:a:b0:35c:46c8:2638 with SMTP id u10-20020a056808000a00b0035c46c82638mr2871633oic.12.1675345992446; Thu, 02 Feb 2023 05:53:12 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v10 3/3] hw/riscv/boot.c: make riscv_load_initrd() static Date: Thu, 2 Feb 2023 10:52:57 -0300 Message-Id: <20230202135257.1657482-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202135257.1657482-1-dbarboza@ventanamicro.com> References: <20230202135257.1657482-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1675346086780100007 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 1e32ce1e10..72885e4a6f 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_= filename, exit(1); } =20 +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename =3D machine->initrd_filename; + uint64_t mem_size =3D machine->ram_size; + void *fdt =3D machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename !=3D NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size =3D load_ramdisk(filename, start, mem_size - start); + if (size =3D=3D -1) { + size =3D load_image_targphys(filename, start, mem_size - start); + if (size =3D=3D -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end =3D start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong kernel_start_addr, @@ -231,46 +271,6 @@ out: return kernel_entry; } =20 -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename =3D machine->initrd_filename; - uint64_t mem_size =3D machine->ram_size; - void *fdt =3D machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename !=3D NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size =3D load_ramdisk(filename, start, mem_size - start); - if (size =3D=3D -1) { - size =3D load_image_targphys(filename, start, mem_size - start); - if (size =3D=3D -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end =3D start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - /* * This function makes an assumption that the DRAM interval * 'dram_base' + 'dram_size' is contiguous. diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index ea1de8b020..a2e4ae9cb0 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,7 +48,6 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, MachineState *ms); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); --=20 2.39.1