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Tsirkin" , Marcel Apfelbaum Subject: [PATCH 1/9] hw/i386/sgx: Do not open-code qdev_realize_and_unref() Date: Fri, 3 Feb 2023 12:36:42 +0100 Message-Id: <20230203113650.78146-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675424393558100001 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Markus Armbruster --- hw/i386/sgx.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index db004d17a6..5ddc5d7ea2 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -299,7 +299,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) &sgx_epc->mr); =20 for (list =3D x86ms->sgx_epc_list; list; list =3D list->next) { - obj =3D object_new("sgx-epc"); + obj =3D object_new(TYPE_SGX_EPC); =20 /* set the memdev link with memory backend */ object_property_parse(obj, SGX_EPC_MEMDEV_PROP, list->value->memde= v, @@ -307,8 +307,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) /* set the numa node property for sgx epc object */ object_property_set_uint(obj, SGX_EPC_NUMA_NODE_PROP, list->value-= >node, &error_fatal); - object_property_set_bool(obj, "realized", true, &error_fatal); - object_unref(obj); + qdev_realize_and_unref(DEVICE(obj), NULL, &error_fatal); } =20 if ((sgx_epc->base + sgx_epc->size) < sgx_epc->base) { --=20 2.38.1 From nobody Wed Apr 24 12:44:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Fri, 03 Feb 2023 03:37:02 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PATCH 2/9] hw/ppc/sam460ex: Correctly set MAL properties Date: Fri, 3 Feb 2023 12:36:43 +0100 Message-Id: <20230203113650.78146-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675424307431100009 MAL properties are declared as uint8_t: static Property ppc4xx_mal_properties[] =3D { DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0), DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0), DEFINE_PROP_END_OF_LIST(), }; Set the property using qdev_prop_set_uint8(). Fixes: da116a8aab ("ppc/ppc405: QOM'ify MAL") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: BALATON Zoltan --- hw/ppc/sam460ex.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 4a22ce3761..cf065aae0e 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -389,8 +389,8 @@ static void sam460ex_init(MachineState *machine) =20 /* MAL */ dev =3D qdev_new(TYPE_PPC4xx_MAL); - qdev_prop_set_uint32(dev, "txc-num", 4); - qdev_prop_set_uint32(dev, "rxc-num", 16); + qdev_prop_set_uint8(dev, "txc-num", 4); + qdev_prop_set_uint8(dev, "rxc-num", 16); ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); object_unref(OBJECT(dev)); sbdev =3D SYS_BUS_DEVICE(dev); --=20 2.38.1 From nobody Wed Apr 24 12:44:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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Fri, 03 Feb 2023 03:37:07 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joel Stanley , Peter Maydell Subject: [PATCH 3/9] hw/arm/nrf51: QOM-alias 'flash-size' property in SoC object Date: Fri, 3 Feb 2023 12:36:44 +0100 Message-Id: <20230203113650.78146-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675424329422100002 No need to use an intermediate 'flash-size' property in the SoC object. Alias the property, so when the machine (here microbit) sets the value on the SoC, it is propagated to the flash object. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/microbit.c | 5 ++++- hw/arm/nrf51_soc.c | 10 +--------- hw/nvram/nrf51_nvm.c | 6 +++++- include/hw/arm/nrf51_soc.h | 1 - 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 50df362088..79b5574884 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -36,6 +36,7 @@ static void microbit_init(MachineState *machine) MicrobitMachineState *s =3D MICROBIT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mr; + int64_t flash_size; =20 object_initialize_child(OBJECT(machine), "nrf51", &s->nrf51, TYPE_NRF51_SOC); @@ -43,6 +44,8 @@ static void microbit_init(MachineState *machine) object_property_set_link(OBJECT(&s->nrf51), "memory", OBJECT(system_memory), &error_fatal); sysbus_realize(SYS_BUS_DEVICE(&s->nrf51), &error_fatal); + flash_size =3D object_property_get_int(OBJECT(&s->nrf51), + "flash-size", &error_abort); =20 /* * Overlap the TWI stub device into the SoC. This is a microbit-speci= fic @@ -57,7 +60,7 @@ static void microbit_init(MachineState *machine) mr, -1); =20 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - 0, s->nrf51.flash_size); + 0, flash_size); } =20 static void microbit_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 34da0d62f0..cc4a636c51 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -24,9 +24,7 @@ * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_PAGES 256 #define NRF51822_SRAM_PAGES 16 -#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) =20 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) @@ -122,11 +120,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Er= ror **errp) BASE_TO_IRQ(NRF51_RNG_BASE))); =20 /* UICR, FICR, NVMC, FLASH */ - if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size", - s->flash_size, errp)) { - return; - } - if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) { return; } @@ -199,6 +192,7 @@ static void nrf51_soc_init(Object *obj) object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG); =20 object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM); + object_property_add_alias(obj, "flash-size", OBJECT(&s->nvm), "flash-s= ize"); =20 object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO); =20 @@ -215,8 +209,6 @@ static Property nrf51_soc_properties[] =3D { DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGIO= N, MemoryRegion *), DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_S= IZE), - DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, - NRF51822_FLASH_SIZE), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c index 7f1db8c423..bfae028fcd 100644 --- a/hw/nvram/nrf51_nvm.c +++ b/hw/nvram/nrf51_nvm.c @@ -26,6 +26,9 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" =20 +#define NRF51822_FLASH_PAGES 256 +#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) + /* * FICR Registers Assignments * CODEPAGESIZE 0x010 @@ -358,7 +361,8 @@ static void nrf51_nvm_reset(DeviceState *dev) } =20 static Property nrf51_nvm_properties[] =3D { - DEFINE_PROP_UINT32("flash-size", NRF51NVMState, flash_size, 0x40000), + DEFINE_PROP_UINT32("flash-size", NRF51NVMState, + flash_size, NRF51822_FLASH_SIZE), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index e52a56e75e..8cf0c21614 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -45,7 +45,6 @@ struct NRF51State { MemoryRegion twi; =20 uint32_t sram_size; - uint32_t flash_size; =20 MemoryRegion *board_memory; =20 --=20 2.38.1 From nobody Wed Apr 24 12:44:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675424345; cv=none; d=zohomail.com; s=zohoarc; b=XEtw+3SFI2pqXvUCDt60CawODrcb7p6EXeDZkb5d+AxZfOpkUMjusMbc4fr2/GmiYUh7ufv3rwRgLzfxU8JgxqXsKJGeVi6LN4E3ay82aA//T+A6XhSXs139JdpJCCkJO4wMtUQhWlQz6zPHZIj2eCse0eogbboI5heDGsLLGOI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675424347475100003 No need to use intermediate 'fec-phy-num' properties in the SoC object. Alias the properties, so when the machines set the value on the SoC, it is propagated to the network device object. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/fsl-imx25.c | 3 +-- hw/arm/fsl-imx6.c | 3 +-- hw/arm/fsl-imx6ul.c | 8 ++++---- hw/arm/fsl-imx7.c | 12 ++++++------ include/hw/arm/fsl-imx25.h | 1 - include/hw/arm/fsl-imx6.h | 1 - include/hw/arm/fsl-imx6ul.h | 2 -- include/hw/arm/fsl-imx7.h | 1 - 8 files changed, 12 insertions(+), 19 deletions(-) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 24c4374590..eff58e1f7a 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -55,6 +55,7 @@ static void fsl_imx25_init(Object *obj) } =20 object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC); + object_property_add_alias(obj, "fec-phy-num", OBJECT(&s->fec), "phy-nu= m"); =20 object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC); =20 @@ -169,7 +170,6 @@ static void fsl_imx25_realize(DeviceState *dev, Error *= *errp) epit_table[i].irq)); } =20 - object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, &err); qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) { @@ -315,7 +315,6 @@ static void fsl_imx25_realize(DeviceState *dev, Error *= *errp) } =20 static Property fsl_imx25_properties[] =3D { - DEFINE_PROP_UINT32("fec-phy-num", FslIMX25State, phy_num, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 00dafe3f62..4f870c928c 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -100,6 +100,7 @@ static void fsl_imx6_init(Object *obj) =20 =20 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); + object_property_add_alias(obj, "fec-phy-num", OBJECT(&s->eth), "phy-nu= m"); } =20 static void fsl_imx6_realize(DeviceState *dev, Error **errp) @@ -377,7 +378,6 @@ static void fsl_imx6_realize(DeviceState *dev, Error **= errp) spi_table[i].irq)); } =20 - object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err); qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { return; @@ -451,7 +451,6 @@ static void fsl_imx6_realize(DeviceState *dev, Error **= errp) } =20 static Property fsl_imx6_properties[] =3D { - DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index d88d6cc1c5..8b3939e8c5 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -120,8 +120,12 @@ static void fsl_imx6ul_init(Object *obj) * Ethernet */ for (i =3D 0; i < FSL_IMX6UL_NUM_ETHS; i++) { + g_autofree gchar *propname =3D g_strdup_printf("fec%d-phy-num", i = + 1); snprintf(name, NAME_SIZE, "eth%d", i); object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); + qdev_prop_set_uint32(DEVICE(&s->eth[i]), "phy-num", i); + object_property_add_alias(obj, propname, + OBJECT(&s->eth[i]), "phy-num"); } =20 /* USB */ @@ -424,8 +428,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) FSL_IMX6UL_ENET2_TIMER_IRQ, }; =20 - object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", - s->phy_num[i], &error_abort); object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort= ); qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); @@ -618,8 +620,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 static Property fsl_imx6ul_properties[] =3D { - DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), - DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index afc7480799..df035c9314 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -102,8 +102,12 @@ static void fsl_imx7_init(Object *obj) * Ethernet */ for (i =3D 0; i < FSL_IMX7_NUM_ETHS; i++) { - snprintf(name, NAME_SIZE, "eth%d", i); - object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); + g_autofree gchar *propname =3D g_strdup_printf("fec%d-phy-num", i = + 1); + snprintf(name, NAME_SIZE, "eth%d", i); + object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); + qdev_prop_set_uint32(DEVICE(&s->eth[i]), "phy-num", i); + object_property_add_alias(obj, propname, + OBJECT(&s->eth[i]), "phy-num"); } =20 /* @@ -402,8 +406,6 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) FSL_IMX7_ENET2_ADDR, }; =20 - object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", - s->phy_num[i], &error_abort); object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort); qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); @@ -599,8 +601,6 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) } =20 static Property fsl_imx7_properties[] =3D { - DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0), - DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 1b1086e945..e377f8e79a 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -66,7 +66,6 @@ struct FslIMX25State { MemoryRegion rom[2]; MemoryRegion iram; MemoryRegion iram_alias; - uint32_t phy_num; }; =20 /** diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 83291457cf..f7d1a94640 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -74,7 +74,6 @@ struct FslIMX6State { MemoryRegion caam; MemoryRegion ocram; MemoryRegion ocram_alias; - uint32_t phy_num; }; =20 =20 diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 7812e516a5..5217eeb8ff 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -88,8 +88,6 @@ struct FslIMX6ULState { MemoryRegion caam; MemoryRegion ocram; MemoryRegion ocram_alias; - - uint32_t phy_num[FSL_IMX6UL_NUM_ETHS]; }; =20 enum FslIMX6ULMemoryMap { diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 4e5e071864..16c68a4937 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -82,7 +82,6 @@ struct FslIMX7State { IMX7GPRState gpr; ChipideaState usb[FSL_IMX7_NUM_USBS]; DesignwarePCIEHost pcie; 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^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Markus Armbruster --- hw/usb/hcd-ohci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/usb/hcd-ohci.h b/hw/usb/hcd-ohci.h index 11ac57058d..e5e6b434fd 100644 --- a/hw/usb/hcd-ohci.h +++ b/hw/usb/hcd-ohci.h @@ -21,6 +21,7 @@ #ifndef HCD_OHCI_H #define HCD_OHCI_H =20 +#include "hw/sysbus.h" #include "sysemu/dma.h" #include "hw/usb.h" #include "qom/object.h" --=20 2.38.1 From nobody Wed Apr 24 12:44:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675424305; cv=none; d=zohomail.com; s=zohoarc; b=YSM2bACfwCJT1WBdvkn5RZ60KylSGlSwrW1qbrW/ZnLkDqhG840f8uDHMp0F+gxI8U6FtR9hFD+jsAph1rhXh/TVhM3OWv9YkCHOxbSWwtNH5eNi/9mOOJ3bM7lA/CoT9PsOotUwRoPA2tORd6AzYAm7KxM/r/2daAbXV1h9xIQ= ARC-Message-Signature: i=1; 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Fri, 03 Feb 2023 03:37:22 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan , Yoshinori Sato , Magnus Damm Subject: [PATCH 6/9] hw/display/sm501: QOM-alias 'dma-offset' property in chipset object Date: Fri, 3 Feb 2023 12:36:47 +0100 Message-Id: <20230203113650.78146-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675424307446100010 No need to use an intermediate 'dma-offset' property in the chipset object. Alias the property, so when the machine (here r2d-plus) sets the value on the chipset, it is propagated to the OHCI object. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/display/sm501.c | 22 +++++++++++----------- hw/sh4/r2d.c | 2 +- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 52e42585af..49a648e952 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -28,6 +28,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" +#include "hw/usb/hcd-ohci.h" #include "hw/char/serial.h" #include "ui/console.h" #include "hw/sysbus.h" @@ -1942,7 +1943,7 @@ struct SM501SysBusState { /*< public >*/ SM501State state; uint32_t vram_size; - uint32_t base; + OHCISysBusState ohci; SerialMM serial; }; =20 @@ -1950,7 +1951,6 @@ static void sm501_realize_sysbus(DeviceState *dev, Er= ror **errp) { SM501SysBusState *s =3D SYSBUS_SM501(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - DeviceState *usb_dev; MemoryRegion *mr; =20 sm501_init(&s->state, dev, s->vram_size); @@ -1963,13 +1963,10 @@ static void sm501_realize_sysbus(DeviceState *dev, = Error **errp) sysbus_init_mmio(sbd, &s->state.mmio_region); =20 /* bridge to usb host emulation module */ - usb_dev =3D qdev_new("sysbus-ohci"); - qdev_prop_set_uint32(usb_dev, "num-ports", 2); - qdev_prop_set_uint64(usb_dev, "dma-offset", s->base); - sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->ohci), &error_fatal); memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, - sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0)); - sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev)); + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ohci), 0)= ); + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->ohci)); =20 /* bridge to serial emulation module */ sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal); @@ -1980,7 +1977,6 @@ static void sm501_realize_sysbus(DeviceState *dev, Er= ror **errp) =20 static Property sm501_sysbus_properties[] =3D { DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), - DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -2016,15 +2012,19 @@ static void sm501_sysbus_class_init(ObjectClass *kl= ass, void *data) static void sm501_sysbus_init(Object *o) { SM501SysBusState *sm501 =3D SYSBUS_SM501(o); + OHCISysBusState *ohci =3D &sm501->ohci; SerialMM *smm =3D &sm501->serial; =20 + object_initialize_child(o, "ohci", ohci, TYPE_SYSBUS_OHCI); + object_property_add_alias(o, "base", OBJECT(ohci), "dma-offset"); + qdev_prop_set_uint32(DEVICE(ohci), "num-ports", 2); + object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM); qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); =20 - object_property_add_alias(o, "chardev", - OBJECT(smm), "chardev"); + object_property_add_alias(o, "chardev", OBJECT(smm), "chardev"); } =20 static const TypeInfo sm501_sysbus_info =3D { diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 39fc4f19d9..279724ffbb 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -274,7 +274,7 @@ static void r2d_init(MachineState *machine) dev =3D qdev_new("sysbus-sm501"); busdev =3D SYS_BUS_DEVICE(dev); qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE); - qdev_prop_set_uint32(dev, "base", 0x10000000); + qdev_prop_set_uint64(dev, "base", 0x10000000); qdev_prop_set_chr(dev, "chardev", serial_hd(2)); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0x10000000); --=20 2.38.1 From nobody Wed Apr 24 12:44:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675424379; cv=none; d=zohomail.com; s=zohoarc; b=Zq/HDzX3CKZ+jRaaM7eMx0dRlT4t3zkcQai0gISFJjBAaou5l918qM+bpF8jpeWve5mSa5w715vpIJgEDFVwnk0k1mdpJHl1M9AnqvmHh7HSdOeT/QBXabkPLK/P5+dCiMUryM2wcrAAIr56EAxm5qaZCkmKd1jyU+snU6bJBUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675424379; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675424379527100001 DEFINE_PROP_DMAADDR() is only used once. Since it doesn't add much value, simply remove it, along with the header defining it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/usb/hcd-ohci-pci.c | 1 - hw/usb/hcd-ohci.c | 3 +-- include/hw/qdev-dma.h | 16 ---------------- 3 files changed, 1 insertion(+), 19 deletions(-) delete mode 100644 include/hw/qdev-dma.h diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c index 6b630d35a7..92cc151264 100644 --- a/hw/usb/hcd-ohci-pci.c +++ b/hw/usb/hcd-ohci-pci.c @@ -25,7 +25,6 @@ #include "migration/vmstate.h" #include "hw/pci/pci_device.h" #include "hw/sysbus.h" -#include "hw/qdev-dma.h" #include "hw/qdev-properties.h" #include "trace.h" #include "hcd-ohci.h" diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 9d68036d23..26c377bf1b 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -33,7 +33,6 @@ #include "hw/usb.h" #include "migration/vmstate.h" #include "hw/sysbus.h" -#include "hw/qdev-dma.h" #include "hw/qdev-properties.h" #include "trace.h" #include "hcd-ohci.h" @@ -2008,7 +2007,7 @@ static Property ohci_sysbus_properties[] =3D { DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus), DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0), - DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0), + DEFINE_PROP_UINT64("dma-offset", OHCISysBusState, dma_offset, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/qdev-dma.h b/include/hw/qdev-dma.h deleted file mode 100644 index b00391aa0c..0000000000 --- a/include/hw/qdev-dma.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Support for dma_addr_t typed properties - * - * Copyright (C) 2012 David Gibson, IBM Corporation. - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef HW_QDEV_DMA_H -#define HW_QDEV_DMA_H - -#define DEFINE_PROP_DMAADDR(_n, _s, _f, _d) \ - DEFINE_PROP_UINT64(_n, _s, _f, _d) - -#endif --=20 2.38.1 From nobody Wed Apr 24 12:44:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675424413; cv=none; d=zohomail.com; s=zohoarc; b=Wqv2ubKiH3/F6mnKA+1nrosIqiZNkSVMf5PCvRkD4fcM04lVEcfP50VBDo+pq1pS1g376HoZbx2a6J2IBtr/XRCqaO1v0E6t2B3ki8z7s+r9eqto+r5zOqbrwFunhNpuCZvG2wyahNO9IEYblfFY6sTuv0b+Htu8mTBJzTxQ3sk= ARC-Message-Signature: i=1; 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Fri, 03 Feb 2023 03:37:32 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Aleksandar Rikalo , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 8/9] hw/mips: Declare all length properties as unsigned Date: Fri, 3 Feb 2023 12:36:49 +0100 Message-Id: <20230203113650.78146-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675424413850100001 Some length properties are signed, other unsigned: hw/mips/cps.c:183: DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, = 1), hw/mips/cps.c:184: DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq= , 256), hw/misc/mips_cmgcr.c:215: DEFINE_PROP_INT32("num-vp", MIPSGCRState, nu= m_vps, 1), hw/misc/mips_cpc.c:167: DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num= _vp, 0x1), hw/misc/mips_itu.c:552: DEFINE_PROP_INT32("num-fifo", MIPSITUState, nu= m_fifo, hw/misc/mips_itu.c:554: DEFINE_PROP_INT32("num-semaphores", MIPSITUSta= te, Since negative values are not used (the minimum is '0'), unify by declaring all properties as unsigned. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/mips_gic.c | 4 ++-- hw/mips/boston.c | 2 +- hw/mips/cps.c | 12 ++++++------ hw/mips/malta.c | 2 +- hw/misc/mips_cmgcr.c | 2 +- hw/misc/mips_itu.c | 4 ++-- include/hw/intc/mips_gic.h | 4 ++-- include/hw/misc/mips_cmgcr.h | 2 +- include/hw/misc/mips_itu.h | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index bda4549925..4bdc3b1bd1 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -439,8 +439,8 @@ static void mips_gic_realize(DeviceState *dev, Error **= errp) } =20 static Property mips_gic_properties[] =3D { - DEFINE_PROP_INT32("num-vp", MIPSGICState, num_vps, 1), - DEFINE_PROP_INT32("num-irq", MIPSGICState, num_irq, 256), + DEFINE_PROP_UINT32("num-vp", MIPSGICState, num_vps, 1), + DEFINE_PROP_UINT32("num-irq", MIPSGICState, num_irq, 256), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/mips/boston.c b/hw/mips/boston.c index a9d87f3437..21ad844519 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -702,7 +702,7 @@ static void boston_mach_init(MachineState *machine) object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS= ); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, &error_fatal); - object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, + object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", qdev_get_clock_out(dev, "cpu-refclk")); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 2b436700ce..38acc57468 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -114,9 +114,9 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU= ); - object_property_set_int(OBJECT(&s->itu), "num-fifo", 16, + object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); - object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16, + object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, &error_abort); object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_pre= sent, &error_abort); @@ -133,7 +133,7 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) =20 /* Cluster Power Controller */ object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); - object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp, &error_abort); object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, &error_abort); @@ -146,9 +146,9 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) =20 /* Global Interrupt Controller */ object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); - object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp, &error_abort); - object_property_set_int(OBJECT(&s->gic), "num-irq", 128, + object_property_set_uint(OBJECT(&s->gic), "num-irq", 128, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { return; @@ -161,7 +161,7 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) gcr_base =3D env->CP0_CMGCRBase << 4; =20 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); - object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, &error_abort); object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, &error_abort); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ec172b111a..af9021316d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1066,7 +1066,7 @@ static void create_cps(MachineState *ms, MaltaState *= s, object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, &error_fatal); - object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, + object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c index 3c8b37f700..66eb11662c 100644 --- a/hw/misc/mips_cmgcr.c +++ b/hw/misc/mips_cmgcr.c @@ -212,7 +212,7 @@ static const VMStateDescription vmstate_mips_gcr =3D { }; =20 static Property mips_gcr_properties[] =3D { - DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), + DEFINE_PROP_UINT32("num-vp", MIPSGCRState, num_vps, 1), DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800), DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR), DEFINE_PROP_LINK("gic", MIPSGCRState, gic_mr, TYPE_MEMORY_REGION, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index badef5c214..a06cdd10ea 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -549,9 +549,9 @@ static void mips_itu_reset(DeviceState *dev) } =20 static Property mips_itu_properties[] =3D { - DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, + DEFINE_PROP_UINT32("num-fifo", MIPSITUState, num_fifo, ITC_FIFO_NUM_MAX), - DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores, + DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), DEFINE_PROP_END_OF_LIST(), diff --git a/include/hw/intc/mips_gic.h b/include/hw/intc/mips_gic.h index eeb136e261..5e4c71edd4 100644 --- a/include/hw/intc/mips_gic.h +++ b/include/hw/intc/mips_gic.h @@ -211,8 +211,8 @@ struct MIPSGICState { /* GIC VP Timer */ MIPSGICTimerState *gic_timer; =20 - int32_t num_vps; - int32_t num_irq; + uint32_t num_vps; + uint32_t num_irq; }; =20 #endif /* MIPS_GIC_H */ diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h index 9fa58942d7..db4bf5f449 100644 --- a/include/hw/misc/mips_cmgcr.h +++ b/include/hw/misc/mips_cmgcr.h @@ -75,7 +75,7 @@ struct MIPSGCRState { SysBusDevice parent_obj; =20 int32_t gcr_rev; - int32_t num_vps; + uint32_t num_vps; hwaddr gcr_base; MemoryRegion iomem; MemoryRegion *cpc_mr; diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 50d961106d..ab6d286c38 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -57,8 +57,8 @@ struct MIPSITUState { SysBusDevice parent_obj; /*< public >*/ =20 - int32_t num_fifo; - int32_t num_semaphores; + uint32_t num_fifo; + uint32_t num_semaphores; =20 /* ITC Storage */ ITCStorageCell *cell; --=20 2.38.1 From nobody Wed Apr 24 12:44:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675424405697100001 QOM objects shouldn't access each other internals fields except using the QOM API. mips_cps_realize() instantiates a TYPE_MIPS_ITU object, and directly sets the 'saar' pointer: if (saar_present) { s->itu.saar =3D &env->CP0_SAAR; } In order to avoid that, pass the MIPS_CPU object via a QOM link property, and set the 'saar' pointer in mips_itu_realize(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- RFC because not tested. --- hw/mips/cps.c | 23 ++++++----------------- hw/misc/mips_itu.c | 26 ++++++++++++++++++-------- include/hw/misc/mips_itu.h | 5 ++--- 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 38acc57468..2b5269ebf1 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -66,20 +66,17 @@ static bool cpu_mips_itu_supported(CPUMIPSState *env) static void mips_cps_realize(DeviceState *dev, Error **errp) { MIPSCPSState *s =3D MIPS_CPS(dev); - CPUMIPSState *env; - MIPSCPU *cpu; - int i; target_ulong gcr_base; bool itu_present =3D false; - bool saar_present =3D false; =20 if (!clock_get(s->clock)) { error_setg(errp, "CPS input clock is not connected to an output cl= ock"); return; } =20 - for (i =3D 0; i < s->num_vp; i++) { - cpu =3D MIPS_CPU(object_new(s->cpu_type)); + for (int i =3D 0; i < s->num_vp; i++) { + MIPSCPU *cpu =3D MIPS_CPU(object_new(s->cpu_type)); + CPUMIPSState *env =3D &cpu->env; =20 /* All VPs are halted on reset. Leave powering up to CPC. */ if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", tr= ue, @@ -97,7 +94,6 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) cpu_mips_irq_init_cpu(cpu); cpu_mips_clock_init(cpu); =20 - env =3D &cpu->env; if (cpu_mips_itu_supported(env)) { itu_present =3D true; /* Attach ITC Tag to the VP */ @@ -107,22 +103,15 @@ static void mips_cps_realize(DeviceState *dev, Error = **errp) qemu_register_reset(main_cpu_reset, cpu); } =20 - cpu =3D MIPS_CPU(first_cpu); - env =3D &cpu->env; - saar_present =3D (bool)env->saarp; - /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU= ); + object_property_set_link(OBJECT(&s->itu), "cpu[0]", + OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, &error_abort); - object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_pre= sent, - &error_abort); - if (saar_present) { - s->itu.saar =3D &env->CP0_SAAR; - } if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { return; } @@ -158,7 +147,7 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic)= , 0)); =20 /* Global Configuration Registers */ - gcr_base =3D env->CP0_CMGCRBase << 4; + gcr_base =3D MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; =20 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index a06cdd10ea..0eda302db4 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -93,10 +93,10 @@ void itc_reconfigure(MIPSITUState *tag) uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 - if (tag->saar_present) { - address =3D ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; - size =3D 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f); - is_enabled =3D *(uint64_t *) tag->saar & 1; + if (tag->saar) { + address =3D (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; + size =3D 1ULL << ((tag->saar[0] >> 1) & 0x1f); + is_enabled =3D tag->saar[0] & 1; } =20 memory_region_transaction_begin(); @@ -157,7 +157,7 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain =3D 0) is 128 B */ - if (s->saar_present) { + if (s->saar) { return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & ITC_ICR0_BLK_GRAIN_MASK); } else { @@ -515,6 +515,7 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s =3D MIPS_ITU(dev); + CPUMIPSState *env; =20 if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -526,6 +527,15 @@ static void mips_itu_realize(DeviceState *dev, Error *= *errp) s->num_semaphores); return; } + if (!s->cpu0) { + error_setg(errp, "Missing 'cpu[0]' property"); + return; + } + + env =3D &s->cpu0->env; + if (env->saarp) { + s->saar =3D env->CP0_SAAR; + } =20 s->cell =3D g_new(ITCStorageCell, get_num_cells(s)); } @@ -534,8 +544,8 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s =3D MIPS_ITU(dev); =20 - if (s->saar_present) { - *(uint64_t *) s->saar =3D 0x11 << 1; + if (s->saar) { + s->saar[0] =3D 0x11 << 1; s->icr0 =3D get_num_cells(s) << ITC_ICR0_CELL_NUM; } else { s->ITCAddressMap[0] =3D 0; @@ -553,7 +563,7 @@ static Property mips_itu_properties[] =3D { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), + DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU = *), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index ab6d286c38..35218b2d14 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -72,9 +72,8 @@ struct MIPSITUState { uint64_t icr0; =20 /* SAAR */ - bool saar_present; - void *saar; - + uint64_t *saar; + MIPSCPU *cpu0; }; =20 /* Get ITC Configuration Tag memory region. */ --=20 2.38.1