According to spec, ctzw should work with 32-bit register, not 64. For example, previous implementation returns 33 for (1<<33) input when the new one returns 32. Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com> --- target/riscv/insn_trans/trans_rvb.c.inc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index XXXXXXX..XXXXXXX 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1) static void gen_ctzw(TCGv ret, TCGv arg1) { - tcg_gen_ctzi_tl(ret, arg1, 32); + TCGv_i32 t = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t, arg1); + tcg_gen_ctzi_i32(t, t, 32); + + tcg_gen_extu_i32_tl(ret, t); + + tcg_temp_free_i32(t); } static bool trans_ctz(DisasContext *ctx, arg_ctz *a) -- 2.39.1 According to spec, ctzw should work with 32-bit register, not 64. For example, previous implementation returns 33 for (1<<33) input when the new one returns 32. Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com> Suggested-by: Richard Henderson <richard.henderson@linaro.org> --- v2: - Use simpler solution suggested by Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index XXXXXXX..XXXXXXX 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); + ctx->ol = MXL_RV32; return gen_unary(ctx, a, EXT_ZERO, gen_ctzw); } -- 2.39.1