From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434596; cv=none; d=zohomail.com; s=zohoarc; b=iI84Z3c+gS1DVPP98Iz6VBEurFs6YmWw1D+SAK0UkEJlZR5CSFZiudMK51Vxoleei2KnQ0slRBlcdmpYGJmBKYy5ys+rPfcNM3hsMoIQtvZSa1+Ll+pPPYtY4dE7WCrSm1VB3bbWEAfrFk8JRW/MFDmlImaWKHgRUMtCMuvzl/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434596; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Li+pWB+M1ny80ksWu15v+SH9Uhscz2fzZUVC1wklHOc=; b=jUPqFP61c3Uw9nM1rDUYUFrXct/PcSCRbiOXWfgES0a32Oi0cXo0/pQr9ld/YzzxM9CpBThcXGGmGsPxYLvCJVSLTk9Wk0IVq0Qif0TCUXOqjFqwlhmcEDWeZOBLak2I+qMOVA/HjsS3+9itJyA3re2WOiBtG/FIbsffvrG95rg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434596786219.0684063081702; Fri, 3 Feb 2023 06:29:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4T-0006ev-Ax; Fri, 03 Feb 2023 09:29:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4H-0006ao-GA for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:34 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4F-00053d-PZ for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:33 -0500 Received: by mail-wm1-x333.google.com with SMTP id q8so3999534wmo.5 for ; Fri, 03 Feb 2023 06:29:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Li+pWB+M1ny80ksWu15v+SH9Uhscz2fzZUVC1wklHOc=; b=JXAzJ6aVeUmX4jW3n9mI3bu2+wJS722OrZm05c5aowDEyyYgjIns4tJnH08sspHz4F ImcBWQvlGK+RmFJneHyUPcTJ//dwA662ZZMuQnSEhVgc6UgExAEp9eZpYRgDNwAGqy1c w1TVE131EIIFGp8+JYV+ACc5lbukcnPjiLhX2OJW8FPqcK2Nf+NATA4a1bpku8qP/r+c UCRBgJ44wW7fvcUzdUT7SBWgYJv9CrreUiMaGwnCCuWhMcsskJHunAuh7hZm0cAuPzVq FUfzrO5g9rvqgwMS88kQ2iHJiD20jBL4wEJjmMBj9OrfY1U/ovj1Y4+/jJbgBfxqdTae WXTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Li+pWB+M1ny80ksWu15v+SH9Uhscz2fzZUVC1wklHOc=; b=SmvmmNHhLeuUFKD8jt6v818ll7evXcrO8u8WULDAZBjPeZfr4rjpi3+mackQ96mlnR m2jfZO5Dk/PCYOpA+o9zra5A6y6xlSes6Kq/Ph4IBkapzPgCF3T3O4l5dsEZYcvxNdMO PUrgOoc1FQQ/0X3Y7VSiMovRpjmxgJBcdTQrlm+f+IGEB42PY3g5Ucc6draCHlADwY6F wVQWoD586s6uP1YRAJkiXxVLKeroq3ZNiwLjyrgYonjosWRrF8FgK+itGWTI94SeJZAn Pjz7qyGJ7IYkUVSBqhLQ/kOZoCkz2xWsrg6QjHnGMR8V+ni8YVDBta4/RFrFkiut7hFj F6Xw== X-Gm-Message-State: AO0yUKXsCPKvNZyHQhnirC/94uyYuXs96Woa2lgHYvFSrz1mpdZzOxEs MERSelTHuqttuDIVqlhlgPg1csWXXha1raiN X-Google-Smtp-Source: AK7set8scNsUsKKg6zmwS0OB2y2R3PBtX6NAhxv3cb6S8msog7u1gBaSS/FNXFhMaW/3pVb/QCiSBQ== X-Received: by 2002:a05:600c:314a:b0:3df:ee43:860b with SMTP id h10-20020a05600c314a00b003dfee43860bmr731698wmo.23.1675434570103; Fri, 03 Feb 2023 06:29:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3 Date: Fri, 3 Feb 2023 14:28:55 +0000 Message-Id: <20230203142927.834793-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434597769100005 From: Richard Henderson Use the macro instead of two explicit string literals. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Auger Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 3 ++- hw/arm/virt.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 4bb444684f4..8378441dbb1 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -29,6 +29,7 @@ #include "exec/hwaddr.h" #include "kvm_arm.h" #include "hw/arm/boot.h" +#include "hw/arm/smmuv3.h" #include "hw/block/flash.h" #include "hw/boards.h" #include "hw/ide/internal.h" @@ -574,7 +575,7 @@ static void create_smmu(const SBSAMachineState *sms, PC= IBus *bus) DeviceState *dev; int i; =20 - dev =3D qdev_new("arm-smmuv3"); + dev =3D qdev_new(TYPE_ARM_SMMUV3); =20 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ea2413a0bad..90a7099d3b5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1343,7 +1343,7 @@ static void create_smmu(const VirtMachineState *vms, return; } =20 - dev =3D qdev_new("arm-smmuv3"); + dev =3D qdev_new(TYPE_ARM_SMMUV3); =20 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675435024; cv=none; d=zohomail.com; s=zohoarc; b=fLU4lDrDS5w+JxRd+WlEJ0K9z6tAmsgu1OCLU0shYEVCkuK7J5v1si6jBNpBPOur9CvR0Z/li1vSNF8BcAoQTQoKD9DhLLgt9ipRJb/2rMdrZe41SvitYQEfn6MnZiX+w/5MNi4f/62PStGXaD5+SsxiJ9rowniJ+g39haFtRqY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675435024; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=m8O7Eb+in4iFMyKSZKYhuiuIHFHL3PaJb5r8x77Y6qc=; b=SMIYU4lBk7M1igbzuTFVvzWcse9ONxc9nKMEPzbYlC/uJyHkxVZ9BkgZ9fOj0KGGrw04Jrzt9yo5vqH02HYTC7zeDnSEN4ELiDDjIFer8hJxVqauj7TYQagSS8C89bKPC3Jqlpa3t06LEzwl9b2xE6b7i9fxWmElcJbg1QIDR4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675435024511386.4993662325171; Fri, 3 Feb 2023 06:37:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4Q-0006eJ-D5; Fri, 03 Feb 2023 09:29:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4I-0006cW-Ni for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:34 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4G-00053h-7Q for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:34 -0500 Received: by mail-wm1-x32f.google.com with SMTP id k8-20020a05600c1c8800b003dc57ea0dfeso6160135wms.0 for ; Fri, 03 Feb 2023 06:29:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=m8O7Eb+in4iFMyKSZKYhuiuIHFHL3PaJb5r8x77Y6qc=; b=i8IPwMDBK6D7U86NTuPt5cIyVUk6mlA4mBJvYgIojsxJzoWKibHeuVtli4qnDOL3pt Yd1ld05rY1iYMGsLT5sK2vg9mY+TmQ2TVs/TMmMR3xx6ZDb0RjpiG+7WrXdNZSZhkFhM fq6HG09ZyrS7ZODB9X3lz7t0UVq/c5gpZXxdUliRhtvixCSs027smHEyXP+S0KRc83QX 665VkBj3IGZ2/lflE+CCSqULaMib+1y4TKCByWbm5Q/Qhx/cG3vHJ3GP4kyGz4wZ+gQ4 0l98wD09AeQ7u+us2R2gdWqnlpmUGjXXsoSH69kT11YiFKcWHJSxhUNpgT3WJ5lCbSyN Lv5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m8O7Eb+in4iFMyKSZKYhuiuIHFHL3PaJb5r8x77Y6qc=; b=lFM0aJ9Locjf1yjQeCfmqoZGKETy2b7APbMYDI8AJwXMybAhSx0C0dAy/jdMbJWupX DyudobwH75ifZSdK8HWGnFlTnbogYMsKzH4ZO6K5hqbxeRYEEwLSZ/7Nnc86P0n33goa KF/T2DzZSKeS8ERz5Kg8lMy+U0Dd8o7qg+Y3XQz8HB2XVVREAjF1BM1jikLlr3zDB+oD 9HJHxc4bYCrqmE3jFzLcpynPXY+oXp2VZO/CfXIlFY6vqfWu0IDaZXDVdLW7iSsSVppo Zu8BHj7cbs3N5CDg/LoXJcGiQKmEYdP1dTx0PVf0R8jY2/ZuOIh6rSMOXAPoNZiWXQ/C YvrA== X-Gm-Message-State: AO0yUKXq8lmNAMhSptnlZO2h36cJy0E4mbMvjAsK6/i4wqSVrKrxqdUB 7g/nxxa9PuDRzGzzKfob+99OqBHKoMWdROUl X-Google-Smtp-Source: AK7set9KWLzqe2JMhScMfZ61qBDk0+QCJQCWrGT9tmijUiUXGX9cXQ8WWOegNUqvEtELfEiWiai4rg== X-Received: by 2002:a05:600c:4ec7:b0:3dc:5e0d:4ce7 with SMTP id g7-20020a05600c4ec700b003dc5e0d4ce7mr9786261wmq.11.1675434570955; Fri, 03 Feb 2023 06:29:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/33] target/arm: Fix physical address resolution for Stage2 Date: Fri, 3 Feb 2023 14:28:56 +0000 Message-Id: <20230203142927.834793-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675435026272100001 From: Richard Henderson Conversion to probe_access_full missed applying the page offset. Cc: qemu-stable@nongnu.org Reported-by: Sid Manning Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230126233134.103193-1-richard.henderson@linaro.org Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking") Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/ptw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 57f3615a66d..2b125fff446 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -266,7 +266,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, if (unlikely(flags & TLB_INVALID_MASK)) { goto fail; } - ptw->out_phys =3D full->phys_addr; + ptw->out_phys =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); ptw->out_rw =3D full->prot & PAGE_WRITE; pte_attrs =3D full->pte_attrs; pte_secure =3D full->attrs.secure; --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434692; cv=none; d=zohomail.com; s=zohoarc; b=G3obJfFMYochXiDa2A9wLRnOICR/njuM/dLJG50Yr51appo3v7jOTLg4QKCncX4uie0wZ7bKCpb9IJ7fAGQQEhENQzWQLbm8dpK6BpIdwnE3/ats8ZIC7NLLY93eRnlbQIJXfa5/N0xfO+Q7SY4eqZB0sWrMFdwxLe2QvXLMjSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434692; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Dl2CfwC4j/0AnqvEmuWD2f4Vi2U4yq85CQrdrzm1Em8=; b=ZA3U1E5VY04oo4mOiAXf2sy4klYYnFJInjiq0PWEYGqvcqLL/MLbyazVw2IIignavAGZU/QxxXZSldulQ+mropF8U8CDSY8fP0tucAJLBH0rv+JoSk52wrBphiZ7C1jCAMKvzYD5YSAM9QvT9ACTH6ngQJ7n7KJ9OyJK/NFwYEY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434692686268.47123637906304; Fri, 3 Feb 2023 06:31:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4V-0006fM-1L; Fri, 03 Feb 2023 09:29:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4J-0006d3-DC for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:35 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4H-000545-DM for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:34 -0500 Received: by mail-wm1-x32e.google.com with SMTP id d4-20020a05600c3ac400b003db1de2aef0so4002262wms.2 for ; Fri, 03 Feb 2023 06:29:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Dl2CfwC4j/0AnqvEmuWD2f4Vi2U4yq85CQrdrzm1Em8=; b=p59wWQO866sLgxt/UIMwhf6fFMGO5jiMxdiazwnw5dhkgM9wQy/uTcjDvtA7zF38mn s6osZszOW5nrHr7Zz3j9dLRwVOW7puO5IGlfM3ycF15osziz7GvAZBqZMdVI3MQv4IVM CNJ6ajYjZtjKeHKNcIpEIOvx3lI86baz1ei8e4OWzToviMtonevA5FzGl+LLQMGFUqyy /eXP1aIG/O4hVDk936rHDmoJxgCqHvqLgtA4wuDnglFdGj0FIMefhxlMx+0KQRN2guYx NNWeoxH/m/gptdm/eVvM4egHOOVEDZCJlGFFG9EaIHvzyfy9XsBUipcz5c+JQS4CiDfX W2IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dl2CfwC4j/0AnqvEmuWD2f4Vi2U4yq85CQrdrzm1Em8=; b=gOk+nDVzNoIi2HWzIbQrKt1GwgWeUN2mdyPiOuaFwuyvUMrp2YNF4qJW14XvmhwfYM e9pmuNwOci4pfsBo98OxGCxX+zPgCiweVuzk7cs1Fggd+f0lqzUFOEhaHfDhI8/djcNu 2zhsYzLxoFU/hDMKI1ITJ0UAeGh8uWAp9et9IApzcq62z54qxWNpZE1v2OnJUoiaJTPT CGaKoqAIZ+GYaT3PI4DAicrL8rTdOEsnhkF4j9aQl2/esQ9/hoL+1zNO69NqFz+O0Ls1 o0AkB4aB0yeHsfL4u4oVwP2m8ofGy+9dgmlbJTHbDiKzIftHaTtmtKF5wvgSzu5yi5Nf tjMA== X-Gm-Message-State: AO0yUKUwhH76CQR3IcJIhiH2zull0trcHZon21CPPDV3WT/FW/dE/wCB yDOoy6fDGfgPc5iIZQN0tnA1Oas0ZtlHUyvG X-Google-Smtp-Source: AK7set99Rdub/uTII9i3qlvnqSCQeBYJPGcfI10t+5TCalEDrIr93zc+x3HTO85mwEOFtpKLSpxEcg== X-Received: by 2002:a05:600c:4447:b0:3d8:e0d3:ee24 with SMTP id v7-20020a05600c444700b003d8e0d3ee24mr12219695wmn.37.1675434571825; Fri, 03 Feb 2023 06:29:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/33] hw/char/pl011: refactor FIFO depth handling code Date: Fri, 3 Feb 2023 14:28:57 +0000 Message-Id: <20230203142927.834793-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434694756100015 From: Evgeny Iakovlev PL011 can be in either of 2 modes depending guest config: FIFO and single register. The last mode could be viewed as a 1-element-deep FIFO. Current code open-codes a bunch of depth-dependent logic. Refactor FIFO depth handling code to isolate calculating current FIFO depth. One functional (albeit guest-invisible) side-effect of this change is that previously we would always increment s->read_pos in UARTDR read handler even if FIFO was disabled, now we are limiting read_pos to not exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO). Signed-off-by: Evgeny Iakovlev Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell --- include/hw/char/pl011.h | 5 ++++- hw/char/pl011.c | 30 ++++++++++++++++++------------ 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index dc2c90eedca..926322e242d 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -27,6 +27,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011) /* This shares the same struct (and cast macro) as the base pl011 device */ #define TYPE_PL011_LUMINARY "pl011_luminary" =20 +/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth =3D= =3D 1) */ +#define PL011_FIFO_DEPTH 16 + struct PL011State { SysBusDevice parent_obj; =20 @@ -39,7 +42,7 @@ struct PL011State { uint32_t dmacr; uint32_t int_enabled; uint32_t int_level; - uint32_t read_fifo[16]; + uint32_t read_fifo[PL011_FIFO_DEPTH]; uint32_t ilpr; uint32_t ibrd; uint32_t fbrd; diff --git a/hw/char/pl011.c b/hw/char/pl011.c index c076813423f..3fa3b75d042 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -81,6 +81,17 @@ static void pl011_update(PL011State *s) } } =20 +static bool pl011_is_fifo_enabled(PL011State *s) +{ + return (s->lcr & 0x10) !=3D 0; +} + +static inline unsigned pl011_get_fifo_depth(PL011State *s) +{ + /* Note: FIFO depth is expected to be power-of-2 */ + return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; +} + static uint64_t pl011_read(void *opaque, hwaddr offset, unsigned size) { @@ -94,8 +105,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, c =3D s->read_fifo[s->read_pos]; if (s->read_count > 0) { s->read_count--; - if (++s->read_pos =3D=3D 16) - s->read_pos =3D 0; + s->read_pos =3D (s->read_pos + 1) & (pl011_get_fifo_depth(s) -= 1); } if (s->read_count =3D=3D 0) { s->flags |=3D PL011_FLAG_RXFE; @@ -273,11 +283,7 @@ static int pl011_can_receive(void *opaque) PL011State *s =3D (PL011State *)opaque; int r; =20 - if (s->lcr & 0x10) { - r =3D s->read_count < 16; - } else { - r =3D s->read_count < 1; - } + r =3D s->read_count < pl011_get_fifo_depth(s); trace_pl011_can_receive(s->lcr, s->read_count, r); return r; } @@ -286,15 +292,15 @@ static void pl011_put_fifo(void *opaque, uint32_t val= ue) { PL011State *s =3D (PL011State *)opaque; int slot; + unsigned pipe_depth; =20 - slot =3D s->read_pos + s->read_count; - if (slot >=3D 16) - slot -=3D 16; + pipe_depth =3D pl011_get_fifo_depth(s); + slot =3D (s->read_pos + s->read_count) & (pipe_depth - 1); s->read_fifo[slot] =3D value; s->read_count++; s->flags &=3D ~PL011_FLAG_RXFE; trace_pl011_put_fifo(value, s->read_count); - if (!(s->lcr & 0x10) || s->read_count =3D=3D 16) { + if (s->read_count =3D=3D pipe_depth) { trace_pl011_put_fifo_full(); s->flags |=3D PL011_FLAG_RXFF; } @@ -359,7 +365,7 @@ static const VMStateDescription vmstate_pl011 =3D { VMSTATE_UINT32(dmacr, PL011State), VMSTATE_UINT32(int_enabled, PL011State), VMSTATE_UINT32(int_level, PL011State), - VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16), + VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH), VMSTATE_UINT32(ilpr, PL011State), VMSTATE_UINT32(ibrd, PL011State), VMSTATE_UINT32(fbrd, PL011State), --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434754; cv=none; d=zohomail.com; s=zohoarc; b=HvokH/1NGwsrntfWUajyZ5d9nO5UbTzzvESzfoC5QdxHsKu3vfTvpow6SKK1JFnKMjMaoEYFyOGCBWJ9NN3POCuaGsYqe1jYZKf3+dlLy3R7HYYZRkPr3cXH0TDqDjsyE0EGK9tu3n02p/4tjlAyZffb65F3lW4Q8BI02Io8c6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434754; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yxaajrT8hw/p9R5XVhSvXLClGevo4qVUStBee60tFvg=; b=du5Jg9aMJ9i6+foQwakPeK3Vd5QRi/rMBh5G5hSDe5Dg9+o2RUAdQd5Pxfy4VSFR7JM+3b+YTRJursLy6dUfTG3GxFfep9NzhEBMVNwisbHQs++n/lOSYEZB9gDeSh6wlQ1mXZAM0kDsuJv14C46MT84T6Wk5NrjP6fOZnnqioQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434754265792.4268241073768; Fri, 3 Feb 2023 06:32:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4V-0006g1-DO; Fri, 03 Feb 2023 09:29:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4L-0006dI-1x for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:37 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4I-00054B-0a for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:35 -0500 Received: by mail-wm1-x330.google.com with SMTP id d4-20020a05600c3ac400b003db1de2aef0so4002293wms.2 for ; Fri, 03 Feb 2023 06:29:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yxaajrT8hw/p9R5XVhSvXLClGevo4qVUStBee60tFvg=; b=J8I6OgG4yK64MYUVV3p0iaHxs/3GpP91jZfikVKcQBZn3XTtvbyiGpGPIF/GuHqozn bxzoz00vjXlc2g/yTmEcfwnCt3Wk1wu8qYevABdr+o3ryKyoU/7P/rqO0Krgc4081hdK L5/noIUY97aaduO/u39v0BQjpG0KbSqE5dGdUPIgR3eOQocTz7j/GFYV6GLmc5BtKeZw Gu6RhOND6QJeC703/+MXq9nGFi7TP9Lz8YYtMHlm5+jPTwnHSaMl/so0HtQ1MrByBMrE 1q6xKalw5yb9bC7OUhJZIqN/es/qm9t0HUtDdUX6FZ3ttMHwN2INT7ZOte9O9NnPNsJp YErQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yxaajrT8hw/p9R5XVhSvXLClGevo4qVUStBee60tFvg=; b=Mj7PEMPzgh8VcFgJzNv9LFGFfCQ1/5F3VmwwDnjTeF7pX5lcAuK37hJN4ssxLq8ove Bsn0pzqgzn2d2/8h+BsAD5oEnu5D9ebLcf/0zGMgJQSkpLfRnh8Hf0hnM4nt177bD49d TCKRHPJFPGskE8J0QJrlxqhLLNfNHVEwbdQEgP7WybtcoQT5jbvLPqwdbZ9Et04kNy5p jD/+RfvAwXr+5Sj0OeerMMjYvrEoTwpRhmW3kwmqen+fWiVPv6yRGfPoFbw/yu6UDmSX kQl/qZk69DRlDp+Hkefdu47FXIRhYEr2gc/KWS8hCHiojKam79RmDZb34J8tyFJimOnV nnmw== X-Gm-Message-State: AO0yUKWa8Ln12ZgMxzJjwdbU8Qm6JhjPVaVMO4ZugmPiRzJ3K2mvT8qD Ya+zXmEarWynwUqcS+QOpnXUj+qhjbrk8/3U X-Google-Smtp-Source: AK7set/7egwm7XJz8uEoFGVH+93YcCtT7DrnsfgoTamJjPoiqn14WZozrG+4Ln4cQ2kpRJA/wPc2gg== X-Received: by 2002:a7b:c85a:0:b0:3d2:392e:905f with SMTP id c26-20020a7bc85a000000b003d2392e905fmr9589877wml.24.1675434572659; Fri, 03 Feb 2023 06:29:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility Date: Fri, 3 Feb 2023 14:28:58 +0000 Message-Id: <20230203142927.834793-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434755369100001 Content-Type: text/plain; charset="utf-8" From: Evgeny Iakovlev Previous change slightly modified the way we handle data writes when FIFO is disabled. Previously we kept incrementing read_pos and were storing data at that position, although we only have a single-register-deep FIFO now. Then we changed it to always store data at pos 0. If guest disables FIFO and the proceeds to read data, it will work out fine, because we still read from current read_pos before setting it to 0. However, to make code less fragile, introduce a post_load hook for PL011State and move fixup read FIFO state when FIFO is disabled. Since we are introducing a post_load hook, also do some sanity checking on untrusted incoming input state. Signed-off-by: Evgeny Iakovlev Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell --- hw/char/pl011.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 3fa3b75d042..05e8bdc050e 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -352,10 +352,35 @@ static const VMStateDescription vmstate_pl011_clock = =3D { } }; =20 +static int pl011_post_load(void *opaque, int version_id) +{ + PL011State* s =3D opaque; + + /* Sanity-check input state */ + if (s->read_pos >=3D ARRAY_SIZE(s->read_fifo) || + s->read_count > ARRAY_SIZE(s->read_fifo)) { + return -1; + } + + if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0)= { + /* + * Older versions of PL011 didn't ensure that the single + * character in the FIFO in FIFO-disabled mode is in + * element 0 of the array; convert to follow the current + * code's assumptions. + */ + s->read_fifo[0] =3D s->read_fifo[s->read_pos]; + s->read_pos =3D 0; + } + + return 0; +} + static const VMStateDescription vmstate_pl011 =3D { .name =3D "pl011", .version_id =3D 2, .minimum_version_id =3D 2, + .post_load =3D pl011_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32(readbuff, PL011State), VMSTATE_UINT32(flags, PL011State), --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675435021; cv=none; d=zohomail.com; s=zohoarc; b=YJ8bHVFj8m8Eig/yeTKjp7CQEolgbI+CZLDczp+3nTVS8VFKkXQHtRxDP5s16XLG2YJ+GfJE38Ub5UDM9C9+71Rv/54dqSrf0x6Eqfi2jffhp0MZZRc7Wd4RYKHUcATwDX+qZDHnbRT2Q5QMVKrBG9RiQRP1JjGG+wDJPxyrmdA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675435021; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kl1m+bg2bq062qmRTd0sPieM4oFZq05ngUG4exabYiE=; b=G2E7c40FDkiBPqJZddhEUqJ1JiCMETP0Nkl5ilE/XdaMYHgxOfl6tb7JnoNTGonfyNf42RaST+tGUwdB1Qvd1fs+rgK8mrWc3bmoOcJdm+q7iBbk+wAlxQU2nL8L4b/MyyzCr0yLwljV4jNQH+awQQclCy1mpGaJzHliCz2m8F8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675435021476820.5236249639986; Fri, 3 Feb 2023 06:37:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4W-0006gJ-2P; Fri, 03 Feb 2023 09:29:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4N-0006db-3d for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:40 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4J-00054S-5m for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:36 -0500 Received: by mail-wm1-x329.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so6153045wma.1 for ; Fri, 03 Feb 2023 06:29:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kl1m+bg2bq062qmRTd0sPieM4oFZq05ngUG4exabYiE=; b=vRIphZWTyMirEag0ZByn3ahSC+LS3YF5LTF8PEW944bS+7rz6vquIpNk11tce3yYSF /EifeI8X4YS2x+Ju5pK+pQ8NITXhZNPZ8MHwoZuKXcjAoVO7weyMArfEg6syA4MTKIQW MMR4Q5e31SkniAX4ZiSYtbEbPz4v++3RSV4H6SbIDemrOlwmWnhytmKlNiGYThFA+ZoB HfniOlAJwVGYxfQwFlO3fx6j92pxGc6ZuPG9F//n0ptcLZGfnONL35eOBSRjH5g3jJfO FqeDT+EGqOotjuT5+3PDIDZ245yWLgRlwizFIPN0fsGuyqtczy5tpnST0TvWJWrrOXgK bPpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kl1m+bg2bq062qmRTd0sPieM4oFZq05ngUG4exabYiE=; b=GksWlQ3ja7q1fOoxrB0bdr0jpeNc+a60Awu9dOud/6MemtlL/DCjiw7Ri6ZhqYv3aT DdASa6E55UZoed27F54g9kv+zTt1aQQvxCxQu10E4NPL4A7tZD7iU7lVsXXa/lCqZzgx 5CSnXlfSN/lCk5n5iF41bUvbXT4mVQtN2YPdIqSzRGB5QD1nGBRTSfcQ7TOeItaZt41x 5Jro5uxJt7u8cR3XovZecifGqvd3k9xGAyREtiGYIYFw45HomJzSlQ64g6Fd8q4BZsnO excvgDtYsQ1OheBQTw9Oo955d35ApEPRof8GbvMN7PmWdx0zkSgRZXcLjyi78Ja4FIvk hqxQ== X-Gm-Message-State: AO0yUKXnu668xb1m+EoS5z89N3jUvLFracBi3NczFmWFxo3LKUyAiq85 LoNFuG8SxATkyflMbUfLJwtDv99xoiisYGws X-Google-Smtp-Source: AK7set8QSIEqqGuCwBgSy2N9GBZ1nSN06PLf0dQ69aFSvLR2ClAV3zjad3k1TWAz8yNkfIkO8LfQvA== X-Received: by 2002:a1c:4c17:0:b0:3db:262a:8ef with SMTP id z23-20020a1c4c17000000b003db262a08efmr10095638wmf.38.1675434573525; Fri, 03 Feb 2023 06:29:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/33] hw/char/pl011: implement a reset method Date: Fri, 3 Feb 2023 14:28:59 +0000 Message-Id: <20230203142927.834793-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675435022294100002 From: Evgeny Iakovlev PL011 currently lacks a reset method. Implement it. Signed-off-by: Evgeny Iakovlev Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell --- hw/char/pl011.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 05e8bdc050e..ca7537d8ed2 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -427,11 +427,6 @@ static void pl011_init(Object *obj) s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, = s, ClockUpdate); =20 - s->read_trigger =3D 1; - s->ifl =3D 0x12; - s->cr =3D 0x300; - s->flags =3D 0x90; - s->id =3D pl011_id_arm; } =20 @@ -443,11 +438,32 @@ static void pl011_realize(DeviceState *dev, Error **e= rrp) pl011_event, NULL, s, NULL, true); } =20 +static void pl011_reset(DeviceState *dev) +{ + PL011State *s =3D PL011(dev); + + s->lcr =3D 0; + s->rsr =3D 0; + s->dmacr =3D 0; + s->int_enabled =3D 0; + s->int_level =3D 0; + s->ilpr =3D 0; + s->ibrd =3D 0; + s->fbrd =3D 0; + s->read_pos =3D 0; + s->read_count =3D 0; + s->read_trigger =3D 1; + s->ifl =3D 0x12; + s->cr =3D 0x300; + s->flags =3D 0x90; +} + static void pl011_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 dc->realize =3D pl011_realize; + dc->reset =3D pl011_reset; dc->vmsd =3D &vmstate_pl011; device_class_set_props(dc, pl011_properties); } --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434701; cv=none; d=zohomail.com; s=zohoarc; b=YIUHw9rPQkBBy89Bsjppb6Nw1vqMDkaHUv2dcgBYsN5FyFKBRLj9KPHpo2+3UyhEH/787vTtNVHcmktf+4MBx3S5SsW13SQ+LcJF/6hq8Piy9zOt6XE62M2pkuu3fuIIRqK7+C7brMe1K1FwyMh1BekV+EFIvq1l4fwbN+/zw3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434701; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vPVJCWB3C3sZSgsGNanDCbKT7SX6LCAO601kW+euxik=; b=Rm2q8C7nPCo47pvq3HkMPJWKF/bKXrAD9wLkEB6C/1cThN1uFIBG6soFj70NKOp09vGNokSk747w+9FSdi5OeGKMONL4SCI3mUe27OyTZL+AH1UBP0KhMLMA0MXYJ0oiaua0Wjv1DmVHlsTKExPM7MLYi2Tmigd+KEUs7UJ0aBE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434701384329.51579745483946; Fri, 3 Feb 2023 06:31:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4d-0006jQ-RD; Fri, 03 Feb 2023 09:29:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4T-0006f4-Fq for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:46 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4K-00054x-87 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:40 -0500 Received: by mail-wr1-x42b.google.com with SMTP id j25so1277741wrc.4 for ; Fri, 03 Feb 2023 06:29:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vPVJCWB3C3sZSgsGNanDCbKT7SX6LCAO601kW+euxik=; b=FpBIaM3XdddGB2IqZS6R6yqeKLqK6EJv9gHWvP6NcL8r8e3HrOK+f7xwhPDegBBZxE 7bgdmGRo5q/qvcuhZq4lcYYVDUSbovpuFFy2DEsT3qDQBVx1lpXRosPD1dFpJqpzJSIQ gGWEccvvUpTR+0lBRLh1+pMGRrpDe0WmR9BQgosv0saE9wwejkuAS/6MhYeNhngRw2aR ZQxPayLjM9eu0jvGBoXR3fOASwhJTDaiaX7VIWbsCbskpBMAMHQGn+9cK0BMRIl0HPYj 0oVrGK9zam2EVoxb5lgtrqdrsNpLPPlikgMjjHYGcRi5sO/slugTCQUlB1n/1V3HZZLw fA/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vPVJCWB3C3sZSgsGNanDCbKT7SX6LCAO601kW+euxik=; b=QwuKdKfgEVT8uCpSMmlaqZVHRgUC/Lo2rd+Kme9EIYpH35Qfuzb6IKvnP9bqQifEr+ FReG7KDhqlo77llb5VZ9ffY9m2FPaqCdpePtrAREIvp3op6yuQRlwxmcsfExxfJOq41Y aCewqYiHMRneWSNO6RgX4X0ow2Jcp8b+xn+YXWA4pS+K+2QX+X3kQftRtWXjm0j2wPsE o1uW5uo7H1iEaq2lGRHCDlgbb6FersYviu8sxQFziTqYpT/Wx52nI4n2S2rUKMG8bvBF pKEhiS8thuh6C9dz/8eaTUa1PxQUnjqOx6wmuEGQ38RngUuION0m46Ne5RsC7WeqcD2e NpqA== X-Gm-Message-State: AO0yUKXAOGvhNZpQ2Qwa7r/wJBZNXnTs+qYnZe38Wmo+C+xVvVb7bpHg SULdkvon6l291Pnr7ufYTxg/ciF6cIzFWpTQ X-Google-Smtp-Source: AK7set8JjjZnBojYAoZb036LVdh5Ta9k6ZTCZqi4fP63my9/p4AadujjH6zMH5cnZS1RKX2JWnBABQ== X-Received: by 2002:a5d:5092:0:b0:2bf:9468:340 with SMTP id a18-20020a5d5092000000b002bf94680340mr7874118wrt.19.1675434574257; Fri, 03 Feb 2023 06:29:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset Date: Fri, 3 Feb 2023 14:29:00 +0000 Message-Id: <20230203142927.834793-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434703056100003 Content-Type: text/plain; charset="utf-8" From: Evgeny Iakovlev Current FIFO handling code does not reset RXFE/RXFF flags when guest resets FIFO by writing to UARTLCR register, although internal FIFO state is reset to 0 read count. Actual guest-visible flag update will happen only on next data read or write attempt. As a result of that any guest that expects RXFE flag to be set (and RXFF to be cleared) after resetting FIFO will never see that happen. Signed-off-by: Evgeny Iakovlev Reviewed-by: Peter Maydell Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell --- hw/char/pl011.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index ca7537d8ed2..c15cb7af20b 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -92,6 +92,16 @@ static inline unsigned pl011_get_fifo_depth(PL011State *= s) return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; } =20 +static inline void pl011_reset_fifo(PL011State *s) +{ + s->read_count =3D 0; + s->read_pos =3D 0; + + /* Reset FIFO flags */ + s->flags &=3D ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF); + s->flags |=3D PL011_FLAG_RXFE | PL011_FLAG_TXFE; +} + static uint64_t pl011_read(void *opaque, hwaddr offset, unsigned size) { @@ -239,8 +249,7 @@ static void pl011_write(void *opaque, hwaddr offset, case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & 0x10) { - s->read_count =3D 0; - s->read_pos =3D 0; + pl011_reset_fifo(s); } if ((s->lcr ^ value) & 0x1) { int break_enable =3D value & 0x1; @@ -450,12 +459,11 @@ static void pl011_reset(DeviceState *dev) s->ilpr =3D 0; s->ibrd =3D 0; s->fbrd =3D 0; - s->read_pos =3D 0; - s->read_count =3D 0; s->read_trigger =3D 1; s->ifl =3D 0x12; s->cr =3D 0x300; - s->flags =3D 0x90; + s->flags =3D 0; + pl011_reset_fifo(s); } =20 static void pl011_class_init(ObjectClass *oc, void *data) --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434801; cv=none; d=zohomail.com; s=zohoarc; b=Oljh5Ys7aKgA9Iado45NY8r75NHqrLI1iJw6DJyhFS78lbbVdAhjG/KrnVfTBJMlSczoz4Qo+dpR1paSOn97v+gjJSDpy2qDuPqBwoY1PgOqjpmM7h/p3lkKsgLNlun2gKSByTCU4Xy24VIpxB0jYtirPQLf5IZOPp9qhrMvU/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434801; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xjR2XR977p7LFkCyD/RSl9r6hvoh3VT3zTXhEMUsJd8=; b=OqebKgBTA0lnjFrlQM4O4Wxa7c8tt/95bICPvQhUWYOU1HtdI04fBvuH1V+ZsTK4tjXN8CKrFbpUOdqnCB89Hp6iOh4AgfWx8SwdAPpgvVHIkas5CpRENMdk+geeHMjs1ZHa6qXmCP9vvXXUmCUNo4AzswIAjNmaQ26M6hxHJFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434801633443.8077277175481; Fri, 3 Feb 2023 06:33:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4W-0006gi-P1; Fri, 03 Feb 2023 09:29:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4S-0006f3-Nw for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:45 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4K-00053d-Ex for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:40 -0500 Received: by mail-wm1-x333.google.com with SMTP id q8so3999749wmo.5 for ; Fri, 03 Feb 2023 06:29:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xjR2XR977p7LFkCyD/RSl9r6hvoh3VT3zTXhEMUsJd8=; b=ru7LF32+GMvqBKUzoUsMR6hQDS6MrPomUhCpMiIu4ZoAFFr66bVMlWYFkCS6hh23Iw IgLAYpMS+il8iceVds/doOrOhUiCA7VHmX38VvX9QiY5FUj/qTC8PE4bM6EQcK/R6hFG aMRDrdX/X3VY37PV2zzlcFQTxnf4/Cihh8DHkK4QhaRzz6JiPtsYP6YLBanT+G4F7Exq D7Bn1FryShyN/VXvl8KBK1VBBeOP/dpQPqBfPSG/Gm9X0nMpG3+Nws4ck96Fv0b1P0E+ fpWS851tzn2Bz4jkGJxbnUef3EWyz3h9C9XywAtamcN7bQ2LsK5KrBWCVUlnCWM2U6jT aRvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xjR2XR977p7LFkCyD/RSl9r6hvoh3VT3zTXhEMUsJd8=; b=DNa5IS2sM7cpO13Z2BXF8TQhoR7SUAjhKEu+8nrEpkNoUQAABnSmtRYmIBo1kLrhHb K3UQmHvUDQ5RWPUiIiDcfORCV1cPiHJfBm3/Cr0qI3bJj3Sp8DP8Bc+H3UdI0z7q+Mjx CXfzi4owN4u4lpKaeYzRXqPjkywMQ5HusJ5Ds8m7uik1krRTusejDav7mppd7FIJXn7S 9U3bioAdw7UU1yaYDfJXnfs7iOPkRQ32JfjT9DHB+t9RRkK3WPxxY5+51RARR+RwYrrL 3bc+p1Si/6eSzetpIZno+3rw78mVH0Dbiuq9eRx3k1fqXKUDLnMheJKUqgBro5GLpLiQ F8iA== X-Gm-Message-State: AO0yUKWnS3hMnP6ab2Rw1mNE+YL4NbZsMFpnewdVbKyLdmd1g3eri9sn tTF33Uot5Tms6uAnoCccAsF6BoRzmLWseKxb X-Google-Smtp-Source: AK7set9gEhVPQLpmlLdH+cMlkKz/LF/pILwEzgix4el7KrNrvy/ssdEZz4tPHk5SgkL2P6rfIhiVPQ== X-Received: by 2002:a7b:ce85:0:b0:3dc:50c2:cc1 with SMTP id q5-20020a7bce85000000b003dc50c20cc1mr10069615wmj.23.1675434575021; Fri, 03 Feb 2023 06:29:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/33] hvf: arm: Add support for GICv3 Date: Fri, 3 Feb 2023 14:29:01 +0000 Message-Id: <20230203142927.834793-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434803660100001 Content-Type: text/plain; charset="utf-8" From: Alexander Graf We currently only support GICv2 emulation. To also support GICv3, we will need to pass a few system registers into their respective handler functions. This patch adds support for HVF to call into the TCG callbacks for GICv3 system register handlers. This is safe because the GICv3 TCG code is generic as long as we limit ourselves to EL0 and EL1 - which are the only modes supported by HVF. To make sure nobody trips over that, we also annotate callbacks that don't work in HVF mode, such as EL state change hooks. With GICv3 support in place, we can run with more than 8 vCPUs. Signed-off-by: Alexander Graf Message-id: 20230128224459.70676-1-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 16 +++- target/arm/hvf/hvf.c | 151 ++++++++++++++++++++++++++++++++++++ target/arm/hvf/trace-events | 2 + 3 files changed, 168 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index b17b29288c7..9a7fc190994 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -21,6 +21,8 @@ #include "hw/irq.h" #include "cpu.h" #include "target/arm/cpregs.h" +#include "sysemu/tcg.h" +#include "sysemu/qtest.h" =20 /* * Special case return value from hppvi_index(); must be larger than @@ -2810,6 +2812,8 @@ void gicv3_init_cpuif(GICv3State *s) * which case we'd get the wrong value. * So instead we define the regs with no ri->opaque info, and * get back to the GICv3CPUState from the CPUARMState. + * + * These CP regs callbacks can be called from either TCG or HVF co= de. */ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); =20 @@ -2905,6 +2909,16 @@ void gicv3_init_cpuif(GICv3State *s) define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo); } } - arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs); + if (tcg_enabled() || qtest_enabled()) { + /* + * We can only trap EL changes with TCG. However the GIC inter= rupt + * state only changes on EL changes involving EL2 or EL3, so f= or + * the non-TCG case this is OK, as EL2 and EL3 can't exist. + */ + arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, c= s); + } else { + assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2)); + assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); + } } } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 060aa0ccf4b..ad65603445e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -80,6 +80,33 @@ #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) =20 +#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) +#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) +#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) +#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) +#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) +#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) +#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) +#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) +#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) +#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) +#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) +#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) +#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) +#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) +#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) +#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) +#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) +#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) +#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) +#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) +#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) +#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) +#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) +#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) +#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) +#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) + #define WFX_IS_WFE (1 << 0) =20 #define TMR_CTL_ENABLE (1 << 0) @@ -788,6 +815,43 @@ static bool is_id_sysreg(uint32_t reg) SYSREG_CRM(reg) < 8; } =20 +static uint32_t hvf_reg2cp_reg(uint32_t reg) +{ + return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, + (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, + (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, + (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, + (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, + (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); +} + +static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const ARMCPRegInfo *ri; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + if (ri) { + if (ri->accessfn) { + if (ri->accessfn(env, ri, true) !=3D CP_ACCESS_OK) { + return false; + } + } + if (ri->type & ARM_CP_CONST) { + *val =3D ri->resetvalue; + } else if (ri->readfn) { + *val =3D ri->readfn(env, ri); + } else { + *val =3D CPREG_FIELD64(env, ri); + } + trace_hvf_vgic_read(ri->name, *val); + return true; + } + + return false; +} + static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); @@ -839,6 +903,36 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg= , uint32_t rt) case SYSREG_OSDLR_EL1: /* Dummy register */ break; + case SYSREG_ICC_AP0R0_EL1: + case SYSREG_ICC_AP0R1_EL1: + case SYSREG_ICC_AP0R2_EL1: + case SYSREG_ICC_AP0R3_EL1: + case SYSREG_ICC_AP1R0_EL1: + case SYSREG_ICC_AP1R1_EL1: + case SYSREG_ICC_AP1R2_EL1: + case SYSREG_ICC_AP1R3_EL1: + case SYSREG_ICC_ASGI1R_EL1: + case SYSREG_ICC_BPR0_EL1: + case SYSREG_ICC_BPR1_EL1: + case SYSREG_ICC_DIR_EL1: + case SYSREG_ICC_EOIR0_EL1: + case SYSREG_ICC_EOIR1_EL1: + case SYSREG_ICC_HPPIR0_EL1: + case SYSREG_ICC_HPPIR1_EL1: + case SYSREG_ICC_IAR0_EL1: + case SYSREG_ICC_IAR1_EL1: + case SYSREG_ICC_IGRPEN0_EL1: + case SYSREG_ICC_IGRPEN1_EL1: + case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_SGI0R_EL1: + case SYSREG_ICC_SGI1R_EL1: + case SYSREG_ICC_SRE_EL1: + case SYSREG_ICC_CTLR_EL1: + /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ + if (!hvf_sysreg_read_cp(cpu, reg, &val)) { + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + } + break; default: if (is_id_sysreg(reg)) { /* ID system registers read as RES0 */ @@ -944,6 +1038,33 @@ static void pmswinc_write(CPUARMState *env, uint64_t = value) } } =20 +static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const ARMCPRegInfo *ri; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + + if (ri) { + if (ri->accessfn) { + if (ri->accessfn(env, ri, false) !=3D CP_ACCESS_OK) { + return false; + } + } + if (ri->writefn) { + ri->writefn(env, ri, val); + } else { + CPREG_FIELD64(env, ri) =3D val; + } + + trace_hvf_vgic_write(ri->name, val); + return true; + } + + return false; +} + static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); @@ -1021,6 +1142,36 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t = reg, uint64_t val) case SYSREG_OSDLR_EL1: /* Dummy register */ break; + case SYSREG_ICC_AP0R0_EL1: + case SYSREG_ICC_AP0R1_EL1: + case SYSREG_ICC_AP0R2_EL1: + case SYSREG_ICC_AP0R3_EL1: + case SYSREG_ICC_AP1R0_EL1: + case SYSREG_ICC_AP1R1_EL1: + case SYSREG_ICC_AP1R2_EL1: + case SYSREG_ICC_AP1R3_EL1: + case SYSREG_ICC_ASGI1R_EL1: + case SYSREG_ICC_BPR0_EL1: + case SYSREG_ICC_BPR1_EL1: + case SYSREG_ICC_CTLR_EL1: + case SYSREG_ICC_DIR_EL1: + case SYSREG_ICC_EOIR0_EL1: + case SYSREG_ICC_EOIR1_EL1: + case SYSREG_ICC_HPPIR0_EL1: + case SYSREG_ICC_HPPIR1_EL1: + case SYSREG_ICC_IAR0_EL1: + case SYSREG_ICC_IAR1_EL1: + case SYSREG_ICC_IGRPEN0_EL1: + case SYSREG_ICC_IGRPEN1_EL1: + case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_SGI0R_EL1: + case SYSREG_ICC_SGI1R_EL1: + case SYSREG_ICC_SRE_EL1: + /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ + if (!hvf_sysreg_write_cp(cpu, reg, val)) { + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + } + break; default: cpu_synchronize_state(cpu); trace_hvf_unhandled_sysreg_write(env->pc, reg, diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events index 820e8e02979..4fbbe4b45ec 100644 --- a/target/arm/hvf/trace-events +++ b/target/arm/hvf/trace-events @@ -9,3 +9,5 @@ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64 hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64 hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [= ec=3D0x%x pc=3D0x%"PRIx64"]" hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t= cpuid) "PSCI Call x0=3D0x%016"PRIx64" x1=3D0x%016"PRIx64" x2=3D0x%016"PRIx= 64" x3=3D0x%016"PRIx64" cpu=3D0x%x" +hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=3D0x= %016"PRIx64"]" +hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=3D0x= %016"PRIx64"]" --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434656; cv=none; d=zohomail.com; s=zohoarc; b=Rol0sa0MU3uJ/jDrETPUakvmy7Skon9deDHfl8EybQftxcIMH/j52CmfgY8muXFia26Q9f2ysHZgMQhebhsPMrVeITGQ/WvReFvLECxGw2nduyeO7NsBslqHu8EJCqjXMwii0IZyIxeVpDYMh6n9E5R4guvPQQTQSaPa27fHaqg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434656; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XxpRepMJTovvA+isBKIvWPf2Mb0oogTF5j2Y5fZGMUU=; b=MQVBAjAZyQ5KM0wRbDG+OAuMqihc+4NNtuWBHhzOcG3WG6eAb1xqzT6QDJRSGqcNfDUrt3HaR2u3nkOxA35I/Pi3b+Hln3j2x/eLNzjC87A3lMJwi0NL6Rc9LlKAnKwYEiqO9oNC+yBWIAGxKRjGWpy0W2BKK1/M98BowHEcHhQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434656984795.5603720480376; Fri, 3 Feb 2023 06:30:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4d-0006jR-RQ; Fri, 03 Feb 2023 09:29:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4U-0006fR-Mm for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:46 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4M-00055K-T2 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:43 -0500 Received: by mail-wm1-x32c.google.com with SMTP id j29-20020a05600c1c1d00b003dc52fed235so4005581wms.1 for ; Fri, 03 Feb 2023 06:29:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=XxpRepMJTovvA+isBKIvWPf2Mb0oogTF5j2Y5fZGMUU=; b=YwOWfy6VyhNuaVP/DEUZPqtZJkqhYO3GDZyIov9FheIwMWJJkGSCZkUbIb6gv5TrnB FHbtsCZnwVeZZKFtNg/q3sEeR0Y278AEjtqAVHwrIZkAat3XMae/9RU9EjSsQeI+uNQh YqaAypzFex6nYULV4Y6TA2A1Uq4Wg8OFxPjW7LAyRlG7hvJFMpyP9EEO1XDrYi/aQ3yz HZEbWfRgV5eQdSUPA9JqxWa2wVQPEvpm1UZJ3jcOO93Prm8kZo7G47N+gxUor8l4z7jj k998XfpY9J/bYfgyDcMoP+77AS6tvN1+cs1PebzawNLiPtOpIg0xhVX4tC+o5UYybB9F Jdpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XxpRepMJTovvA+isBKIvWPf2Mb0oogTF5j2Y5fZGMUU=; b=A0g86WK9SJlWA27eEJo46tTb/5Lla+56I5w1UaceiTbAvZu9qqswl20rvCQAyUnYQn X8fSLvVDSkfl9OkhQiGuA5Ha+qupTd4925bPg11dOt2LAfOxF3VmfhaibV018idUmX8t XOHQwqAFSU2FhlM/Eht2xKYiINENiCoBlgmDrihb2hMGqTxpCQ9kKINpsmAJzZRbJAfC JFm0dw2afCS/EHlkOISMTdpYJ04Hu82pJbR0X6f3pjGqK6uqEuE5ZgptjAZy5i8H1R9w yihwaDaGd58L4F4qtWcHj5GFb8qAMP2RoVBbFhxPGvt6GquhfPlYcYFLBoRXPtmB6lfq BVVQ== X-Gm-Message-State: AO0yUKXD/DQZNT1v7MAQk2Kv80L4Af1EQK74UhydFK3xVH+EStw1QzOi 1JjDQoFxlBPPtItY7zPoxz7szOhcpMKQysi+ X-Google-Smtp-Source: AK7set82JzSu+JAxlGK9tqiprP3f7zw7BMlmfVQ9lfCZUf7+JWq0M2sNAbq5UZPUWc9r86HPanTF4A== X-Received: by 2002:a7b:ca54:0:b0:3dc:2b62:ee9f with SMTP id m20-20020a7bca54000000b003dc2b62ee9fmr10009573wml.3.1675434575851; Fri, 03 Feb 2023 06:29:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic Date: Fri, 3 Feb 2023 14:29:02 +0000 Message-Id: <20230203142927.834793-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434658834100003 Content-Type: text/plain; charset="utf-8" From: Alexander Graf Up to now, the finalize_gic_version() code open coded what is essentially a support bitmap match between host/emulation environment and desired target GIC type. This open coding leads to undesirable side effects. For example, a VM with KVM and -smp 10 will automatically choose GICv3 while the same command line with TCG will stay on GICv2 and fail the launch. This patch combines the TCG and KVM matching code paths by making everything a 2 pass process. First, we determine which GIC versions the current environment is able to support, then we go through a single state machine to determine which target GIC mode that means for us. After this patch, the only user noticable changes should be consolidated error messages as well as TCG -M virt supporting -smp > 8 automatically. Signed-off-by: Alexander Graf Reviewed-by: Richard Henderson Reviewed-by: Cornelia Huck Reviewed-by: Zenghui Yu Message-id: 20221223090107.98888-2-agraf@csgraf.de Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 15 ++-- hw/arm/virt.c | 198 ++++++++++++++++++++++-------------------- 2 files changed, 112 insertions(+), 101 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index c7dd59d7f1f..e1ddbea96be 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -109,14 +109,19 @@ typedef enum VirtMSIControllerType { } VirtMSIControllerType; =20 typedef enum VirtGICType { - VIRT_GIC_VERSION_MAX, - VIRT_GIC_VERSION_HOST, - VIRT_GIC_VERSION_2, - VIRT_GIC_VERSION_3, - VIRT_GIC_VERSION_4, + VIRT_GIC_VERSION_MAX =3D 0, + VIRT_GIC_VERSION_HOST =3D 1, + /* The concrete GIC values have to match the GIC version number */ + VIRT_GIC_VERSION_2 =3D 2, + VIRT_GIC_VERSION_3 =3D 3, + VIRT_GIC_VERSION_4 =3D 4, VIRT_GIC_VERSION_NOSEL, } VirtGICType; =20 +#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2) +#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3) +#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4) + struct VirtMachineClass { MachineClass parent; bool disallow_affinity_adjustment; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 90a7099d3b5..28c43d59fbd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1820,6 +1820,84 @@ static void virt_set_memmap(VirtMachineState *vms, i= nt pa_bits) } } =20 +static VirtGICType finalize_gic_version_do(const char *accel_name, + VirtGICType gic_version, + int gics_supported, + unsigned int max_cpus) +{ + /* Convert host/max/nosel to GIC version number */ + switch (gic_version) { + case VIRT_GIC_VERSION_HOST: + if (!kvm_enabled()) { + error_report("gic-version=3Dhost requires KVM"); + exit(1); + } + + /* For KVM, gic-version=3Dhost means gic-version=3Dmax */ + return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, + gics_supported, max_cpus); + case VIRT_GIC_VERSION_MAX: + if (gics_supported & VIRT_GIC_VERSION_4_MASK) { + gic_version =3D VIRT_GIC_VERSION_4; + } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { + gic_version =3D VIRT_GIC_VERSION_3; + } else { + gic_version =3D VIRT_GIC_VERSION_2; + } + break; + case VIRT_GIC_VERSION_NOSEL: + if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && + max_cpus <=3D GIC_NCPU) { + gic_version =3D VIRT_GIC_VERSION_2; + } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { + /* + * in case the host does not support v2 emulation or + * the end-user requested more than 8 VCPUs we now default + * to v3. In any case defaulting to v2 would be broken. + */ + gic_version =3D VIRT_GIC_VERSION_3; + } else if (max_cpus > GIC_NCPU) { + error_report("%s only supports GICv2 emulation but more than 8= " + "vcpus are requested", accel_name); + exit(1); + } + break; + case VIRT_GIC_VERSION_2: + case VIRT_GIC_VERSION_3: + case VIRT_GIC_VERSION_4: + break; + } + + /* Check chosen version is effectively supported */ + switch (gic_version) { + case VIRT_GIC_VERSION_2: + if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { + error_report("%s does not support GICv2 emulation", accel_name= ); + exit(1); + } + break; + case VIRT_GIC_VERSION_3: + if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { + error_report("%s does not support GICv3 emulation", accel_name= ); + exit(1); + } + break; + case VIRT_GIC_VERSION_4: + if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { + error_report("%s does not support GICv4 emulation, is virtuali= zation=3Don?", + accel_name); + exit(1); + } + break; + default: + error_report("logic error in finalize_gic_version"); + exit(1); + break; + } + + return gic_version; +} + /* * finalize_gic_version - Determines the final gic_version * according to the gic-version property @@ -1828,118 +1906,46 @@ static void virt_set_memmap(VirtMachineState *vms,= int pa_bits) */ static void finalize_gic_version(VirtMachineState *vms) { + const char *accel_name =3D current_accel_name(); unsigned int max_cpus =3D MACHINE(vms)->smp.max_cpus; + int gics_supported =3D 0; =20 - if (kvm_enabled()) { - int probe_bitmap; + /* Determine which GIC versions the current environment supports */ + if (kvm_enabled() && kvm_irqchip_in_kernel()) { + int probe_bitmap =3D kvm_arm_vgic_probe(); =20 - if (!kvm_irqchip_in_kernel()) { - switch (vms->gic_version) { - case VIRT_GIC_VERSION_HOST: - warn_report( - "gic-version=3Dhost not relevant with kernel-irqchip= =3Doff " - "as only userspace GICv2 is supported. Using v2 ..."); - return; - case VIRT_GIC_VERSION_MAX: - case VIRT_GIC_VERSION_NOSEL: - vms->gic_version =3D VIRT_GIC_VERSION_2; - return; - case VIRT_GIC_VERSION_2: - return; - case VIRT_GIC_VERSION_3: - error_report( - "gic-version=3D3 is not supported with kernel-irqchip= =3Doff"); - exit(1); - case VIRT_GIC_VERSION_4: - error_report( - "gic-version=3D4 is not supported with kernel-irqchip= =3Doff"); - exit(1); - } - } - - probe_bitmap =3D kvm_arm_vgic_probe(); if (!probe_bitmap) { error_report("Unable to determine GIC version supported by hos= t"); exit(1); } =20 - switch (vms->gic_version) { - case VIRT_GIC_VERSION_HOST: - case VIRT_GIC_VERSION_MAX: - if (probe_bitmap & KVM_ARM_VGIC_V3) { - vms->gic_version =3D VIRT_GIC_VERSION_3; - } else { - vms->gic_version =3D VIRT_GIC_VERSION_2; - } - return; - case VIRT_GIC_VERSION_NOSEL: - if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <=3D GIC_NCPU= ) { - vms->gic_version =3D VIRT_GIC_VERSION_2; - } else if (probe_bitmap & KVM_ARM_VGIC_V3) { - /* - * in case the host does not support v2 in-kernel emulatio= n or - * the end-user requested more than 8 VCPUs we now default - * to v3. In any case defaulting to v2 would be broken. - */ - vms->gic_version =3D VIRT_GIC_VERSION_3; - } else if (max_cpus > GIC_NCPU) { - error_report("host only supports in-kernel GICv2 emulation= " - "but more than 8 vcpus are requested"); - exit(1); - } - break; - case VIRT_GIC_VERSION_2: - case VIRT_GIC_VERSION_3: - break; - case VIRT_GIC_VERSION_4: - error_report("gic-version=3D4 is not supported with KVM"); - exit(1); + if (probe_bitmap & KVM_ARM_VGIC_V2) { + gics_supported |=3D VIRT_GIC_VERSION_2_MASK; } - - /* Check chosen version is effectively supported by the host */ - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2 && - !(probe_bitmap & KVM_ARM_VGIC_V2)) { - error_report("host does not support in-kernel GICv2 emulation"= ); - exit(1); - } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3 && - !(probe_bitmap & KVM_ARM_VGIC_V3)) { - error_report("host does not support in-kernel GICv3 emulation"= ); - exit(1); + if (probe_bitmap & KVM_ARM_VGIC_V3) { + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; } - return; - } - - /* TCG mode */ - switch (vms->gic_version) { - case VIRT_GIC_VERSION_NOSEL: - vms->gic_version =3D VIRT_GIC_VERSION_2; - break; - case VIRT_GIC_VERSION_MAX: + } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { + /* KVM w/o kernel irqchip can only deal with GICv2 */ + gics_supported |=3D VIRT_GIC_VERSION_2_MASK; + accel_name =3D "KVM with kernel-irqchip=3Doff"; + } else { + gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { - /* CONFIG_ARM_GICV3_TCG was set */ + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; if (vms->virt) { /* GICv4 only makes sense if CPU has EL2 */ - vms->gic_version =3D VIRT_GIC_VERSION_4; - } else { - vms->gic_version =3D VIRT_GIC_VERSION_3; + gics_supported |=3D VIRT_GIC_VERSION_4_MASK; } - } else { - vms->gic_version =3D VIRT_GIC_VERSION_2; } - break; - case VIRT_GIC_VERSION_HOST: - error_report("gic-version=3Dhost requires KVM"); - exit(1); - case VIRT_GIC_VERSION_4: - if (!vms->virt) { - error_report("gic-version=3D4 requires virtualization enabled"= ); - exit(1); - } - break; - case VIRT_GIC_VERSION_2: - case VIRT_GIC_VERSION_3: - break; } + + /* + * Then convert helpers like host/max to concrete GIC versions and ens= ure + * the desired version is supported + */ + vms->gic_version =3D finalize_gic_version_do(accel_name, vms->gic_vers= ion, + gics_supported, max_cpus); } =20 /* --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434671; cv=none; d=zohomail.com; s=zohoarc; b=Okvx8Fp65gqcU9kYwHdqhMvqPJZceMgWtItLWR0ve9VlCf3tfSQLZaK8Ly954twg9qYckdWxfmkfIvAXYbVRGW/jJyUTBDfKjDNDeij7b0Nn2YaD5NFdBjjTu3MnAAnqfpj8ou+YRylOglXwNXP0tzEh/LOLJEyLXVdswdJjpdM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434671; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hajMqWBba417xljX2PthUn9B4t3yYT0YWGuT0ofiAD4=; b=Q8KQDZwEYwY3FePegh99IlDyw6N8+oWTT3+3ASt5Xtyhxa8ZBIKU51Ot9GypILwPsLg7+0nhaWcPoalDzIObw4jt3E3iLqw7HTtMp8qucWFAEksPrhXWLCYOxq7YfGIQo2Kn7LTNZwZ1Bb9639GX+aMso1pUmVFeX1tWeT7iDtk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434671187131.94276201958462; Fri, 3 Feb 2023 06:31:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4d-0006jI-P8; Fri, 03 Feb 2023 09:29:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4U-0006fP-Lo for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:46 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4M-00055T-T2 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:43 -0500 Received: by mail-wm1-x336.google.com with SMTP id k16so4011794wms.2 for ; Fri, 03 Feb 2023 06:29:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hajMqWBba417xljX2PthUn9B4t3yYT0YWGuT0ofiAD4=; b=zXafyWWnS/sBsfgec+52+1yPAb5prgixQCW2hETKzQ61js4oR6oA+TDj47pC/shGvS gvtk2c8z4XEj/qnkFDw7B6vcU6K204wJPQE3F26T2YqdOYBBBKAQ7wtpDexB0Fwv5nTD SYG6w8kG1Fak8EqHgp4RXXmc8/HD3NvSOo5pv7qDQfDPcr8YD7Y+1f8/guyzN8aynwdK MICpDZynT/QvYVE37PosFyOHv7nJWQ0nYSY3PXhYLDlPmuzBT9YYr2fEBdilfVBQ6VkW DhNj+Ppf5XATy6oyjY5AYLRilwX+4D5BNnm3yZ9Vr9QAsaqMd68BErPelHAydbADy0a5 /NJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hajMqWBba417xljX2PthUn9B4t3yYT0YWGuT0ofiAD4=; b=njjEkUxtTQ8Vb+MoZdOmW1XAkP7xGeR7ZNwOmvZJT+YOJsONbPh/aJWpLI4aC7I2UQ x4MAImbJOUfivygufiM+BRCKhJQPiymjwDXEn1wSTV+UaKEs6CNyWWz4U8xEVVrCAH6O ewCom0xvspNSmpdphdN9Yrerga6p1ViPUHdDkxp9mpog1PsmMXpOF4MasW59GxHJlNnQ GMHfRe0C1S87jHub2EgxUKsqzrf1vWuscuiJwagrsGzZ41Wj9GtncI/mArtc44k+bOOA Dtyh6qxnUZh5Iumlws1RJlyPCvj/jGGkQWRqXDVpDik3yWuh/nEVe2IswgUiZSZtAs62 t+Eg== X-Gm-Message-State: AO0yUKUyLEDPFGkaAaUv1JWR+hZYCzDeYidMkKiu92svjWm0JW1AqOIM Tut9pg8DRcRUWUiiFIk7eRKke1EjpuJ5CNQq X-Google-Smtp-Source: AK7set+Hjqya6h/mOeagBoP7/kNROEH1zOB2EJiCbIhmeUXrp12eaKXIZvtAk0STL/8+y/gghXw5+g== X-Received: by 2002:a05:600c:3545:b0:3df:ea9a:21c7 with SMTP id i5-20020a05600c354500b003dfea9a21c7mr1827418wmq.33.1675434576722; Fri, 03 Feb 2023 06:29:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit Date: Fri, 3 Feb 2023 14:29:03 +0000 Message-Id: <20230203142927.834793-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434672496100003 From: Alexander Graf Let's explicitly list out all accelerators that we support when trying to determine the supported set of GIC versions. KVM was already separate, so the only missing one is HVF which simply reuses all of TCG's emulation code and thus has the same compatibility matrix. Signed-off-by: Alexander Graf Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Cornelia Huck Reviewed-by: Zenghui Yu Reviewed-by: Richard Henderson Message-id: 20221223090107.98888-3-agraf@csgraf.de [PMM: Added qtest to the list of accelerators] Signed-off-by: Peter Maydell --- hw/arm/virt.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 28c43d59fbd..ba477282885 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -47,8 +47,10 @@ #include "sysemu/numa.h" #include "sysemu/runstate.h" #include "sysemu/tpm.h" +#include "sysemu/tcg.h" #include "sysemu/kvm.h" #include "sysemu/hvf.h" +#include "sysemu/qtest.h" #include "hw/loader.h" #include "qapi/error.h" #include "qemu/bitops.h" @@ -1929,7 +1931,7 @@ static void finalize_gic_version(VirtMachineState *vm= s) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; - } else { + } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { gics_supported |=3D VIRT_GIC_VERSION_3_MASK; @@ -1938,6 +1940,9 @@ static void finalize_gic_version(VirtMachineState *vm= s) gics_supported |=3D VIRT_GIC_VERSION_4_MASK; } } + } else { + error_report("Unsupported accelerator, can not determine GIC suppo= rt"); + exit(1); } =20 /* --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434685; cv=none; d=zohomail.com; s=zohoarc; b=FOsK2ZfbLVXumeyLzKCsprz1Csj3RccvE40qWPdV6JwNCwOY34UdkQ8hNOAucaCFRCHbAJ7nwCYoglPWpnt0ye77sQpk5w4Yr63xEuPSaDJQ3wftKb25fsel0MK4jsrTyWCKXZpiPYtg8LV9ERF3JbSek76V0Eytpw/+4xjBRQ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434685; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PCE6xhlUxSVGC/HAzEQA6//gIKkr5P4027KM8duLe7Y=; b=jw6jjBR5Gm9XyJi5k3cePJ9KQqNw6hhNTmiMjIEAIbA/uSESldWpTQZvg7ujd+WaQeetEgn1a8mZedkdMY/DNDlgNHv441KmLZAFMwRWTq4K6XRUKQ2E6a1khzKtpCJp8dp3U1uykh9ebaJ4+PZ2INmChSDCvsCvijV1kJ6M1mg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434685203641.5806439205835; Fri, 3 Feb 2023 06:31:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4h-0006su-1I; Fri, 03 Feb 2023 09:29:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4U-0006fQ-Md for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:46 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4O-00055Z-Og for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:44 -0500 Received: by mail-wm1-x32f.google.com with SMTP id j29-20020a05600c1c1d00b003dc52fed235so4005652wms.1 for ; Fri, 03 Feb 2023 06:29:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PCE6xhlUxSVGC/HAzEQA6//gIKkr5P4027KM8duLe7Y=; b=smExylBu+dCWNA3iRN6G2wrNloWUa4Uctl9f5ddsyGBmSvd1wEu2psoXlRaCVlgwXN lxOaHTlobfPHw90UtMUr55q9wZkxJd8u+UQ5YejV7EEyXUAPLmy8HB0oS8wrMfHzBzl+ byjE/lJDZKRmyGn6eTv/uUYmGiBKuFH9BS9zFI63xs0gaWpCX9qpULBAxgShz1MssgOe 954oporfEtAEUUj8S2XTGLgRYxlUDGPwt3CjPaF3jaHwMAyadJ1Aaimpzzn8zwjmLsEj js+ZwEQijRwYJ7eZHVX1hFVBDlbVjIOBVgLFUpLKwiq5f730K+6m3aAZnc0oWWqKfG+E a8Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PCE6xhlUxSVGC/HAzEQA6//gIKkr5P4027KM8duLe7Y=; b=AT4PrlwhPVD+uK2Zah9r4/BlReFCx9l0XV38R008xR6TYJjya8Q8XCIkeD0y2X7gjP pqDKzu1ZBQjbYojVr661Q66lc8fgAhbQ6a8d7CfSWB1KX2YPkcw9qUHW86OBheLZIIyi 3scZO8iFTkMQeIvdi/8pxeK8uMWKz217zp10RbWcUjiuqJjxo8FA9ThYqwvvpx5eSqZM toSEGFd0jDMtyem+80UfW80OZ1UUojmzk/mu+r/s40uy8vwlW/GNwpgIiUPNITr6Mbsr ZaQOq0IIG419kFlsDfEdAT4GNojGWPwTTFl612IA0nk1h/rOCrtLH66KXWpCoXIETSbr V9LQ== X-Gm-Message-State: AO0yUKUdXK/6pM2Zxo+5T8WWTxWSqasfUPEj2TgSmS3WHXXV0H8EZSfJ BrgWrlgmU67GAFkUh4vduzdJhEtFUujwLrOe X-Google-Smtp-Source: AK7set89ukBBqbO05qOF3lfrtWqaA5ETDwxUYFFjXh7QigWABw6K5GHO3DLH3ZmspjUCBqwUhwxogA== X-Received: by 2002:a05:600c:3795:b0:3dc:561a:79e7 with SMTP id o21-20020a05600c379500b003dc561a79e7mr9541317wmr.2.1675434577609; Fri, 03 Feb 2023 06:29:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus Date: Fri, 3 Feb 2023 14:29:04 +0000 Message-Id: <20230203142927.834793-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434686728100003 From: Marcin Juszkiewicz Cortex-A76 supports 40bits of address space. sbsa-ref's memory starts above this limit. Signed-off-by: Marcin Juszkiewicz Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20230126114416.2447685-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 8378441dbb1..f778cb6d097 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -146,7 +146,6 @@ static const int sbsa_ref_irqmap[] =3D { static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), - ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("max"), }; --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675435021; cv=none; d=zohomail.com; s=zohoarc; b=WEbamUftp6Q8tXe6lhPXjwGvslr5QBRnne3/w/XWgAkjOn6JUTA+8o0NEkpPRvj3DOCGe5yDLNb2Dw0Y7rbFsMVGGcJr5brddVbKMnBXmbyie985tJ84VozHkuPcSXITLb/yONMZIc9DqUurdv58YLrzZonlleqb5pC3fqNea9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675435021; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vEB5hK/P/E0Hi1gXCAfQiABUckdVC9FZuTnsRmpcDkM=; b=Rxce+Tjlq4XmSif95VrwDBmmy6EpfEdv5ewOD8Bvp179syfIcdgTRvzIwx0SfhvbW3asabE9oxJTwVQKgfnW/pq2ObVcnXaC5yf08hstVGENtgqoKlFQoaJQHXXbRZupI4xGtBXSrJkY1g9d55u1r+FzknvVACMyh/BnTSzcfsk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675435021521507.5458837264748; Fri, 3 Feb 2023 06:37:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4h-0006tn-QZ; Fri, 03 Feb 2023 09:29:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4Y-0006hi-L2 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:52 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4Q-00055e-Ky for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:47 -0500 Received: by mail-wm1-x329.google.com with SMTP id q8so3999859wmo.5 for ; Fri, 03 Feb 2023 06:29:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vEB5hK/P/E0Hi1gXCAfQiABUckdVC9FZuTnsRmpcDkM=; b=IHm8AL62XXf9/K1Iz4qp8f9mZWq1GzrGp4pOcSlPYF6xj4wxPeUhvouyb5O7AV//Wm QpL9qdH1cTjzwvCzUhQHjXbKQCPEZVcB542h3dAfa3Y8CiDVCzxXVAJ0K1ELv2X1Muih BKtYT2zwM+OnQasHF5OkfSCsc6Uwz+XDGNEqR/maOHyAXfEcHaAhVsxKORxsuzU0HwzT G5uhEEUXDgfOtBWOpgWc7wlFNgxZil1qZBJvxgbGJVzKBA4OT3k5xaRJTRp2501GE24f RI5BnUxSmN5vZjhHmN1PdG8mZw1diOSgSDCTWnqPf6SUK9CWVjg7+aFweZfoVkaOt0m4 Ch5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vEB5hK/P/E0Hi1gXCAfQiABUckdVC9FZuTnsRmpcDkM=; b=Lh0VstW72dSZTM12AckiYV4UANbRIaHyAOUlSP+dDc4ZBGTbQiufOAUj490172nPD2 UsFas9v6O6Jq3iy+JaZfsCMMQOreVnMJqhJAWGOMCfYK0NSsw1sKRqviJoiZy4CHtq0+ chFGHU3M69rDdd9bb41k6u5OykKFGfIZey+p7Yh7WTvkIWihSD7SRroB9SRwC687WJ8V Z8kqottPjfV+Ma2vEn1J9JQzfEvsftDuDwFzXABhM8Fp/dBCXBcbSM4srbciWu2FhTYg ET3TyFYPtoS760oQRR7KPxC70TAfygjLRuVOU4E7x5Nao+cPRXCJG0OLJbk/KOoOJ285 fvgw== X-Gm-Message-State: AO0yUKXB6cosBEt/GL5iDrF+FrG58Y/A2M4DktoJa5oX19ojDW9DBfsP YFjZrozKDLYow8JV53mwkpCoYsfEFqGwWUu6 X-Google-Smtp-Source: AK7set/QfZL7Jb7+Sp3FlWxdERj2O3xPFEMqRof+zyHI7Jz/RK/94ZNuif1QbQE1WEMJzOkLkoPOxg== X-Received: by 2002:a05:600c:3d90:b0:3df:eedf:df32 with SMTP id bi16-20020a05600c3d9000b003dfeedfdf32mr162829wmb.17.1675434578414; Fri, 03 Feb 2023 06:29:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly Date: Fri, 3 Feb 2023 14:29:05 +0000 Message-Id: <20230203142927.834793-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675435022292100001 Content-Type: text/plain; charset="utf-8" The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name them AT S1E1R and AT S1E1W (which are entirely different instructions). Fix the names. (This has no guest-visible effect as the names are for debug purposes only.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-2-peter.maydell@linaro.org Message-id: 20230127175507.2895013-2-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 72b37b7cf17..ccb7d1e1712 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7734,11 +7734,11 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { =20 #ifndef CONFIG_USER_ONLY static const ARMCPRegInfo ats1e1_reginfo[] =3D { - { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + { .name =3D "AT_S1E1RP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write64 }, - { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + { .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write64 }, --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434873; cv=none; d=zohomail.com; s=zohoarc; b=AMR5ZxEoT0zNsVlpOPelWxVPPXQ1yob6CNyeib0+WwnKo6nPRO+G1pHLmaHWMeu/7h4KH+/hT3lx5FA1aGgrqapVc0q7naUwtjOkI+q4vi2V983CtJIWNdsfuEE6PEG4zXsIn6wzEf1WUTZNu33ID9HAg/tyKKVRAZytR6HWo/o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434873; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YcRN5KzcgPE4Jkd8YcnXRx6q8ttqJHp+NRxt/dZGyyI=; b=AfGxRqQZQ4M4Ch2pDBFw0aeKLEmHqLssIFjZYsqzMDG2H1nMXIKZoiEmRJHobj4aB0lfmn75yz92bmWnEa1prXsn+wNyfZqhOOYRjJuMQ6sKlY8935FF/Feb897x+SxbwtmlHrbfXWXyacSLK+92yTvP32yse8EoNRBh4fwYo6Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434873913714.7374868238464; Fri, 3 Feb 2023 06:34:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4j-0006ua-CN; Fri, 03 Feb 2023 09:30:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4Y-0006hk-M4 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:52 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4Q-00055s-LH for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:47 -0500 Received: by mail-wm1-x32a.google.com with SMTP id bg26so4031501wmb.0 for ; Fri, 03 Feb 2023 06:29:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YcRN5KzcgPE4Jkd8YcnXRx6q8ttqJHp+NRxt/dZGyyI=; b=AbmdDGlk4qmqgcQbJscQpMSnhttNdRoip+D2y16lovjDZPzYFzkPqAtdvXMuR6QmI2 CCsUHkB8drSsH/wm47WKZ5UmQRPDWxqIes9tS53ZGCoqi3RJp6EiRAz42FRlFD0pM9Mr tt4gOlXwc6yfAGETWXtxjUWawk1rjpB9iaM7DDySdEgwhflZU+oVBfPE3Tjeny96EFuP +0ZWH0ZsdHd5XQm4EGqTe+IF/J0/eC+4axy+s9mUPkquTeTiczgk7F9Mmy90vY6TbFPr 9IQO2hmJlRTwlfD95vajkJJGS6pHBfbnnxVzRyQ0jVeXSxrYTdXw28utlWJamdDyNIvX Ek1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YcRN5KzcgPE4Jkd8YcnXRx6q8ttqJHp+NRxt/dZGyyI=; b=oXWnyxlrHqZm36A3+CqyiKzRh/SeK0ZpugqOQPtf1xRSGvUebXsnuNPplfLrb1yX6k yT8GwbeWPNHFNJlyaVWwwbsZ7IdqqjITFSkoURfPdte1NTu6F4qKnwpkNXqWl9Z1GyAY BliOdZhJ/8EwBAgqYEZoJb0zFOwr8b7+WKABR9IboOKk5QkmP7bEHOsp9c1LunKq54fe R9L1ZFR8fAx5fM34ExSVYoueO+mElp5hlxmTkqDhO/9YcpDHYVI/lj3ExzbsP/wdTJdW xZKNfbiM9PPSKtfa+bdsOw12AgT/f0qDCv6/rMojE04ztr7Clo2s9rDfHot7LEXspHAw kSOQ== X-Gm-Message-State: AO0yUKVpSRiz2yS+sKKlpUtaaAxpjs2Z9UCj7O+Guy418+1boGqNViZt QdNOSvk+HPXr5oYp8tz2qUhwakd2xybLPWIO X-Google-Smtp-Source: AK7set8PEXYQMtNd2hSFgwZGWppNtm5XooC8mntXQDuDVCYGQFwVFlYsdzJOiflq1QcQGH8Q0bK0/g== X-Received: by 2002:a05:600c:4ec7:b0:3dc:5e0d:4ce7 with SMTP id g7-20020a05600c4ec700b003dc5e0d4ce7mr9786650wmq.11.1675434579209; Fri, 03 Feb 2023 06:29:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1 Date: Fri, 3 Feb 2023 14:29:06 +0000 Message-Id: <20230203142927.834793-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434874309100005 Content-Type: text/plain; charset="utf-8" The AArch32 ATS12NSO* address translation operations are supposed to trap to either EL2 or EL3 if they're executed at Secure EL1 (which can only happen if EL3 is AArch64). We implement this, but we got the syndrome value wrong: like other traps to EL2 or EL3 on an AArch32 cpreg access, they should report the 0x3 syndrome, not the 0x0 'uncategorized' syndrome. This is clear in the access pseudocode for these instructions. Fix the syndrome value for these operations by correcting the returned value from the ats_access() function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-3-peter.maydell@linaro.org Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ccb7d1e1712..6f6772d8e04 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3284,9 +3284,9 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, if (arm_current_el(env) =3D=3D 1) { if (arm_is_secure_below_el3(env)) { if (env->cp15.scr_el3 & SCR_EEL2) { - return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; + return CP_ACCESS_TRAP_EL2; } - return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; + return CP_ACCESS_TRAP_EL3; } return CP_ACCESS_TRAP_UNCATEGORIZED; } --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434604; cv=none; d=zohomail.com; s=zohoarc; b=NPbmajDmF1mmOzbVe7poN243WkEUrcaGMItpxqp4mHkx3UQlN1Pj/LECCb82DGAK+xOAxmEGr1cRB7UDUeDRxG/hry3bcrY4IUl26er64qD3JYSf4pmwmD0eJTvl30cMEIcL5Sq3vtJVybztcy2n+xxcX0P3PyjDVM1NitdOcpo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434604; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Sdt11QbukYZJY11YGNYm/awc0QmfZC+VMlPzEhlWldI=; b=bz7aP1X80mE8WXWF6iq7isd5rhphpc6H1W2ZwBUV33DpGW+IE1czBR5ja0aPfMIs9n2zCT0Xi6I/59Z+8JarjBpu7ZjlxkFpxKrVg2USAoE0+WlsWLiRyteoJEO8TpTbzi1K/vqZSK0zULza8/jUU2D5MvMlU9N1gTAs+R1o7JA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434604850218.9872338426528; Fri, 3 Feb 2023 06:30:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4h-0006sv-3R; Fri, 03 Feb 2023 09:29:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4Y-0006hl-Kr for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:52 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4S-00055y-L0 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:48 -0500 Received: by mail-wm1-x32b.google.com with SMTP id bg26so4031531wmb.0 for ; Fri, 03 Feb 2023 06:29:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Sdt11QbukYZJY11YGNYm/awc0QmfZC+VMlPzEhlWldI=; b=xXRco1L51IAQ54FA3XZBtXgDImQcDfT1e4IDAXCOzisC51ffYnt1Bno8fRfgxadu8E ZLHqHkHoWjT44tqAbmJymTQv7rqys89+I4W7uEhe4xJ8OyQqrWqY5JNULpMsr7RJR7Yb duqYjU3rfQFxGBUpEyFuyzpOTef6fh53gml2ERns3OVAimpxfamC2PeiNRbfLRAd+9Jr bO/up1oIbt+DeQLz5a0lMyh+U1KCRV6Y4Swu7jpBfNLFHKgQuD7recCxi1mQAiIIo+Q+ 9FOMq55aUXaJP/TgaHEyose9/OlK1L643V5hkklKtIrKUk/IJ6GrqZySqTmuqhFtHqMy n1iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sdt11QbukYZJY11YGNYm/awc0QmfZC+VMlPzEhlWldI=; b=y0fN/bTrDyS4OQzV4+V+T8SlpNFkbkXbe2vs32nc11y4jpBo/QjvkKccYTfQZFlLdP 5+dLj3or/m+PL6A7CXq/bfMtBh7Ug05ZP1tIUoHReP4UwtIYUzkuGSeTmpt7VnFr1R+y FAYDzI6OK4TUWuV7RC9RY65p4mc+IDWho2FmyCDvUpPndzehRF73V8cb1Daq17Y2OqGa 1/hLTOEPPTgBrhTBEaGH0TM94uGtcrLhINZwnwQYAmktzeAjvaxxdf8c12xaMl9LwHTT MGPZ2BEhoHv862Fhb1AA7LzbuTWUtjtPDuV32wrQrPRbEZ+oW582A6ikADaZiZlOjWfb J57g== X-Gm-Message-State: AO0yUKW1FVbOmFsu31JbOMUu7MsIUOfPOd2noZRfqG1CHYSgvjnH5nIv B8scen+iZYT7BOlyVQSia4wYUnTdWl0j/uLH X-Google-Smtp-Source: AK7set/TQSrvVHzod2kxyhY0GaJunIu0jPOeglJrhfFTXQWgLBwnf30uSJrKXMcVGjgB2crAy2ps6A== X-Received: by 2002:a05:600c:1e24:b0:3da:f665:5b66 with SMTP id ay36-20020a05600c1e2400b003daf6655b66mr12426685wmb.6.1675434580123; Fri, 03 Feb 2023 06:29:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} Date: Fri, 3 Feb 2023 14:29:07 +0000 Message-Id: <20230203142927.834793-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434605788100007 Content-Type: text/plain; charset="utf-8" We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2 and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in the ats_access() function, but doing so was incorrect (a bug fixed in a previous commit). There aren't any cases where we want an access function to be able to request a trap to EL2 or EL3 with a zero syndrome value, so remove these enum values. As well as cleaning up dead code, the motivation here is that we'd like to implement fine-grained-trap handling in helper_access_check_cp_reg(). Although the fine-grained traps to EL2 are always lower priority than trap-to-same-EL and higher priority than trap-to-EL3, they are in the middle of various other kinds of trap-to-EL2. Knowing that a trap-to-EL2 must always for us have the same syndrome (ie that an access function will return CP_ACCESS_TRAP_EL2 and there is no other kind of trap-to-EL2 enum value) means we don't have to try to choose which of the two syndrome values to report if the access would trap to EL2 both for the fine-grained-trap and because the access function requires it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-4-peter.maydell@linaro.org Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org --- target/arm/cpregs.h | 4 ++-- target/arm/op_helper.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7e78c2c05c6..9744179df01 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -224,10 +224,10 @@ typedef enum CPAccessResult { * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). * Note that this is not a catch-all case -- the set of cases which may * result in this failure is specifically defined by the architecture. + * This trap is always to the usual target EL, never directly to a + * specified target EL. */ CP_ACCESS_TRAP_UNCATEGORIZED =3D (2 << 2), - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 2, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 3, } CPAccessResult; =20 typedef struct ARMCPRegInfo ARMCPRegInfo; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 31f89db8997..def5d3515e2 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -673,6 +673,8 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *en= v, uint32_t key, case CP_ACCESS_TRAP: break; case CP_ACCESS_TRAP_UNCATEGORIZED: + /* Only CP_ACCESS_TRAP traps are direct to a specified EL */ + assert((res & CP_ACCESS_EL_MASK) =3D=3D 0); if (cpu_isar_feature(aa64_ids, cpu) && isread && arm_cpreg_in_idspace(ri)) { /* --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434666; cv=none; d=zohomail.com; s=zohoarc; b=KNJz3L2Qbh2ysD9IXQKLm4tIgArqifB7d4UIINsyviuJ0wac3107EwxuI73msp1aSaETyIxi2OPDcLRANspIFU9EAzkuwRNtVQCB5XaO6Id5+AvubVxBY9+G4w82bME8Yav3CrWjlgCJDEPguyQThUXAVnRHUDXfNkBpqqfMrIE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434666; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Dfm26fYv3JIUSRJGZZpIcFrn+v6yWG7PrqTs/YhXiNE=; b=T+d3q8FqQh13yv9NnBA59JmenTmVX/euUF/ov1J5cBJr21bbXKIJFveqawRGJ4qjijQA74a3Pg5WnF8WmQ1pagT5RwlSfYIfGWONc3rRyXhbc81m1gSqvGePATySJdN77ZGoPwqJALPSXZLZUf0uBh9NSarznGJ3lywGHU36rBA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434666853336.76925112566005; Fri, 3 Feb 2023 06:31:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4l-0006xE-Kb; Fri, 03 Feb 2023 09:30:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4Y-0006hn-Lx for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:52 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4U-000560-FF for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:50 -0500 Received: by mail-wm1-x32d.google.com with SMTP id q8so3999939wmo.5 for ; Fri, 03 Feb 2023 06:29:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Dfm26fYv3JIUSRJGZZpIcFrn+v6yWG7PrqTs/YhXiNE=; b=LvG8CmYM0h4lkSolWC/d3q1fmqzy3awVjQ4MK12MxKzLt5O7fDSIns4HRLyMRiseev biXPop+IHblE0JPHsirvup8HIIJY+ZVgv5tgIs+zEnYysZhqQiufFjNxaHRmg2GNZu9c 42wMIAKPArisO0X4H/2n6Z2SwuFf7QmN8bP17K2evaVmU9cEF6/e+xT74LgjyyZsyUx0 MaGK+o+W3bi/qaPrYkmKYjLvuluBMxj79sTMJBdZvnlzZ1ai9FMABUQSZWGo2TdGw9jp IF4ZlwXoaw2cbJeo8Td1bhDA+STqigFYQJphg9Fp2c/bVKLfEEJutf8nCJjcGfM6KvCa F9Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dfm26fYv3JIUSRJGZZpIcFrn+v6yWG7PrqTs/YhXiNE=; b=djdhPA7VwtuaeOqsmS9xJIP7QZpv8++utOA6GDLNcZHmsIVfhWzO8L8jaJd2afNhUh 1vXiO8vcvm63esQy/d833CV5fugULYYh5IDiQnU7hQsVj0/2kBFXzAy+QVe5WNFdUAmm fPOyD5cei/rZQURyzHMR/EEaDmaHYToJqECiLh6+LUNh+5X6QAHr/HPsHKOj7Uz2eQ2x gRaHbaEFA2LyaSZHoAil/3g5oC84QFMcQMuHRn4rJvffbmvurnqjOMrh5H7+z8NJMbv3 Wx1i+vUDEW4pw5aehS3p36SoYvd5lUSOGy1F73QzcS9C9lPsZT0qUQmxSxSVRoS4L1ag k9UQ== X-Gm-Message-State: AO0yUKWvRTr/Wxh6l81JwISjSUqy1+16powG+rW2ZXbbgjrxCqOnAiGf gkg1OwV/j9TYMLPWieY66AdH5ua2G+k7pkrV X-Google-Smtp-Source: AK7set+BDIUKdwlVcdkfRSzionBUhTwXkkjstzhMmLqdZic+crE4M2hfrhEN1n2JOjmD2O9FDnn4Bg== X-Received: by 2002:a7b:ce94:0:b0:3dc:43a0:83bb with SMTP id q20-20020a7bce94000000b003dc43a083bbmr10177557wmj.3.1675434580920; Fri, 03 Feb 2023 06:29:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier Date: Fri, 3 Feb 2023 14:29:08 +0000 Message-Id: <20230203142927.834793-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434668588100003 Content-Type: text/plain; charset="utf-8" Rearrange the code in do_coproc_insn() so that we calculate the syndrome value for a potential trap early; we're about to add a second check that wants this value earlier than where it is currently determined. (Specifically, a trap to EL2 because of HSTR_EL2 should take priority over an UNDEF to EL1, even when the UNDEF is because the register does not exist at all or because its ri->access bits non-configurably fail the access. So the check we put in for HSTR_EL2 trapping at EL1 (which needs the syndrome) is going to have to be done before the check "is the ARMCPRegInfo pointer NULL".) This commit is just code motion; the change to HSTR_EL2 handling that will use the 'syndrome' variable is in a subsequent commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-5-peter.maydell@linaro.org Message-id: 20230127175507.2895013-5-peter.maydell@linaro.org --- target/arm/translate.c | 83 +++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 365e02fb0b8..9252a464a12 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4718,6 +4718,47 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); TCGv_ptr tcg_ri =3D NULL; bool need_exit_tb; + uint32_t syndrome; + + /* + * Note that since we are an implementation which takes an + * exception on a trapped conditional instruction only if the + * instruction passes its condition code check, we can take + * advantage of the clause in the ARM ARM that allows us to set + * the COND field in the instruction to 0xE in all cases. + * We could fish the actual condition out of the insn (ARM) + * or the condexec bits (Thumb) but it isn't necessary. + */ + switch (cpnum) { + case 14: + if (is64) { + syndrome =3D syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, + isread, false); + } else { + syndrome =3D syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, + rt, isread, false); + } + break; + case 15: + if (is64) { + syndrome =3D syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, + isread, false); + } else { + syndrome =3D syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, + rt, isread, false); + } + break; + default: + /* + * ARMv8 defines that only coprocessors 14 and 15 exist, + * so this can only happen if this is an ARMv7 or earlier CPU, + * in which case the syndrome information won't actually be + * guest visible. + */ + assert(!arm_dc_feature(s, ARM_FEATURE_V8)); + syndrome =3D syn_uncategorized(); + break; + } =20 if (!ri) { /* @@ -4755,48 +4796,6 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, * Note that on XScale all cp0..c13 registers do an access check * call in order to handle c15_cpar. */ - uint32_t syndrome; - - /* - * Note that since we are an implementation which takes an - * exception on a trapped conditional instruction only if the - * instruction passes its condition code check, we can take - * advantage of the clause in the ARM ARM that allows us to set - * the COND field in the instruction to 0xE in all cases. - * We could fish the actual condition out of the insn (ARM) - * or the condexec bits (Thumb) but it isn't necessary. - */ - switch (cpnum) { - case 14: - if (is64) { - syndrome =3D syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, false); - } else { - syndrome =3D syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, false); - } - break; - case 15: - if (is64) { - syndrome =3D syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, false); - } else { - syndrome =3D syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, false); - } - break; - default: - /* - * ARMv8 defines that only coprocessors 14 and 15 exist, - * so this can only happen if this is an ARMv7 or earlier CPU, - * in which case the syndrome information won't actually be - * guest visible. - */ - assert(!arm_dc_feature(s, ARM_FEATURE_V8)); - syndrome =3D syn_uncategorized(); - break; - } - gen_set_condexec(s); gen_update_pc(s, 0); tcg_ri =3D tcg_temp_new_ptr(); --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VPoHsQyZBehpHPFgUeyHV4nrXZ51tWP4ro3jxrpAuIc=; b=yaG0Yu5edOsbec845lS2t3qRBwtEXeIORo2yyXAQD3UNqIVHBaKueJ0ppCO5rJz/Bm 2R+dvZjHAheHH5Pfl6KgP480s7w2szbTaOSnDWIxiv0PLvgoA9d/YQQdiWAHpFem5R7B d+wOKqUFyDSUOkjCN04pSlzMLp5UM6QoY/opTC3oGcG2wsM1rVAkv+/LTaKhTgH7Mk7U VLaHwxYw+iEbZd4nDhGNG8KfU0rfNWf0NjaRtgUq5Q3y6L/qy9rLNObh+AACcIuRbh42 tMHPa7dueOrG/EZj7T+F/QKKw71JtfdRElW5p4mSeQ4Vah331ESF7wisGtlsJN7SAXLA aTdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VPoHsQyZBehpHPFgUeyHV4nrXZ51tWP4ro3jxrpAuIc=; b=BBxOHXKDjJQe/a9RQTVxJ69Z9oeawjvDDPi+3mBS7Ibq9r4WLsPWET/VErpj0Mfk34 HFzXoGSMqhAtQuZu1k/p4Bmmi3JcR6Fy/xRbcHQu15itIpsKLF3Iwe8jzJxOrEGYm+Wq mCYWBfIGbWu1tGhj3TRJoZRLtIoMhMXj8rOUPfewfPtDxq6ShesyzOnvlZnWCJjXgbjT lCsdOx1XYq9pmjepH6toG7wXbFyMP5ubWtxV0R/VCNdNe/x4OhzQ1dQG9zV1CUZigsJk zYG0h6RwsnS6ddKkelrrX98NbobVa0coJsMG2sueGGv95aykiK2U1F48zQDI1XMKwpVt DK/w== X-Gm-Message-State: AO0yUKX8bbfIcaZ+2dGa+SbxyDlrL1Dlpc4pTuhNiXrBQ1bX64nHiR7a NU+onOq5eNXJpqCPpWLNHfMYES3yDED6fm+S X-Google-Smtp-Source: AK7set+zFaG7T8znvS3vHl01F49XTUeUFtJB642uZL15iPIFSvBAL0kc7Z5uj0h5EfOUvf4nJfVOhQ== X-Received: by 2002:a05:600c:3c94:b0:3da:2a78:d7a4 with SMTP id bg20-20020a05600c3c9400b003da2a78d7a4mr9665379wmb.21.1675434581761; Fri, 03 Feb 2023 06:29:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps Date: Fri, 3 Feb 2023 14:29:09 +0000 Message-Id: <20230203142927.834793-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434623963100003 Content-Type: text/plain; charset="utf-8" The HSTR_EL2 register has a collection of trap bits which allow trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor registers. The specification of these bits is that when the bit is set we should trap * EL1 accesses * EL0 accesses, if the access is not UNDEFINED when the trap bit is 0 In other words, all UNDEF traps from EL0 to EL1 take precedence over the HSTR_EL2 trap to EL2. (Since this is all AArch32, the only kind of trap-to-EL1 is the UNDEF.) Our implementation doesn't quite get this right -- we check for traps in the order: * no such register * ARMCPRegInfo::access bits * HSTR_EL2 trap bits * ARMCPRegInfo::accessfn So UNDEFs that happen because of the access bits or because the register doesn't exist at all correctly take priority over the HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the accessfn we are incorrectly always taking the HSTR_EL2 trap. There aren't many of these, but one example is the PMCR; if you look at the access pseudocode for this register you can see that UNDEFs taken because of the value of PMUSERENR.EN are checked before the HSTR_EL2 bit. Rearrange helper_access_check_cp_reg() so that we always call the accessfn, and use its return value if it indicates that the access traps to EL0 rather than continuing to do the HSTR_EL2 check. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-6-peter.maydell@linaro.org Message-id: 20230127175507.2895013-6-peter.maydell@linaro.org --- target/arm/op_helper.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index def5d3515e2..660dae696dd 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -640,10 +640,24 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *= env, uint32_t key, goto fail; } =20 + if (ri->accessfn) { + res =3D ri->accessfn(env, ri, isread); + } + /* - * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses - * to sysregs non accessible at EL0 to have UNDEF-ed already. + * If the access function indicates a trap from EL0 to EL1 then + * that always takes priority over the HSTR_EL2 trap. (If it indicates + * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicat= es + * a trap to EL2, then the syndrome is the same either way so we don't + * care whether technically the architecture says that HSTR_EL2 trap or + * the other trap takes priority. So we take the "check HSTR_EL2" path + * for all of those cases.) */ + if (res !=3D CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) =3D=3D 0) && + arm_current_el(env) =3D=3D 0) { + goto fail; + } + if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp =3D=3D 15 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { uint32_t mask =3D 1 << ri->crn; @@ -661,9 +675,6 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *en= v, uint32_t key, } } =20 - if (ri->accessfn) { - res =3D ri->accessfn(env, ri, isread); - } if (likely(res =3D=3D CP_ACCESS_OK)) { return ri; } --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434995; cv=none; d=zohomail.com; s=zohoarc; b=RsQcLvJamuNn2oNV/k8pkuEVvwn2zswcvFV9KVqIxiYa9lxxfFS1U1GHaDGI3BwbZh7kPw8cC+erYPeV2uGDnb1iDiXq5usuCV0ld+2JjdVU7AvrTmvF+EH2H/acW8QpDyGxOGJRqDSlMaOSPW0Mvw98V2ivCKYkAeOqJ1kw0hU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434995; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ywpnf7dogvfNG28omNoMIAJoanzOfNSxnC/Zz1BiDLQ=; b=f+4Fs0ibnTfZMKFMnJo/j8zYkU/Bp06WVsWbaxpkrNlOSvMm7u8iHit42UlzMvYQcxRM79ycK3bvnB0Q1OECRBoqa3GcVuk0X6WXxJkwa4GTchPmtofBYGQlY14lgi+dOpf/GQMsTHaVCrXGcSafTGWSvlwAl04JBTbAB7HlJNY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434995541697.2464240495286; Fri, 3 Feb 2023 06:36:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4g-0006rQ-DW; Fri, 03 Feb 2023 09:29:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4Y-0006hq-PS for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:52 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4U-00053h-FR for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:50 -0500 Received: by mail-wm1-x32f.google.com with SMTP id k8-20020a05600c1c8800b003dc57ea0dfeso6160546wms.0 for ; Fri, 03 Feb 2023 06:29:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ywpnf7dogvfNG28omNoMIAJoanzOfNSxnC/Zz1BiDLQ=; b=yHY6XMDbMNnNzH2YnKv+x3pCY8Lu6hJR9q0HxZ8OfpJm+ptoEIyT6iaqKxAtzh1Wku Rh9wnEkI7g2WB1F/Zzg1+tVfohrbKnIwMPUxMLeL3vF96yQN9yF5Q8RCxoHT6LzukQoP yNMTePmUQiBcucmipXGXOOW8VzQuTn2KeNIhSadtTpU3+4YT3zGvX8ot2zqYQ3Zhr42Y 0gwqphuwGk5fVRwaWpZfCyimgwZj4fKadOZiMtbYJBeSvQiFcTBafEQG8pdmLorCVDWV WGGWZ6i/Pq5Joj4c8dsTVAognOeMyRShgSoOkIvLtLYR3yNzyAY/y9NCJC4bHkJXOT6r aDqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ywpnf7dogvfNG28omNoMIAJoanzOfNSxnC/Zz1BiDLQ=; b=e7TVNdoVc21TuaEINXboebJvSB8MrOzwtyNYliqc4+jo0yI9wmWvqo/8NRfYGTvzW8 T3se1pnYM2B9BjDo+P0sszO0I0OK0j26SaS7GW2FVbPTwq2d6TO2ErfGpgXcd461+pwN VvkAnTPv/V5uovl/nFZPycz0FQAkf5aBn2DcfEUL3yT4oNaEsjbDKZx3uJNX9TKTKeEq UPCoMLuvzEWrYptMSp3M3bgWOB47Xkh/plR75+gza7vsp1Qd9/aWEOkfY7N5UszvcRWT 505jTWodWTGXMJOWlx7OocTau9ox7nzoyPothYnOJsGtF87yORlJTfkViEFZ6siEtIjZ eiTw== X-Gm-Message-State: AO0yUKWq5veUFEQ0RvrdB3Qr7Vj6UIP7EK3qokSCgw23x/3c+sGbI/G0 adPsm+s/o6/hp4QJhB7eQUZyQ0qYSJjzz0qc X-Google-Smtp-Source: AK7set/ZJ92laVxo0ch3u+FsdpXTvQ4LuMLgXOioCbCwnxc6WxXYaUPNr7nH/Aaeutd8oTHpFoTY9A== X-Received: by 2002:a05:600c:4687:b0:3db:eb0:6f6 with SMTP id p7-20020a05600c468700b003db0eb006f6mr10139201wmo.13.1675434582584; Fri, 03 Feb 2023 06:29:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 Date: Fri, 3 Feb 2023 14:29:10 +0000 Message-Id: <20230203142927.834793-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434996107100001 Content-Type: text/plain; charset="utf-8" The semantics of HSTR_EL2 require that it traps cpreg accesses to EL2 for: * EL1 accesses * EL0 accesses, if the access is not UNDEFINED when the trap bit is 0 (You can see this in the I_ZFGJP priority ordering, where HSTR_EL2 traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and HSTR_EL2 traps from EL0 are priority 15.) However, we don't get this right for EL1 accesses which UNDEF because the register doesn't exist at all or because its ri->access bits non-configurably forbid the access. At EL1, check for the HSTR_EL2 trap early, before either of these UNDEF reasons. We have to retain the HSTR_EL2 check in access_check_cp_reg(), because at EL0 any kind of UNDEF-to-EL1 (including "no such register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'") takes precedence over the trap to EL2. But we only need to do that check for EL0 now. Signed-off-by: Peter Maydell Tested-by: Fuad Tabba Reviewed-by: Richard Henderson Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org --- target/arm/op_helper.c | 6 +++++- target/arm/translate.c | 28 +++++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 660dae696dd..7797a137af6 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -658,7 +658,11 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *e= nv, uint32_t key, goto fail; } =20 - if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp =3D=3D 15 && + /* + * HSTR_EL2 traps from EL1 are checked earlier, in generated code; + * we only need to check here for traps from EL0. + */ + if (!is_a64(env) && arm_current_el(env) =3D=3D 0 && ri->cp =3D=3D 15 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { uint32_t mask =3D 1 << ri->crn; =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9252a464a12..f4bfe55158e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4760,6 +4760,32 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, break; } =20 + if (s->hstr_active && cpnum =3D=3D 15 && s->current_el =3D=3D 1) { + /* + * At EL1, check for a HSTR_EL2 trap, which must take precedence + * over the UNDEF for "no such register" or the UNDEF for "access + * permissions forbid this EL1 access". HSTR_EL2 traps from EL0 + * only happen if the cpreg doesn't UNDEF at EL0, so we do those in + * access_check_cp_reg(), after the checks for whether the access + * configurably trapped to EL1. + */ + uint32_t maskbit =3D is64 ? crm : crn; + + if (maskbit !=3D 4 && maskbit !=3D 14) { + /* T4 and T14 are RES0 so never cause traps */ + TCGv_i32 t; + DisasLabel over =3D gen_disas_label(s); + + t =3D load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2= )); + tcg_gen_andi_i32(t, t, 1u << maskbit); + tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); + tcg_temp_free_i32(t); + + gen_exception_insn(s, 0, EXCP_UDEF, syndrome); + set_disas_label(s, over); + } + } + if (!ri) { /* * Unknown register; this might be a guest error or a QEMU @@ -4788,7 +4814,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, return; } =20 - if (s->hstr_active || ri->accessfn || + if ((s->hstr_active && s->current_el =3D=3D 0) || ri->accessfn || (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) { /* * Emit code to perform further access permissions checks at --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434812; cv=none; d=zohomail.com; s=zohoarc; b=gG3/uXBQCqlo51MzkUYbooJQBQp09obcqEIlJn5HOZJcghITYZLT4aWDplCvzQkuSrrnwJKIu84TxVPqRI8fb9GMuYXINUiJ1+MF8jHdr0yBi1qEdEbHqKtbwng+l5BdP9/sFQaiUcR1Dj/7vspk15PgQBWACr+tcX/gkZpHyWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434812; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mxLk9UAVIvLrK+pxFU4lwUCPe5SiyMuXU578mmntVS4=; b=MXVSMvLO4y6ROsSFv/VzZ/zLD+t1WVzGhsOreosOq5T6XMZGJeBIC6DoA/7GVLgVsdVlXXsl/yWZqqLWUCeqsUSb20sT5sjOQo2JVbicH0IZHdqBbEJuF8b+KUg1rgPZdxdRh59DeswjDHTbflYiPKJhrbmu3LRnaLIMSXx1j90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434812623987.6660793562369; Fri, 3 Feb 2023 06:33:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4g-0006qo-7N; Fri, 03 Feb 2023 09:29:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4Y-0006hm-M1 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:52 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4U-00056G-FH for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:49 -0500 Received: by mail-wm1-x333.google.com with SMTP id j29-20020a05600c1c1d00b003dc52fed235so4005857wms.1 for ; Fri, 03 Feb 2023 06:29:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mxLk9UAVIvLrK+pxFU4lwUCPe5SiyMuXU578mmntVS4=; b=XhmwRjzK31X5R9YD1XmKUTIz6wfW8bbCzHBF/xH72qBdmi9dhHZicnAh41q4rYn34I u7qj6o8hrG1HX6rWrE5AMV1QemcP24eRo86pwan9RP2l3n22NIkRkzKk/6oXXYnrQlw1 6nlYfumTkA6x5+3iRelpkPwxOav1dCodHuj/DFqsJEPgor2sB+DNJVKNIAbIffYvp6Fi vTblwMJ+E2vLFfZ29YMCsgha1nle2uIOdi5/17hDGneuxWP/qg+ZSLSrvRAJXRKJ+1K0 1pM2B7NE8eztbFG65lVZgLDJG+mbiFAUZmEVtEEmTR5K3fOvK34s0TIUKHkoLGK3Q5fV o1Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mxLk9UAVIvLrK+pxFU4lwUCPe5SiyMuXU578mmntVS4=; b=NOiazYP2H+fcwDELKO24myJl2zrSKNC+giOoDz8OimmCxsFLF+jdMw5rQeFSvJPX6U yV9dWJyiRLMKSh3MYN0sYmVxlLmB5QKeSuoyTLCV0xaFtv9sR4mbCdG64j+giO78dUvY 2LCOm2GdG701yhPocjySBUJGM4s64AB5zmK4Z7b9cG45nTZ+ORRdjT2Dh6ARyffuEOzv Ubq/HyzhCIJey05M85MdygkPbpKi9pKMTmpJXvTJxNrNR7TeRvYhOg0hIEhX97auPJg4 VfZNDsNf1pVap3P2wsWO7LfiroJFpJWulPwTJ6LlrivB6MrfgZqsBKThP1Iu3fXbOBUF 44Bw== X-Gm-Message-State: AO0yUKWmy2GpyiPr91IYme0mgtvk8dOonDzl7BDWEJtQsTt6dI5mCgTe 8RGri6SiH/qbK7t+NuYNEct5azvMBcYnt0J7 X-Google-Smtp-Source: AK7set92DmYWoeVR3LVzJcgJyCqqn73/7ZwKI2RIb4gBxtmLTwwsGKprCtO8uzIgMPE27+XWIn30dg== X-Received: by 2002:a05:600c:4f96:b0:3cf:9844:7b11 with SMTP id n22-20020a05600c4f9600b003cf98447b11mr10832298wmq.23.1675434583478; Fri, 03 Feb 2023 06:29:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled Date: Fri, 3 Feb 2023 14:29:11 +0000 Message-Id: <20230203142927.834793-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434813684100001 Content-Type: text/plain; charset="utf-8" The HSTR_EL2 register is not supposed to have an effect unless EL2 is enabled in the current security state. We weren't checking for this, which meant that if the guest set up the HSTR_EL2 register we would incorrectly trap even for accesses from Secure EL0 and EL1. Add the missing checks. (Other places where we look at HSTR_EL2 for the not-in-v8A bits TTEE and TJDBX are already checking that we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-8-peter.maydell@linaro.org Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- target/arm/op_helper.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6f6772d8e04..66966869218 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11716,7 +11716,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState= *env, int fp_el, DP_TBFLAG_A32(flags, VFPEN, 1); } =20 - if (el < 2 && env->cp15.hstr_el2 && + if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7797a137af6..dec03310ad5 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -663,6 +663,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *en= v, uint32_t key, * we only need to check here for traps from EL0. */ if (!is_a64(env) && arm_current_el(env) =3D=3D 0 && ri->cp =3D=3D 15 && + arm_is_el2_enabled(env) && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { uint32_t mask =3D 1 << ri->crn; =20 --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434603; cv=none; d=zohomail.com; s=zohoarc; b=JI/zq/pEBcVRfNJaB+a+8v/RkG6xjsq+zVdsjXWRCEeXjrK7Ay0vQeRIcCwcNWE4mC3nszBQwc+LLiCJz2hGTdw40V/p2rHR0kSTbQ8SuhI4098OMN695EhZ7nZxI/Gj0iVgJMUWmC34f3I5Ljh4Lc67iGoGHaAGq3lK3vMxqvQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434603; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ds4xseoNfbnQ7hbgUrM03/ZlS2pNinEaEuw8bi6heWo=; b=e80ie148N1B+9BQUD5yDvAl/VkUP9tu2bx4xkVy1gWRuU0n5tYgONcHE5rhMd5exuXKEipsh12lM8EpfPdHJvyAAr9/40cC8I8Xmzg7bhEuH4gD2faIHaVPR+FwX9Besu8cl+DKveyTGkbSzIb6bnhvWQu0BrBGZtB5npzS6oSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434602910328.3679389235158; Fri, 3 Feb 2023 06:30:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4j-0006uZ-AN; Fri, 03 Feb 2023 09:30:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4a-0006i4-GV for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:53 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4U-00056P-Ft for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:50 -0500 Received: by mail-wm1-x336.google.com with SMTP id j29-20020a05600c1c1d00b003dc52fed235so4005888wms.1 for ; Fri, 03 Feb 2023 06:29:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ds4xseoNfbnQ7hbgUrM03/ZlS2pNinEaEuw8bi6heWo=; b=J51u2ruUtmj113I8FD60d1SfuDsTTxcJgdc1cC1xW1cDlRbF+WKk5b+juBXhZrt4Yc pwdfn18HRM8oyOIisUyFZhVACZAN9ZMgXvyEaFm8/Vz/LS2Sxm/E5/YSnHptsyaPFlGB sAW3ipTKHH76aGXC0O37RvUK/fkIg8OAGBwJlq30oHoTcCDFn2hbxHmV1GMT2HLFx9Mb mawc/g4szLkLfaI5B2PUUusttTUcmtS84BOFIw2PEE+ixUaxeJY6ivmoeGeZGPpr5pbh wwXstKE2F2kodiQNUxup3d3VdKOL1JW45XhUxCUcT9eFmBvY5+lyQWCEXpG57gIixqny l+tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ds4xseoNfbnQ7hbgUrM03/ZlS2pNinEaEuw8bi6heWo=; b=zIrlKHX339k6R2yIP76zLQVeVWA1SxSRtcN1gt9qWo9a0XtYLS2o1EyvsHUprS9BzB 84uBQMis83BHQjB98A0uKfzktqYRSp1K2fPJz4WpOtW2cwYGqz0oxrQ4YhP2Mxggic0V wNjE3Odfx2ISxUCvw/KHc8z+ogfWHeuWclsUCxwBKnDJY+8l3pgSMoVDgkN3AMXjtxAJ htUg/Y910OjJEiNRjYxKmYvrat/qcX8kTMXAP8i8t4jXA+WT9slm5JTlxHr7NbeGJoil 128tlYLCYLELbMOlk5y5/RJQj8Te1meTdU6YDc9NKB/qT4etP8oycD1OtOGl1uHdW+Kt nEnw== X-Gm-Message-State: AO0yUKUMR0dPXN1ECY2CL7Wv2j5NX4lrN6qQ9WzNDMPPXoO9otxzyXKM 2OAUTc1TsglH1SpfONBUAb6NAYFi35A830Nt X-Google-Smtp-Source: AK7set+BGvVNxBaWSAXOQtjlECJB1dUal9/kAEmEF3t9SK9zWAS7BS/ujA7hiWY0IOjT52NQL6aLug== X-Received: by 2002:a7b:c8c6:0:b0:3df:9858:c03b with SMTP id f6-20020a7bc8c6000000b003df9858c03bmr4694978wml.16.1675434584300; Fri, 03 Feb 2023 06:29:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/33] target/arm: Define the FEAT_FGT registers Date: Fri, 3 Feb 2023 14:29:12 +0000 Message-Id: <20230203142927.834793-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434603775100003 Content-Type: text/plain; charset="utf-8" Define the system registers which are provided by the FEAT_FGT fine-grained trap architectural feature: HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2 All these registers are a set of bit fields, where each bit is set for a trap and clear to not trap on a particular system register access. The R and W register pairs are for system registers, allowing trapping to be done separately for reads and writes; the I register is for system instructions where trapping is on instruction execution. The data storage in the CPU state struct is arranged as a set of arrays rather than separate fields so that when we're looking up the bits for a system register access we can just index into the array rather than having to use a switch to select a named struct member. The later FEAT_FGT2 will add extra elements to these arrays. The field definitions for the new registers are in cpregs.h because in practice the code that needs them is code that also needs the cpregs information; cpu.h is included in a lot more files. We're also going to add some FGT-specific definitions to cpregs.h in the next commit. We do not implement HAFGRTR_EL2, because we don't implement FEAT_AMUv1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-9-peter.maydell@linaro.org Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org --- target/arm/cpregs.h | 285 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 15 +++ target/arm/helper.c | 40 +++++++ 3 files changed, 340 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 9744179df01..cb3dc567819 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -230,6 +230,291 @@ typedef enum CPAccessResult { CP_ACCESS_TRAP_UNCATEGORIZED =3D (2 << 2), } CPAccessResult; =20 +/* Indexes into fgt_read[] */ +#define FGTREG_HFGRTR 0 +#define FGTREG_HDFGRTR 1 +/* Indexes into fgt_write[] */ +#define FGTREG_HFGWTR 0 +#define FGTREG_HDFGWTR 1 +/* Indexes into fgt_exec[] */ +#define FGTREG_HFGITR 0 + +FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) +FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1) +FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1) +FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1) +FIELD(HFGRTR_EL2, APDAKEY, 4, 1) +FIELD(HFGRTR_EL2, APDBKEY, 5, 1) +FIELD(HFGRTR_EL2, APGAKEY, 6, 1) +FIELD(HFGRTR_EL2, APIAKEY, 7, 1) +FIELD(HFGRTR_EL2, APIBKEY, 8, 1) +FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1) +FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1) +FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1) +FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1) +FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1) +FIELD(HFGRTR_EL2, CTR_EL0, 14, 1) +FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1) +FIELD(HFGRTR_EL2, ESR_EL1, 16, 1) +FIELD(HFGRTR_EL2, FAR_EL1, 17, 1) +FIELD(HFGRTR_EL2, ISR_EL1, 18, 1) +FIELD(HFGRTR_EL2, LORC_EL1, 19, 1) +FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1) +FIELD(HFGRTR_EL2, LORID_EL1, 21, 1) +FIELD(HFGRTR_EL2, LORN_EL1, 22, 1) +FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1) +FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1) +FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1) +FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1) +FIELD(HFGRTR_EL2, PAR_EL1, 27, 1) +FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1) +FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1) +FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1) +FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1) +FIELD(HFGRTR_EL2, TCR_EL1, 32, 1) +FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1) +FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1) +FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1) +FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1) +FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1) +FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1) +FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1) +FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1) +FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1) +FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1) +FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1) +FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1) +FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1) +FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1) +FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) +FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) +FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) +FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) +/* 51-53: RES0 */ +FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) +FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) +/* 56-63: RES0 */ + +/* These match HFGRTR but bits for RO registers are RES0 */ +FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) +FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1) +FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1) +FIELD(HFGWTR_EL2, APDAKEY, 4, 1) +FIELD(HFGWTR_EL2, APDBKEY, 5, 1) +FIELD(HFGWTR_EL2, APGAKEY, 6, 1) +FIELD(HFGWTR_EL2, APIAKEY, 7, 1) +FIELD(HFGWTR_EL2, APIBKEY, 8, 1) +FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1) +FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1) +FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1) +FIELD(HFGWTR_EL2, ESR_EL1, 16, 1) +FIELD(HFGWTR_EL2, FAR_EL1, 17, 1) +FIELD(HFGWTR_EL2, LORC_EL1, 19, 1) +FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1) +FIELD(HFGWTR_EL2, LORN_EL1, 22, 1) +FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1) +FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1) +FIELD(HFGWTR_EL2, PAR_EL1, 27, 1) +FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1) +FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1) +FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1) +FIELD(HFGWTR_EL2, TCR_EL1, 32, 1) +FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1) +FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1) +FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1) +FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1) +FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1) +FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1) +FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1) +FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1) +FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1) +FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1) +FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1) +FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) +FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) +FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) +FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) +FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) +FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) + +FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) +FIELD(HFGITR_EL2, ICIALLU, 1, 1) +FIELD(HFGITR_EL2, ICIVAU, 2, 1) +FIELD(HFGITR_EL2, DCIVAC, 3, 1) +FIELD(HFGITR_EL2, DCISW, 4, 1) +FIELD(HFGITR_EL2, DCCSW, 5, 1) +FIELD(HFGITR_EL2, DCCISW, 6, 1) +FIELD(HFGITR_EL2, DCCVAU, 7, 1) +FIELD(HFGITR_EL2, DCCVAP, 8, 1) +FIELD(HFGITR_EL2, DCCVADP, 9, 1) +FIELD(HFGITR_EL2, DCCIVAC, 10, 1) +FIELD(HFGITR_EL2, DCZVA, 11, 1) +FIELD(HFGITR_EL2, ATS1E1R, 12, 1) +FIELD(HFGITR_EL2, ATS1E1W, 13, 1) +FIELD(HFGITR_EL2, ATS1E0R, 14, 1) +FIELD(HFGITR_EL2, ATS1E0W, 15, 1) +FIELD(HFGITR_EL2, ATS1E1RP, 16, 1) +FIELD(HFGITR_EL2, ATS1E1WP, 17, 1) +FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1) +FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1) +FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1) +FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1) +FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1) +FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1) +FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1) +FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1) +FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1) +FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1) +FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1) +FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1) +FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1) +FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1) +FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1) +FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1) +FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1) +FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1) +FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1) +FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1) +FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1) +FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1) +FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1) +FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1) +FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1) +FIELD(HFGITR_EL2, TLBIVAE1, 43, 1) +FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1) +FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1) +FIELD(HFGITR_EL2, TLBIVALE1, 46, 1) +FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1) +FIELD(HFGITR_EL2, CFPRCTX, 48, 1) +FIELD(HFGITR_EL2, DVPRCTX, 49, 1) +FIELD(HFGITR_EL2, CPPRCTX, 50, 1) +FIELD(HFGITR_EL2, ERET, 51, 1) +FIELD(HFGITR_EL2, SVC_EL0, 52, 1) +FIELD(HFGITR_EL2, SVC_EL1, 53, 1) +FIELD(HFGITR_EL2, DCCVAC, 54, 1) +FIELD(HFGITR_EL2, NBRBINJ, 55, 1) +FIELD(HFGITR_EL2, NBRBIALL, 56, 1) + +FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) +FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) +FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1) +FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1) +FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1) +FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1) +FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1) +FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1) +/* 8: RES0: OSLAR_EL1 is WO */ +FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1) +FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1) +FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1) +FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1) +FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1) +FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1) +FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1) +FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1) +FIELD(HDFGRTR_EL2, PMINTEN, 17, 1) +FIELD(HDFGRTR_EL2, PMOVS, 18, 1) +FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1) +/* 20: RES0: PMSWINC_EL0 is WO */ +/* 21: RES0: PMCR_EL0 is WO */ +FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1) +FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1) +FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1) +FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1) +FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1) +FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1) +FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1) +FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1) +FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1) +FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1) +FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1) +FIELD(HDFGRTR_EL2, TRC, 33, 1) +FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1) +FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1) +FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1) +FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1) +/* 38, 39: RES0 */ +FIELD(HDFGRTR_EL2, TRCID, 40, 1) +FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1) +/* 42: RES0: TRCOSLAR is WO */ +FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1) +FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1) +FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1) +FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1) +FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1) +FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1) +/* 49: RES0: TRFCR_EL1 is WO */ +FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1) +FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1) +FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1) +FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1) +FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1) +FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1) +FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1) +FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1) +FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1) +FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1) +FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1) +FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1) +FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1) +FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1) + +/* + * These match HDFGRTR_EL2, but bits for RO registers are RES0. + * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0. + */ +FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1) +FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1) +FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1) +FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1) +FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1) +FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1) +FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1) +FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1) +FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1) +FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1) +FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1) +FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1) +FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1) +FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1) +FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1) +FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1) +FIELD(HDFGWTR_EL2, PMINTEN, 17, 1) +FIELD(HDFGWTR_EL2, PMOVS, 18, 1) +FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1) +FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1) +FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1) +FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1) +FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1) +FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1) +FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1) +FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1) +FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1) +FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1) +FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1) +FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1) +FIELD(HDFGWTR_EL2, TRC, 33, 1) +FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1) +FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1) +FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1) +FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1) +FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1) +FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1) +FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1) +FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1) +FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1) +FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1) +FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1) +FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1) +FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1) +FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1) +FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1) +FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1) +FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1) +FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) +FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) +FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) + typedef struct ARMCPRegInfo ARMCPRegInfo; =20 /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8cf70693be4..063024508af 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -529,6 +529,16 @@ typedef struct CPUArchState { uint64_t disr_el1; uint64_t vdisr_el2; uint64_t vsesr_el2; + + /* + * Fine-Grained Trap registers. We store these as arrays so the + * access checking code doesn't have to manually select + * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. + * FEAT_FGT2 will add more elements to these arrays. + */ + uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ + uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ + uint64_t fgt_exec[1]; /* HFGITR */ } cp15; =20 struct { @@ -4164,6 +4174,11 @@ static inline bool isar_feature_aa64_tgran64_2(const= ARMISARegisters *id) return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran64(id)); } =20 +static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) !=3D 0; +} + static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 66966869218..20527995359 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1869,6 +1869,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_hcx, cpu)) { valid_mask |=3D SCR_HXEN; } + if (cpu_isar_feature(aa64_fgt, cpu)) { + valid_mask |=3D SCR_FGTEN; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -7546,6 +7549,39 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[3]) }, }; + +static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 2 && + arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGT= EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo fgt_reginfo[] =3D { + { .name =3D "HFGRTR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR])= }, + { .name =3D "HFGWTR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 5, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]= ) }, + { .name =3D "HDFGRTR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]= ) }, + { .name =3D "HDFGWTR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 1, .opc2 =3D 5, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR= ]) }, + { .name =3D "HFGITR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_RW, .accessfn =3D access_fgt, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR])= }, +}; #endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -8933,6 +8969,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_scxtnum, cpu)) { define_arm_cp_regs(cpu, scxtnum_reginfo); } + + if (cpu_isar_feature(aa64_fgt, cpu)) { + define_arm_cp_regs(cpu, fgt_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434651; cv=none; d=zohomail.com; s=zohoarc; b=Vmu2Qb2IFMzd4auh9nd036PhOg2Q0SDeaqA3KCqbAR4xfUJdw6WW5MQmBneHE0SpKdUfWN5pedObjGzh69IKR3W5zPHBd3ehcakDdfa7Fr8QP61ljsgDTmNGqblXTGQ2qjISw6cKftwWXR8bJMKZ11ur2XM+69oUjhDVedqo6rw= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VBGtDc2wO9Pk/ZYyPMtUfkQ3djSTk8nYlVlddOC0ytw=; b=jCUaoMW7ivOpngoOHqdg3DkwyWcFQyiXj1MO66B3H/BJUuvqfaUSrf+Hf/Jhuao2RK KQUxOD7g7EHmAaEKC+EHU6XughHMUsLVStBkDMWmM3yScT+We4V5dvZPZssIrDrdfSxD Rc/83m0wTE0puV4lR/Jom5mwTMWD/Cbm9Gf+dvD2YTJAUZIKT4ThaYm4j+xhw66uUsU2 BHDpV1imuUSeWBn6+He8GGpkKb3mazxedvT2r/EH+dLpMGFhhMBD+SP/iS+KGrj4wppN ulGYBJTSpSi9C7G/zdTsF/io6di5JDofvR0R6Kx9u+UwPgkf2A6MgCJNH10s/mNWxhuP QxEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VBGtDc2wO9Pk/ZYyPMtUfkQ3djSTk8nYlVlddOC0ytw=; b=B8G2FxpBPI3DbaSmPFrw39FGwDUk1ViDX7TDKRS4veZ+nm+0OcOjTsj+9mRELES00x 8T2urEt6XUr8CpYDaEbnqC/5qxyQe6oFkbTHs1Jmfd6wqpHOlyHa1NT38JMoQSSQ6Vhz gk7etZ+V+YkgI/cVHEw1qrD+tu3AGfLXOYFW2ujRcSnIjdeGcm7ntGv0oskRfgKzDG98 feEk87BPVsCebB1J0QxXZaVqsvM3T+bONvfzF0mVf9CUyqTUcZVduG/d6B1WGCUFuMU1 /btVRA+GER9BhYfPfR4yxgyeMld7KCC8AcKcG2jE3C6eXQhxSmKGjEsEM0K/lR7/7ptu /3GA== X-Gm-Message-State: AO0yUKVsUwhg6tTBB1QM/ZjyM8htuUtzGwB0aTCkI++xISGrder/MkLz LhTJju8xxNxbiI4fdSgPIdXV4MCQ89IvKyan X-Google-Smtp-Source: AK7set/IGXo7c83ybfgORHdtldLy0pnq9noZ/n9Th9YMmUgM/YjbYIW0wy30YMYV5jMMSEvxalJCXQ== X-Received: by 2002:a05:600c:c13:b0:3dc:496f:ad56 with SMTP id fm19-20020a05600c0c1300b003dc496fad56mr9707779wmb.14.1675434585138; Fri, 03 Feb 2023 06:29:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/33] target/arm: Implement FGT trapping infrastructure Date: Fri, 3 Feb 2023 14:29:13 +0000 Message-Id: <20230203142927.834793-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434652771100001 Content-Type: text/plain; charset="utf-8" Implement the machinery for fine-grained traps on normal sysregs. Any sysreg with a fine-grained trap will set the new field to indicate which FGT register bit it should trap on. FGT traps only happen when an AArch64 EL2 enables them for an AArch64 EL1. They therefore are only relevant for AArch32 cpregs when the cpreg can be accessed from EL0. The logic in access_check_cp_reg() will check this, so it is safe to add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo. The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname which can be used to specify the FGT bit, eg .fgt =3D FGT_AFSR0_EL1 (We assume that there is no bit name duplication across the FGT registers, for brevity's sake.) Subsequent commits will add the .fgt fields to the relevant register definitions and define the FGT_nnn values for them. Note that some of the FGT traps are for instructions that we don't handle via the cpregs mechanisms (mostly these are instruction traps). Those we will have to handle separately. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org --- target/arm/cpregs.h | 72 ++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 1 + target/arm/internals.h | 20 +++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 9 +++++ target/arm/op_helper.c | 30 ++++++++++++++++ target/arm/translate-a64.c | 3 +- target/arm/translate.c | 2 ++ 8 files changed, 138 insertions(+), 1 deletion(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index cb3dc567819..8cc12045af6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -515,6 +515,73 @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) =20 +/* Which fine-grained trap bit register to check, if any */ +FIELD(FGT, TYPE, 10, 3) +FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ +FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */ +FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */ + +/* + * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::f= gt + * fields. We assume for brevity's sake that there are no duplicated + * bit names across the various FGT registers. + */ +#define DO_BIT(REG, BITNAME) \ + FGT_##BITNAME =3D FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT + +/* Some bits have reversed sense, so 0 means trap and 1 means not */ +#define DO_REV_BIT(REG, BITNAME) \ + FGT_##BITNAME =3D FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT + +typedef enum FGTBit { + /* + * These bits tell us which register arrays to use: + * if FGT_R is set then reads are checked against fgt_read[]; + * if FGT_W is set then writes are checked against fgt_write[]; + * if FGT_EXEC is set then all accesses are checked against fgt_exec[]. + * + * For almost all bits in the R/W register pairs, the bit exists in + * both registers for a RW register, in HFGRTR/HDFGRTR for a RO regist= er + * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-ver= sa + * for a WO register. There are unfortunately a couple of exceptions + * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but + * the FGT system only allows trapping of writes, not reads. + * + * Note that we arrange these bits so that a 0 FGTBit means "no trap". + */ + FGT_R =3D 1 << R_FGT_TYPE_SHIFT, + FGT_W =3D 2 << R_FGT_TYPE_SHIFT, + FGT_EXEC =3D 4 << R_FGT_TYPE_SHIFT, + FGT_RW =3D FGT_R | FGT_W, + /* Bit to identify whether trap bit is reversed sense */ + FGT_REV =3D R_FGT_REV_MASK, + + /* + * If a bit exists in HFGRTR/HDFGRTR then either the register being + * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either + * want to trap for both reads and writes or else it's harmless to mark + * it as trap-on-writes. + * If a bit exists only in HFGWTR/HDFGWTR then either the register bei= ng + * trapped is WO, or else it is one of the two oddball special cases + * which are RW but have only a write trap. We mark these as only + * FGT_W so we get the right behaviour for those special cases. + * (If a bit was added in future that provided only a read trap for an + * RW register we'd need to do something special to get the FGT_R bit + * only. But this seems unlikely to happen.) + * + * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if + * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGW= TR. + */ + FGT_HFGRTR =3D FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT), + FGT_HFGWTR =3D FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT), + FGT_HDFGRTR =3D FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), + FGT_HDFGWTR =3D FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), + FGT_HFGITR =3D FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), +} FGTBit; + +#undef DO_BIT +#undef DO_REV_BIT + typedef struct ARMCPRegInfo ARMCPRegInfo; =20 /* @@ -569,6 +636,11 @@ struct ARMCPRegInfo { CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ CPSecureState secure; + /* + * Which fine-grained trap register bit to check, if any. This + * value encodes both the trap register and bit within it. + */ + FGTBit fgt; /* * The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 063024508af..5cc81bec9bf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3170,6 +3170,7 @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) +FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/internals.h b/target/arm/internals.h index d9555309df0..e1e018da463 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1377,4 +1377,24 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState = *env) ((1 << (1 - 1)) | (1 << (2 - 1)) | \ (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) =20 +/* + * Return true if it is possible to take a fine-grained-trap to EL2. + */ +static inline bool arm_fgt_active(CPUARMState *env, int el) +{ + /* + * The Arm ARM only requires the "{E2H,TGE} !=3D {1,1}" test for traps + * that can affect EL0, but it is harmless to do the test also for + * traps on registers that are only accessible at EL1 because if the t= est + * returns true then we can't be executing at EL1 anyway. + * FGT traps only happen when EL2 is enabled and EL1 is AArch64; + * traps from AArch32 only happen for the EL0 is AArch32 case. + */ + return cpu_isar_feature(aa64_fgt, env_archcpu(env)) && + el < 2 && arm_is_el2_enabled(env) && + arm_el_is_aa64(env, 1) && + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE) && + (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FG= TEN)); +} + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index f17f095cbe2..599902016dc 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -130,6 +130,8 @@ typedef struct DisasContext { bool is_nonstreaming; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; + /* True if fine-grained traps are active */ + bool fgt_active; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 20527995359..2389e41bd07 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11689,6 +11689,7 @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMSt= ate *env, int fp_el, if (arm_singlestep_active(env)) { DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); } + return flags; } =20 @@ -11761,6 +11762,10 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } =20 + if (arm_fgt_active(env, el)) { + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + } + if (env->uncached_cpsr & CPSR_IL) { DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } @@ -11895,6 +11900,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMStat= e *env, int el, int fp_el, DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } =20 + if (arm_fgt_active(env, el)) { + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + } + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { /* * Set MTE_ACTIVE if any access may be Checked, and leave clear diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index dec03310ad5..3baf8004f64 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -680,6 +680,36 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *e= nv, uint32_t key, } } =20 + /* + * Fine-grained traps also are lower priority than undef-to-EL1, + * higher priority than trap-to-EL3, and we don't care about priority + * order with other EL2 traps because the syndrome value is the same. + */ + if (arm_fgt_active(env, arm_current_el(env))) { + uint64_t trapword =3D 0; + unsigned int idx =3D FIELD_EX32(ri->fgt, FGT, IDX); + unsigned int bitpos =3D FIELD_EX32(ri->fgt, FGT, BITPOS); + bool rev =3D FIELD_EX32(ri->fgt, FGT, REV); + bool trapbit; + + if (ri->fgt & FGT_EXEC) { + assert(idx < ARRAY_SIZE(env->cp15.fgt_exec)); + trapword =3D env->cp15.fgt_exec[idx]; + } else if (isread && (ri->fgt & FGT_R)) { + assert(idx < ARRAY_SIZE(env->cp15.fgt_read)); + trapword =3D env->cp15.fgt_read[idx]; + } else if (!isread && (ri->fgt & FGT_W)) { + assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); + trapword =3D env->cp15.fgt_write[idx]; + } + + trapbit =3D extract64(trapword, bitpos, 1); + if (trapbit !=3D rev) { + res =3D CP_ACCESS_TRAP_EL2; + goto fail; + } + } + if (likely(res =3D=3D CP_ACCESS_OK)) { return ri; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 52b1b8a1f0a..a47dab4f1dd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1962,7 +1962,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, return; } =20 - if (ri->accessfn) { + if (ri->accessfn || (ri->fgt && s->fgt_active)) { /* Emit code to perform further access permissions checks at * runtime; this may result in an exception. */ @@ -14741,6 +14741,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); + dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl =3D (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; diff --git a/target/arm/translate.c b/target/arm/translate.c index f4bfe55158e..3f51dc6a6bf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4815,6 +4815,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, } =20 if ((s->hstr_active && s->current_el =3D=3D 0) || ri->accessfn || + (ri->fgt && s->fgt_active) || (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) { /* * Emit code to perform further access permissions checks at @@ -9415,6 +9416,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); + dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); =20 if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled =3D 1; --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434870; cv=none; d=zohomail.com; s=zohoarc; b=GZd4BzrkBYIC/IsJFAZnKsewRAXy5tYQsYAN9a5NMbcYAkNw6317FOGy7GywNvL2HmRf+bEGzns13mPP/X9iq4UzXHeO8tPtAXIRVVBs7LXwoq9Ay7eULNqFz7RcLJGp2VxxLjLLvY0KcW9ar3BES5pDK9sB3hEf2nk8lUh9QX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434870; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yQxmFDzxxFrhEVqQzCA0FWZTs2ofEI2+0Euyqm2fY1E=; b=vn3ejJCBVKvfaKNXNgXAMDtPSngk3iqzBj1CwoqAauUWhW0GtxbxP/PuZlskIK1Dec 1WsmgsjFv68IFr1dSUDpMEmrC2QM60frjnLCKBnODw7clEyych1B3dKwbDz+GNDIo0rB T12tEg/HPGIvLv20CnSgbIoGpWSB6sGfazwGw9yzSrHgJA2zxyfFh4RtIhIUcut/EWJq 86yQ4NzvOPWlAENtGU1BkQBI7ltLlDNQTtjJecncdn9caLSAbWIaPIx2+JRPppwVXhTq XMA29uaOtIYP/yfPa9N1/UAP+jd6YFKXSdiWpq/2PrxaogTF80heGDxjqdn8i0q1ok2D Mp6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yQxmFDzxxFrhEVqQzCA0FWZTs2ofEI2+0Euyqm2fY1E=; b=LIEPqlE9Ivb7En7tTnSgiIvUAebxVz86sChjJk8h+xbHDU+aqNGhky4URxQiu8m3qu GE1lE+y3Wx9r07VzX6E/HjLHCIegMhtG7irqCqVvcVYXC3FYGU2KuCR6Q9f2kqpp6/lW VmrsS5k5+f4X9sg2MSenU3tDuOTVRZxetXigODVpsePa7q9HOQGKviDCEDIj/5MAVjYx IYJ17dlE5PynB58r0LCNScWKna9GecF8MxFsgs4W9j4CtiIKzUl9Ti+7LfP6KlZSBVWX hbNACdLoh4WP0rS/0fxaYcyhDr5UO24J67zrPr8trA3TxkzHNKRzFeQkHlUI5D+6t5XU tnig== X-Gm-Message-State: AO0yUKVbKE12ii0PlyJ50dh1s3hytYs2eYqOCri1/wwHiIwgM066drjl fyqS8p8ld0ELYjPTP3/2455cIYd9x7nmSuLe X-Google-Smtp-Source: AK7set+tdBRj2q+iONCgcqrAFkvTexPqGqoH+dVqNefECuXzuzh4DB8PyOfnJQqAteyiGCG7aW5f/w== X-Received: by 2002:a05:600c:3c9b:b0:3dc:46e8:982 with SMTP id bg27-20020a05600c3c9b00b003dc46e80982mr9496370wmb.19.1675434586066; Fri, 03 Feb 2023 06:29:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11 Date: Fri, 3 Feb 2023 14:29:14 +0000 Message-Id: <20230203142927.834793-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434872273100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 0..11. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org --- target/arm/cpregs.h | 14 ++++++++++++++ target/arm/helper.c | 17 +++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 8cc12045af6..82f2cefff0a 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -577,6 +577,20 @@ typedef enum FGTBit { FGT_HDFGRTR =3D FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), FGT_HDFGWTR =3D FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), FGT_HFGITR =3D FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), + + /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ + DO_BIT(HFGRTR, AFSR0_EL1), + DO_BIT(HFGRTR, AFSR1_EL1), + DO_BIT(HFGRTR, AIDR_EL1), + DO_BIT(HFGRTR, AMAIR_EL1), + DO_BIT(HFGRTR, APDAKEY), + DO_BIT(HFGRTR, APDBKEY), + DO_BIT(HFGRTR, APGAKEY), + DO_BIT(HFGRTR, APIAKEY), + DO_BIT(HFGRTR, APIBKEY), + DO_BIT(HFGRTR, CCSIDR_EL1), + DO_BIT(HFGRTR, CLIDR_EL1), + DO_BIT(HFGRTR, CONTEXTIDR_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 2389e41bd07..30e54455ac7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -633,6 +633,7 @@ static const ARMCPRegInfo cp_reginfo[] =3D { { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_CONTEXTIDR_EL1, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, @@ -2163,6 +2164,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, .access =3D PL1_R, .accessfn =3D access_tid4, + .fgt =3D FGT_CCSIDR_EL1, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW }, { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, @@ -2179,6 +2181,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid1, + .fgt =3D FGT_AIDR_EL1, .resetvalue =3D 0 }, /* * Auxiliary fault status registers: these also are IMPDEF, and we @@ -2187,10 +2190,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AFSR0_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AFSR1_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * MAIR can just read-as-written because we don't implement caches @@ -4392,6 +4397,7 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AMAIR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, @@ -7041,42 +7047,52 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { { .name =3D "APDAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apda.lo) }, { .name =3D "APDAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apda.hi) }, { .name =3D "APDBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apdb.lo) }, { .name =3D "APDBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apdb.hi) }, { .name =3D "APGAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APGAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apga.lo) }, { .name =3D "APGAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APGAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apga.hi) }, { .name =3D "APIAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apia.lo) }, { .name =3D "APIAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apia.hi) }, { .name =3D "APIBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apib.lo) }, { .name =3D "APIBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, }; =20 @@ -7940,6 +7956,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_tid4, + .fgt =3D FGT_CLIDR_EL1, .resetvalue =3D cpu->clidr }; define_one_arm_cp_reg(cpu, &clidr); --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434797; cv=none; d=zohomail.com; s=zohoarc; b=dSLi9WPmmQyfYzgH+QSia4pi5RfJ66yFw03znFSaiuj1FUwu4t6kj2nWKuJDXu3xmiCHTvkE0LniIDHNr1UOXbj3L5fmGarZXAWOwNmtZzF/NVVd2h7F8Mfkf8Kdr0M9eZYkYtT/drg3Bg8IvgI5yRiY9cFv6SsdCXFKmp/qDZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434797; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=p6ebWUhLxy1Vko9RKec4Spu2hlMYvJ/5ZZfi2NMMhLY=; b=m3o7g7LhK5q8cqpL4j091RrVmUQyFzUloPWMHfgS+aNbhLD14RDz9TMgnliR1aokHH 9qysRQNs0JHAsuijtYaouh4EUL8WTTmbd+rR5JLoO912pPfHcjx3CeCReigSecuvOCqW NNrb8JQvVbP5bj5KPq+YLd69xjtH14gv4kqUvI1qg/Z/hNF8xmYbxb4CP1dDeqCOyiyt KAPjS5jL8cC2GV3n3Jt6xV4ISU4vygfL/+srEAR7hQJkMz5faAUtB3fdFbqKJ0ssRccf Ho1WQlj64n9Qk39LgN7fSmeehOvsAxAfYVfuX7qFOSSoDHd8KlMDK7PUCv1cYB6IAVzY eOdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p6ebWUhLxy1Vko9RKec4Spu2hlMYvJ/5ZZfi2NMMhLY=; b=Me2y9esak2Rjo55hWDAachaL/aCNBGKseebG1yipo90fBBEPZJsWZRWYXUfRrvehhw tKjgUh5gqzBJYUSjAgfk+wa0DhyjJkn7VYk2iqAdWye9bFu4pfaFSAVLUqdeoirQW5ag XtOIPUcu7Z8PsVpE9yacDNgvNEBvb87DVlEcVpjV5SHsPOQ8eupdbJoliOVM/75jWey3 b5N4TGqCedJEmH9VVLHygtO4xail3QNSrlSkvgx0+r/6rvp5bq0dctE49DedCJVzMLge HmiuDh9Hapig+7GBrYfCKGoIB4Sh5ng0XrOThxKuv36wIKFM4M1uJfw2w8t/XpLAJlgV zS8A== X-Gm-Message-State: AO0yUKUayy8Kv3lyCY40NjasDNJt6gleZ8z7yh2V2g47nfRYhzVk7cPb KgDLcxNcd43A+4zJHgrRKYcZhhrujBNgAYxL X-Google-Smtp-Source: AK7set8KuWmlOkW4EOxa54HPMyi426+Rm56hT7BXKaOl4StLiVo8iQ3Yps6CbTWqhOnSxKYAEz0vqA== X-Received: by 2002:a05:600c:1d83:b0:3cf:68d3:3047 with SMTP id p3-20020a05600c1d8300b003cf68d33047mr9499897wms.41.1675434586946; Fri, 03 Feb 2023 06:29:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23 Date: Fri, 3 Feb 2023 14:29:15 +0000 Message-Id: <20230203142927.834793-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434799600100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 12..23. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/helper.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 82f2cefff0a..67d87ae8bf5 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -591,6 +591,18 @@ typedef enum FGTBit { DO_BIT(HFGRTR, CCSIDR_EL1), DO_BIT(HFGRTR, CLIDR_EL1), DO_BIT(HFGRTR, CONTEXTIDR_EL1), + DO_BIT(HFGRTR, CPACR_EL1), + DO_BIT(HFGRTR, CSSELR_EL1), + DO_BIT(HFGRTR, CTR_EL0), + DO_BIT(HFGRTR, DCZID_EL0), + DO_BIT(HFGRTR, ESR_EL1), + DO_BIT(HFGRTR, FAR_EL1), + DO_BIT(HFGRTR, ISR_EL1), + DO_BIT(HFGRTR, LORC_EL1), + DO_BIT(HFGRTR, LOREA_EL1), + DO_BIT(HFGRTR, LORID_EL1), + DO_BIT(HFGRTR, LORN_EL1), + DO_BIT(HFGRTR, LORSA_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 30e54455ac7..c059935d0e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -869,6 +869,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, + .fgt =3D FGT_CPACR_EL1, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, }; @@ -2170,6 +2171,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tid4, + .fgt =3D FGT_CSSELR_EL1, .writefn =3D csselr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, @@ -2233,6 +2235,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, { .name =3D "ISR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, + .fgt =3D FGT_ISR_EL1, .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, /* 32 bit ITLB invalidates */ { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, @@ -4135,6 +4138,7 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_FAR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, }; @@ -4143,6 +4147,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_ESR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, @@ -5215,6 +5220,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, + .fgt =3D FGT_DCZID_EL0, .readfn =3D aa64_dczid_read }, { .name =3D "DC_ZVA", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 1, @@ -7005,22 +7011,27 @@ static const ARMCPRegInfo lor_reginfo[] =3D { { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORSA_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LOREA_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORN_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORC_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, .access =3D PL1_R, .accessfn =3D access_lor_ns, + .fgt =3D FGT_LORID_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 @@ -8619,6 +8630,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "CTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 0, .crm =3D = 0, .access =3D PL0_R, .accessfn =3D ctr_el0_access, + .fgt =3D FGT_CTR_EL0, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ { .name =3D "TCMTR", --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675435033; cv=none; d=zohomail.com; s=zohoarc; b=Y9+/Er5tI8MuVMX3Gu8LD2yyDOlbncLdWLq7c8XNAqBW/gjpqpyoVjsA+XKOPZoetPKMcl2Gp3IGprXxJnhsJSRFIHNIV0OCPsZmddFCO2NfZ24NobKG7u9NArMtWzGYI3vrTK0aJWX4Yunpd0v2ACC2AHsG65lUY/S9lbGGgjA= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0taStepCYELwMXmaZO+UXEgrJrJoHD0cnE+BYO0UISY=; b=D+ME8HfPbqx0RC/0muSsblIOPi+U8igcLPeD9AIrrZ+MmRd3GZ/hdEoulajlunHPx1 RxT7+E7Pf502Tghcj/0nYAloxbdSc/sNDJZiBjhZY3sacVmmmlMsqCehPZqm44B5Jvqp 5/8pLAl3fjHkIftiSR1dnahRTBpW2yBfVVjygmp4HEVRIgXLseJjhp1XvZaXpzU9QaI1 hZogoBGVERbacHQdF1flpMHh2aYKLFdYhTTYzKOhQs97meJ87sQuRyEGOadgITSZX9dc 9EPqteNZeudTsYgZ67qNSK/n0ysLYMMVvxc5aNAHr3rOJ4XbcC+cH8noK69+JceLQp1u qBHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0taStepCYELwMXmaZO+UXEgrJrJoHD0cnE+BYO0UISY=; b=RJmvDkhVHtUezfaQkh8bjWw1fN5cNfuqIvwgGjCacuzbHppvGPiFpPor2AKX4OytfZ HP9Op02uRHcmIidltDE+ndrZhkw4n9ft1haXfOJUEAzp2VtPr1IDuCb9YRyAxzT/s3WD ATYGrCo1M/NJph+gUm5+iyH6a9ufoq/r+B8uPIBXiuG1PRS7bb5g9cJntjREdtgjI2mH r4nxCv4t0BPSzxo1C7trSE+9LX+qKPAmwSqLi7Pyyu+5N3uaVFMs25YcH+i58/s2Vkhk JwNIvo64NAZpYFOp+0wXa5fGvNA7+czUc6owsWK52CYxkifTtsQKQbeAe+yIrumTY7zt TDFw== X-Gm-Message-State: AO0yUKUNZf/jutcU4VjXw6Nn0QtACv4LrYQyWtVkDRsATTXTJ6zaxd53 x7sa5zoL0ZfNdMWJYjF7CRA1Aew7euh0KS0i X-Google-Smtp-Source: AK7set+osC0w9lCIUlRm7moc946PYM2KM6eh0GOh5P6/t5Q5lC/AMw+WeSuKo4gH38n0KDLiN/0O0Q== X-Received: by 2002:a05:600c:3513:b0:3df:b5ae:5289 with SMTP id h19-20020a05600c351300b003dfb5ae5289mr6773942wmq.8.1675434587760; Fri, 03 Feb 2023 06:29:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35 Date: Fri, 3 Feb 2023 14:29:16 +0000 Message-Id: <20230203142927.834793-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675435034357100005 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 24..35. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/helper.c | 14 ++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 67d87ae8bf5..1b219242d5d 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -603,6 +603,18 @@ typedef enum FGTBit { DO_BIT(HFGRTR, LORID_EL1), DO_BIT(HFGRTR, LORN_EL1), DO_BIT(HFGRTR, LORSA_EL1), + DO_BIT(HFGRTR, MAIR_EL1), + DO_BIT(HFGRTR, MIDR_EL1), + DO_BIT(HFGRTR, MPIDR_EL1), + DO_BIT(HFGRTR, PAR_EL1), + DO_BIT(HFGRTR, REVIDR_EL1), + DO_BIT(HFGRTR, SCTLR_EL1), + DO_BIT(HFGRTR, SCXTNUM_EL1), + DO_BIT(HFGRTR, SCXTNUM_EL0), + DO_BIT(HFGRTR, TCR_EL1), + DO_BIT(HFGRTR, TPIDR_EL1), + DO_BIT(HFGRTR, TPIDRRO_EL0), + DO_BIT(HFGRTR, TPIDR_EL0), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index c059935d0e6..9f6d9e2a3c9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2206,6 +2206,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_MAIR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, @@ -2349,25 +2350,30 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { { .name =3D "TPIDR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 2, .crn =3D 13, .crm =3D 0, .access =3D PL0_RW, + .fgt =3D FGT_TPIDR_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalu= e =3D 0 }, { .name =3D "TPIDRURW", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 2, .access =3D PL0_RW, + .fgt =3D FGT_TPIDR_EL0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrurw_s), offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = }, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, .access =3D PL0_R | PL1_W, + .fgt =3D FGT_TPIDRRO_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el[0]), .resetvalue =3D 0}, { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, .access =3D PL0_R | PL1_W, + .fgt =3D FGT_TPIDRRO_EL0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D 13, .crm =3D 0, .access =3D PL1_RW, + .fgt =3D FGT_TPIDR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalu= e =3D 0 }, { .name =3D "TPIDRPRW", .opc1 =3D 0, .cp =3D 15, .crn =3D 13, .crm =3D= 0, .opc2 =3D 4, .access =3D PL1_RW, @@ -4164,6 +4170,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_TCR_EL1, .writefn =3D vmsa_tcr_el12_write, .raw_writefn =3D raw_write, .resetvalue =3D 0, @@ -5399,6 +5406,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 7, .crm =3D 4, .opc2 =3D 0, .access =3D PL1_RW, .resetvalue =3D 0, + .fgt =3D FGT_PAR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]), .writefn =3D par_write }, #endif @@ -7562,10 +7570,12 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { { .name =3D "SCXTNUM_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, .access =3D PL0_RW, .accessfn =3D access_scxtnum, + .fgt =3D FGT_SCXTNUM_EL0, .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[0]) }, { .name =3D "SCXTNUM_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, .access =3D PL1_RW, .accessfn =3D access_scxtnum, + .fgt =3D FGT_SCXTNUM_EL1, .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, @@ -8604,6 +8614,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, + .fgt =3D FGT_MIDR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 7 : AArch32 aliases o= f MIDR */ @@ -8614,6 +8625,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, .access =3D PL1_R, .accessfn =3D access_aa64_tid1, + .fgt =3D FGT_REVIDR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; ARMCPRegInfo id_v8_midr_alias_cp_reginfo =3D { @@ -8785,6 +8797,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo mpidr_cp_reginfo[] =3D { { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, + .fgt =3D FGT_MPIDR_EL1, .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, }; #ifdef CONFIG_USER_ONLY @@ -8884,6 +8897,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_SCTLR_EL1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, --=20 2.34.1 From nobody Thu Apr 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0VoPlZhHUdfCku+qw/NzX2OrIbw7jq7vrZk3olaLM5Q=; b=ymnWa+5xocLrBnXKaVQcoVpW4/fShfrO4U9YRxRNaCq97lXhjc0wBuinAP7qhwxHiN eR/ziqrG7PvDr6ayBijVgSAxdhury9hoHg3a1pUhwP7jLjV3nn3wi1jzUBUlpwJoAeay 4Z8Hwm9N/YljlgtMX3yxSc5XTSyezRdV0dAAxRVzoc8HPEkLMyP6uhMBxBPtxd3eL4ee sxzR5biJtnY/dmrRwJDxJgCUTuKXk8HV+5//jRVD7QQZ2kwQ7JsR7irsbEAteCYFtCXK yda5liy0RkW3L+8qV5jDPehCCyamAcqbzRzjTqCt4vLwWnYnOs8cOWc7q81QnjRhtAUG rhVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0VoPlZhHUdfCku+qw/NzX2OrIbw7jq7vrZk3olaLM5Q=; b=R8+7SUOD8q7O1j1HBPvMSpFL0TuxJYD3E9tIfCr8BmRajAVST8JNrjP2P6CmSCIa41 KTpaSMDJDD1y3RzWKlOrLVsvAW4+oCh+3MRg18caJmqy8Bp1BQxl03hHgVD/YH2nnYlr Fi9Aupc/oHuWpC1hqEGmzJcDY/0wqzAH559kPOK/U4I5XxJnyz03rNmVSqKdu8eOT+pv IU7KInu/ROM1apdgISibj/Y5tH/mhHDpN224uTXGZ2FkxNgGuXdTL9XEUsWJh6vgWO+w Zn9p7Gh5p1bVrcTxxwcR8TCeGz1Mzj8USFjRCyfIxrpjkTn2vPeggj2dZB+JVqm5lwmN 2PCg== X-Gm-Message-State: AO0yUKU/XFuwTT6S4pRmjNhsygebhGj5TA28gBPHndgoeEFsaTkC4Br+ ZQN0m6HuRQw/2p+uU6jOmxN7CHqXm1vSHei1 X-Google-Smtp-Source: AK7set++BcBRaM/iGFPp6LlrkXj9Qz1+TiqqXh86w/4gK85ZD3f8Q5hiKrqpTjlz5UF6h3lUxgfkqg== X-Received: by 2002:a05:600c:474f:b0:3df:e57d:f4d0 with SMTP id w15-20020a05600c474f00b003dfe57df4d0mr2941024wmo.26.1675434588601; Fri, 03 Feb 2023 06:29:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63 Date: Fri, 3 Feb 2023 14:29:17 +0000 Message-Id: <20230203142927.834793-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434688788100007 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 36..63. Of these, some correspond to RAS registers which we implement as always-UNDEF: these don't need any extra handling for FGT because the UNDEF-to-EL1 always takes priority over any theoretical FGT-trap-to-EL2. Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part of the FEAT_LS64_ACCDATA feature which we don't yet implement. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-14-peter.maydell@linaro.org Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org --- target/arm/cpregs.h | 7 +++++++ hw/intc/arm_gicv3_cpuif.c | 2 ++ target/arm/helper.c | 10 ++++++++++ 3 files changed, 19 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1b219242d5d..fef8ad08acc 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -615,6 +615,13 @@ typedef enum FGTBit { DO_BIT(HFGRTR, TPIDR_EL1), DO_BIT(HFGRTR, TPIDRRO_EL0), DO_BIT(HFGRTR, TPIDR_EL0), + DO_BIT(HFGRTR, TTBR0_EL1), + DO_BIT(HFGRTR, TTBR1_EL1), + DO_BIT(HFGRTR, VBAR_EL1), + DO_BIT(HFGRTR, ICC_IGRPENN_EL1), + DO_BIT(HFGRTR, ERRIDR_EL1), + DO_REV_BIT(HFGRTR, NSMPRI_EL1), + DO_REV_BIT(HFGRTR, NTPIDR2_EL0), } FGTBit; =20 #undef DO_BIT diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 9a7fc190994..d07b13eb270 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2378,6 +2378,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 6, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .access =3D PL1_RW, .accessfn =3D gicv3_fiq_access, + .fgt =3D FGT_ICC_IGRPENN_EL1, .readfn =3D icc_igrpen_read, .writefn =3D icc_igrpen_write, }, @@ -2386,6 +2387,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 7, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .access =3D PL1_RW, .accessfn =3D gicv3_irq_access, + .fgt =3D FGT_ICC_IGRPENN_EL1, .readfn =3D icc_igrpen_read, .writefn =3D icc_igrpen_write, }, diff --git a/target/arm/helper.c b/target/arm/helper.c index 9f6d9e2a3c9..a48b022def6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4158,12 +4158,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_TTBR0_EL1, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_TTBR1_EL1, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, @@ -6488,6 +6490,10 @@ static void disr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t val) * ERRSELR_EL1 * may generate UNDEFINED, which is the effect we get by not * listing them at all. + * + * These registers have fine-grained trap bits, but UNDEF-to-EL1 + * is higher priority than FGT-to-EL2 so we do not need to list them + * in order to check for an FGT. */ static const ARMCPRegInfo minimal_ras_reginfo[] =3D { { .name =3D "DISR_EL1", .state =3D ARM_CP_STATE_BOTH, @@ -6497,6 +6503,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] =3D { { .name =3D "ERRIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_R, .accessfn =3D access_terr, + .fgt =3D FGT_ERRIDR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, @@ -6819,6 +6826,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "TPIDR2_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 5, .access =3D PL0_RW, .accessfn =3D access_tpidr2, + .fgt =3D FGT_NTPIDR2_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr2_el0) }, { .name =3D "SVCR", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 2, @@ -6856,6 +6864,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "SMPRI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 4, .access =3D PL1_RW, .accessfn =3D access_esm, + .fgt =3D FGT_NSMPRI_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "SMPRIMAP_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 5, @@ -8884,6 +8893,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, .access =3D PL1_RW, .writefn =3D vbar_write, + .fgt =3D FGT_VBAR_EL1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BhearbGMg07ixmxcVta7913JfgZva0wWKZfBDKaes20=; b=p7NvEgSosXD4LYrwXJ4g74fQ+yZQPaezsBGjT2jGQNfO2d35npqIJ5Uu8KKwRSpXIC fsSedcPm4NT0bdd+h9OaXUoHGRN3gS4mLNvwawhpHHy2yVMEL88NKbEZs5EZi5dF/l6L /403ZexQ4/gZ9FssTW+djsXO2PdWsrAcj/92eoCCNqvPXWihyRG+m4CMDY3zQSiEulaE 42EDysb4MGQBjsqIZE7/zWWx4Gklb52iZyYOwtIjQRi6uIxfiqs73fEfyzF4lNKBR/na DN+z7ue5zmhNGqjH1vGhQHQmCQDFSXmI7lnYau1hFVpTB5lBCmvMO9mql5wxQtvkdVaT zAJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BhearbGMg07ixmxcVta7913JfgZva0wWKZfBDKaes20=; b=KFldb80Tu3kEsrjY8kS/07sBlWu6IsryeSuz3X4zG17vk6G1SpKJAv7gA20LvjbPkm wuOsNeNfyR0oSxYLoq9pkWQaG7ZGaU1xxzJN+StUX3WccTjfof/5JobgZZFCQoJbSk4M IXUXVNc2qGunCMhsiGNSDN8P18QePDckyDoxsc5WUKUxX3O42L69klwKVKF6nOCk7D9o rRzf1E9ShzATRO/CRGOpxAjyaXsqaYbRv8NNmUTse0AHzC2XzufJVoENVzULYWA6EnZw sOa7v5BybaayLN/JvtCqmv3rpm4/79UFqIlh7U0iJnXmkFlwawCVlJqWmvAzq266NTyt E/fg== X-Gm-Message-State: AO0yUKU+YknsSD77SFviGn/OY02603hao1172937ifj2LVyqNIaCDkFj TF2wAMGa8XMYM/AksIssRGSMhQ/Z24DszORE X-Google-Smtp-Source: AK7set+nBXMGKj/0n3AcB56hzkZm1rib3k9E4TUBvYBJYSFujlFj1MK77V9fhlWTS190TfyOPk1lPw== X-Received: by 2002:a05:600c:1c81:b0:3dc:5987:fe9 with SMTP id k1-20020a05600c1c8100b003dc59870fe9mr10183749wms.2.1675434589544; Fri, 03 Feb 2023 06:29:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11 Date: Fri, 3 Feb 2023 14:29:18 +0000 Message-Id: <20230203142927.834793-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434739279100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitons for the registers trapped by HDFGRTR/HDFGWTR bits 0..11. These cover various debug related registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-15-peter.maydell@linaro.org Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/debug_helper.c | 11 +++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index fef8ad08acc..7c4d07ed9c6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -622,6 +622,18 @@ typedef enum FGTBit { DO_BIT(HFGRTR, ERRIDR_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), + + /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ + DO_BIT(HDFGRTR, DBGBCRN_EL1), + DO_BIT(HDFGRTR, DBGBVRN_EL1), + DO_BIT(HDFGRTR, DBGWCRN_EL1), + DO_BIT(HDFGRTR, DBGWVRN_EL1), + DO_BIT(HDFGRTR, MDSCR_EL1), + DO_BIT(HDFGRTR, DBGCLAIM), + DO_BIT(HDFGWTR, OSLAR_EL1), + DO_BIT(HDFGRTR, OSLSR_EL1), + DO_BIT(HDFGRTR, OSECCR_EL1), + DO_BIT(HDFGRTR, OSDLR_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cced3f168d0..b106746b0e1 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -672,6 +672,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_MDSCR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), .resetvalue =3D 0 }, /* @@ -702,6 +703,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "OSECCR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_OSECCR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as @@ -717,16 +719,19 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSLAR_EL1, .writefn =3D oslar_write }, { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, .access =3D PL1_R, .resetvalue =3D 10, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSLSR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, /* Dummy OSDLR_EL1: 32-bit Linux will read this */ { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, .access =3D PL1_RW, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSDLR_EL1, .writefn =3D osdlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.osdlr_el1) }, /* @@ -763,10 +768,12 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 = =3D 6, .type =3D ARM_CP_ALIAS, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGCLAIM, .writefn =3D dbgclaimset_write, .readfn =3D dbgclaimset_read }, { .name =3D "DBGCLAIMCLR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 = =3D 6, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGCLAIM, .writefn =3D dbgclaimclr_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgclaim) }, }; @@ -1127,12 +1134,14 @@ void define_debug_regs(ARMCPU *cpu) { .name =3D dbgbvr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGBVRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write }, { .name =3D dbgbcr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGBCRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write }, @@ -1149,12 +1158,14 @@ void define_debug_regs(ARMCPU *cpu) { .name =3D dbgwvr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGWVRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write }, { .name =3D dbgwcr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGWCRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write }, --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wbeG3RqWepmqfpgsVO1uBd1T8UYDoP87EdSf0MfbsLw=; b=JiSPmtpu0/QbG5yWmnQfYg7R8CCCGCSB8HEV/ZT+51UvNinajG9Sv25mZWyCeiG2wN r59lpdTGpqLuqDW1BvUbZXiOfF1kpryUZcdYc2xzXuLq0XG/0UwhbPyDz4dK0NUqnTnu IKbkNz81fjks5sA8Heuc2iOQkloHHE7F/45qBZhBq1Fv+QwyoUsqM/DM0IlHxsY67qpk 2AKuu/iLzqRfJDxJYdLqBWjMmHBYkZ7a0GKEaCRMblxaMjDwwCyv9AFwHa0IqLRocEmV 8nmlZjV3OjN1J9sVvc91RCWChsioxjFJZisHcfvPkf+wnImDlC7JUvWp8tyzZlkZmwhP lyzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wbeG3RqWepmqfpgsVO1uBd1T8UYDoP87EdSf0MfbsLw=; b=kD2BJiIEPWYq6yAM1ITFZzN8BQ45bd/32v27CGsDMszUPwizoEFlihhmeYw4O87iN8 x56fMkfaLlRBTuFRbB8pE2+Uz+sfd0x/RTMLmctlHgDK2vaQPHRokfjQ9fJslnOpLk14 KqIVRWfP8O2fSPL+czn+2DSPc0f77OvLj2LfINEhmnId5FjMzOKfg2tHmvjuQgusIGhI RRLoXFP4u6nqcDqVA7YxAl02urqdvwFdqNxaIsGlXM2/fkf0srE5HKGuMiXE3XBR1Z7E xdk4H0dDjczK0eEoCtOIgXpGgnrc1Qbjz1wmBeES1q730MAO5DNOSN5W3x3q40puiud+ h2Lw== X-Gm-Message-State: AO0yUKV7XnHVnBbwHmIBj2dPemIV+sqtfhAG9x8717tfjTSB/PovcfiX ANYqYgl169m57TBTpCI36WRY0WHsdEIrj0QG X-Google-Smtp-Source: AK7set+E6CB1wWGMYvVjoLXu0IlvF1SRcMSHlXIr8CpeuQMV4UBHnjtriOeGfpwcLGqih0O3Jj/+kA== X-Received: by 2002:a05:6000:1007:b0:2c1:15b8:9eb7 with SMTP id a7-20020a056000100700b002c115b89eb7mr8348968wrx.59.1675434590353; Fri, 03 Feb 2023 06:29:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63 Date: Fri, 3 Feb 2023 14:29:19 +0000 Message-Id: <20230203142927.834793-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434654654100005 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HDFGRTR/HDFGWTR bits 12..x. Bits 12..22 and bit 58 are for PMU registers. The remaining bits in HDFGRTR/HDFGWTR are for traps on registers that are part of features we don't implement: Bits 23..32 and 63 : FEAT_SPE Bits 33..48 : FEAT_ETE Bits 50..56 : FEAT_TRBE Bits 59..61 : FEAT_BRBE Bit 62 : FEAT_SPEv1p2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-16-peter.maydell@linaro.org Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7c4d07ed9c6..c37e013b8f3 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -634,6 +634,18 @@ typedef enum FGTBit { DO_BIT(HDFGRTR, OSLSR_EL1), DO_BIT(HDFGRTR, OSECCR_EL1), DO_BIT(HDFGRTR, OSDLR_EL1), + DO_BIT(HDFGRTR, PMEVCNTRN_EL0), + DO_BIT(HDFGRTR, PMEVTYPERN_EL0), + DO_BIT(HDFGRTR, PMCCFILTR_EL0), + DO_BIT(HDFGRTR, PMCCNTR_EL0), + DO_BIT(HDFGRTR, PMCNTEN), + DO_BIT(HDFGRTR, PMINTEN), + DO_BIT(HDFGRTR, PMOVS), + DO_BIT(HDFGRTR, PMSELR_EL0), + DO_BIT(HDFGWTR, PMSWINC_EL0), + DO_BIT(HDFGWTR, PMCR_EL0), + DO_BIT(HDFGRTR, PMMIR_EL1), + DO_BIT(HDFGRTR, PMCEIDN_EL0), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index a48b022def6..2e494b8f924 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2035,21 +2035,25 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenset_write, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .raw_writefn =3D raw_write }, { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, .type =3D = ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL0_RW, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .writefn =3D pmcntenclr_write, .type =3D ARM_CP_ALIAS | ARM_CP_IO }, { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, @@ -2057,41 +2061,49 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .fgt =3D FGT_PMSWINC_EL0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .writefn =3D pmswinc_write }, { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .fgt =3D FGT_PMSWINC_EL0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .writefn =3D pmswinc_write }, { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fgt =3D FGT_PMSELR_EL0, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), .accessfn =3D pmreg_access_selr, .writefn =3D pmselr_write, .raw_writefn =3D raw_write}, { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, .access =3D PL0_RW, .accessfn =3D pmreg_access_selr, + .fgt =3D FGT_PMSELR_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, + .fgt =3D FGT_PMCCNTR_EL0, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, .accessfn =3D pmreg_access_ccntr }, { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, + .fgt =3D FGT_PMCCNTR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, @@ -2099,32 +2111,38 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCCFILTR_EL0, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .resetvalue =3D 0, }, { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCCFILTR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), .resetvalue =3D 0, }, { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMEVTYPERN_EL0, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMEVTYPERN_EL0, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access_xevcntr, + .fgt =3D FGT_PMEVCNTRN_EL0, .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access_xevcntr, + .fgt =3D FGT_PMEVCNTRN_EL0, .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, @@ -2139,6 +2157,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), .resetvalue =3D 0, @@ -2146,18 +2165,21 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, .resetvalue =3D 0x0 }, { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenclr_write, }, { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenclr_write }, @@ -2293,6 +2315,7 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { /* PMOVSSET is not implemented in v7 before v7ve */ { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, @@ -2300,6 +2323,7 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, @@ -6884,6 +6908,7 @@ static void define_pmu_regs(ARMCPU *cpu) ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_RW, + .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), .accessfn =3D pmreg_access, .writefn =3D pmcr_write, @@ -6893,6 +6918,7 @@ static void define_pmu_regs(ARMCPU *cpu) .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), .resetvalue =3D cpu->isar.reset_pmcr_el0, @@ -6910,23 +6936,27 @@ static void define_pmu_regs(ARMCPU *cpu) { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fgt =3D FGT_PMEVCNTRN_EL0, .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, .accessfn =3D pmreg_access_xevcntr }, { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess_xevcntr, .type =3D ARM_CP_IO, + .fgt =3D FGT_PMEVCNTRN_EL0, .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, .raw_readfn =3D pmevcntr_rawread, .raw_writefn =3D pmevcntr_rawwrite }, { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fgt =3D FGT_PMEVTYPERN_EL0, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .accessfn =3D pmreg_access }, { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .fgt =3D FGT_PMEVTYPERN_EL0, .type =3D ARM_CP_IO, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .raw_writefn =3D pmevtyper_rawwrite }, @@ -6942,10 +6972,12 @@ static void define_pmu_regs(ARMCPU *cpu) { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, }; define_arm_cp_regs(cpu, v81_pmu_regs); @@ -6955,6 +6987,7 @@ static void define_pmu_regs(ARMCPU *cpu) .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, + .fgt =3D FGT_PMMIR_EL1, .resetvalue =3D 0 }; define_one_arm_cp_reg(cpu, &v84_pmmir); @@ -8251,18 +8284,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D cpu->pmceid0 }, { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D cpu->pmceid1 }, }; #ifdef CONFIG_USER_ONLY --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434761; cv=none; d=zohomail.com; s=zohoarc; b=NwJ9HjYCo2T6+4y98ncgibpOV9WKXx8UvAjggxZsc170rb43f6zf0iNKC91e+rgKwYta2nocY9DwawmnZ5SCklhP1/KPz/7PlMHuNwGe9WVWMEaF2TK/ZvYSGECPaQ33Y+3RpOZlJGikE2t6cteccUA3lg5RAl73RZ9jRsQgD3Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0kuEeOGJXchZ8ADATn7eDSLjUofIRhTU/h1wg7+RQIY=; b=uwSrQabT/LxCgMKW7qSGI5DDQYZUCu7c9EQJHE8DH0cOfVec8vUofCtNKUWpydBNkG UIldJPeTIAcQKnfZPfZZiciGFh1pEyJmV+NZL1MlB3mnSQ0rZrNnJkpv1Ojq7q4ePhGN wkS/kRuhX0nNXq+qakoopBiTO6J++321UkxgBMgEAGk3bLKn6ePD2JyN85ZdRZncch+V a6Ag1w07X15WqUjGJ0m1U1k0dBfJ6CwkSwMztbeSBb322ZoTZnCI9D55DmVNGrnofl1g UFj5xC5piOwVik4h/FoHAC2Wj91mYFszrWFMYsaqNKdirVzck8buGOhc/Y+iCmEtZKA6 C37g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0kuEeOGJXchZ8ADATn7eDSLjUofIRhTU/h1wg7+RQIY=; b=udHbysjMQej0Kc5dukYZt7+dqM6d569YgYeZjOzvyt2Sv8JXXoFY2yFIRE9u9qNBAG HxV0PYw0FQB8HAyCsKz1AXzxMbUuY8gWwQBDYnhqHDc2rFBF8vJjPFhZy6F1RNFrJ538 RLdhYTji89IeoBkmfwMfBOeobTrF7Z7HMLnpiGZwSkFMMER9PbOT4KZh1UBW9oLLRuZ6 DVRwnxaDZ/g9XHS2BP0AOWT8zcJcHFpAlqgELrO73yLXyGS5Cld7aEGaTgnaZ+K7PNyg f+Kq7zpdeo7BlIXJGrfL8vta4VmPlS8hrJydQhuJFuALAelKfJFX4rZyhUjZb7yENexN elzg== X-Gm-Message-State: AO0yUKXUOda49MxQrRgROd5KuVHf1MAfxMX/fHaatSeZci8Mobni8vPb tILNeEHoSuUIg8HQX4YYviDgPxFe5UO0dZHz X-Google-Smtp-Source: AK7set9zsUT528NEtUoB21q7NnnLsP6FP13P/XpYxNgbQuU4ZKyWhUQ+yppU98YFaqknoB8Xot01Mw== X-Received: by 2002:a05:600c:4fc8:b0:3df:e46c:7984 with SMTP id o8-20020a05600c4fc800b003dfe46c7984mr3755728wmq.38.1675434591211; Fri, 03 Feb 2023 06:29:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11 Date: Fri, 3 Feb 2023 14:29:20 +0000 Message-Id: <20230203142927.834793-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434761453100001 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 0..11. These bits cover various cache maintenance operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-17-peter.maydell@linaro.org Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org --- target/arm/cpregs.h | 14 ++++++++++++++ target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c37e013b8f3..6596c2a1233 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -646,6 +646,20 @@ typedef enum FGTBit { DO_BIT(HDFGWTR, PMCR_EL0), DO_BIT(HDFGRTR, PMMIR_EL1), DO_BIT(HDFGRTR, PMCEIDN_EL0), + + /* Trap bits in HFGITR_EL2, starting from bit 0 */ + DO_BIT(HFGITR, ICIALLUIS), + DO_BIT(HFGITR, ICIALLU), + DO_BIT(HFGITR, ICIVAU), + DO_BIT(HFGITR, DCIVAC), + DO_BIT(HFGITR, DCISW), + DO_BIT(HFGITR, DCCSW), + DO_BIT(HFGITR, DCCISW), + DO_BIT(HFGITR, DCCVAU), + DO_BIT(HFGITR, DCCVAP), + DO_BIT(HFGITR, DCCVADP), + DO_BIT(HFGITR, DCCIVAC), + DO_BIT(HFGITR, DCZVA), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 2e494b8f924..51866ba70e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5261,6 +5261,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, @@ -5270,21 +5271,26 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIALLUIS, .accessfn =3D access_ticab }, { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIALLU, .accessfn =3D access_tocu }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_ICIVAU, .accessfn =3D access_tocu }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, + .fgt =3D FGT_DCIVAC, .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, + .fgt =3D FGT_DCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, @@ -5292,17 +5298,21 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, + .fgt =3D FGT_DCCSW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCVAU, .accessfn =3D access_tocu }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, + .fgt =3D FGT_DCCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, @@ -7413,6 +7423,7 @@ static const ARMCPRegInfo dcpop_reg[] =3D { { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, }; =20 @@ -7420,6 +7431,7 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, }; #endif /*CONFIG_USER_ONLY*/ @@ -7499,28 +7511,36 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "DC_IGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL1_W, + .fgt =3D FGT_DCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_IGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, + .fgt =3D FGT_DCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_IGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL1_W, + .fgt =3D FGT_DCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_IGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, + .fgt =3D FGT_DCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, + .fgt =3D FGT_DCCSW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, + .fgt =3D FGT_DCCSW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CIGSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, + .fgt =3D FGT_DCCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, + .fgt =3D FGT_DCCISW, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, }; =20 @@ -7542,26 +7562,32 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[]= =3D { { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVADP, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCIVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_GVA", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, @@ -7569,6 +7595,7 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, { .name =3D "DC_GZVA", .state =3D ARM_CP_STATE_AA64, @@ -7577,6 +7604,7 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { #ifndef CONFIG_USER_ONLY /* Avoid overhead of an access check that always passes in user-mode= */ .accessfn =3D aa64_zva_access, + .fgt =3D FGT_DCZVA, #endif }, }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=l4/0NpXlWNPM4wA8sqHiRSyY2vkB5nRmX1x8NuZEF3A=; b=JyAx3o6U2q/idHo43ZFCrSzVQmrCcWM4fYGUcuxqd+J/k4FVMyXq8UvD62YHwZlksA 5sue6GnON0MM59vG9jqRQ7DsE7Cj0Wl22qSiq7oH+vyzLdrGTEq725CpzALhwuVWevxm c7c4A6tE6HvDAbexinWmDnjRoopWeB0k4j4jQZ6HZ5gCMEUGTGeKpTBiQ2xE3aBjphOK zbM6FhyjJKaGXynAVcIgUU6ikesKAbLMb113zJkEpA7FrMlE/R7E+q67IvzyFLVVGP1s bIE1wMKvABtW7Z4ZhqJPaZGlsoFFzyEAnhU7nDTxybSnw/HkKsgfVx0lmvwF4BC3wVfa t0Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l4/0NpXlWNPM4wA8sqHiRSyY2vkB5nRmX1x8NuZEF3A=; b=TyTHyZSe7ejNryaRwb6u2ybfpkuJzhAB+FqO5xA+WgXpenlVBa0ybCRn+ekWMzQeGD 2avC1PbNjGDVTwMz+6hfgY+qs5/pj8lotSaFI0oVtw1VZcZokWOjQNss5z67dgOqPj2Z HDz35t/yL8MTG/vESvP8hN5bJMxkuU00lCSGAI7uhPMZpUoCKAWAP9AN80l0kiE+c5Aa t+YSmm0wCMNqPak9vyXCNn/oIDZUVEJyDPE5pSGK4R0mngwhJleqy4Ty/98jWOAOKjK1 lvjxEyQ87qE1Oh0ziwwd5zPTvg2JVxZORSpXWvVUrzSCxU5JFE66HUtEtUVZg2DTGpdL 3Q7Q== X-Gm-Message-State: AO0yUKWeUtGYqslHhjTDyxSg9z5AeCDXFA+5bhNfcEvoA6vKOyHmfs2B bNAkHtrXkSkAqswTOnkcS1edOsoAw+mdLUvK X-Google-Smtp-Source: AK7set9O1F0xq/ekvBSc9VgRT+xzbDDWGHWQEwykGW6RMylDhNzLy8Clw8KI31x+/X0kSuTcUaCKMw== X-Received: by 2002:a05:600c:3d1b:b0:3db:fc3:6de4 with SMTP id bh27-20020a05600c3d1b00b003db0fc36de4mr10126056wmb.35.1675434592034; Fri, 03 Feb 2023 06:29:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17 Date: Fri, 3 Feb 2023 14:29:21 +0000 Message-Id: <20230203142927.834793-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434690772100009 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 12..17. These bits cover AT address translation instructions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org --- target/arm/cpregs.h | 6 ++++++ target/arm/helper.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 6596c2a1233..1f74308ef5d 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -660,6 +660,12 @@ typedef enum FGTBit { DO_BIT(HFGITR, DCCVADP), DO_BIT(HFGITR, DCCIVAC), DO_BIT(HFGITR, DCZVA), + DO_BIT(HFGITR, ATS1E1R), + DO_BIT(HFGITR, ATS1E1W), + DO_BIT(HFGITR, ATS1E0R), + DO_BIT(HFGITR, ATS1E0W), + DO_BIT(HFGITR, ATS1E1RP), + DO_BIT(HFGITR, ATS1E1WP), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 51866ba70e9..8b9c7fcc3a4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5400,18 +5400,22 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1R, .writefn =3D ats_write64 }, { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1W, .writefn =3D ats_write64 }, { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E0R, .writefn =3D ats_write64 }, { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E0W, .writefn =3D ats_write64 }, { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, @@ -7880,10 +7884,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] =3D { { .name =3D "AT_S1E1RP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1RP, .writefn =3D ats_write64 }, { .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1WP, .writefn =3D ats_write64 }, }; =20 --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434818; cv=none; d=zohomail.com; s=zohoarc; b=dU4T5Pamn+ZrlZmid8UI1bryknqpI9Jyj8UPWAcQM8BVgxfsAwNn8HUHzzLceiZH8ZwjTmd4u8Z4sNoki+I23YrqfJnMYknnSYetReI0BTeXNIbZjxdvfg6dgSprW9pQ7g/4ub5PDvB5NZQNN5nsuFk/vZMlfpVjcH07nHHpCeg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434818; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4Uw8/DYeISr8umhjp5MVaOTabiUrIqChl/nqNJJfyJA=; b=FhQvy2fGYp06MROWmVHJckyqPI8h/VYsIRuLIOgtK5gurho6dSstcM/RgPdauIIBasUG8oUM8Q5kSRI1vPu31iwSlQyr93w2QyXMNsCjLEH3YkV+RoqFpiANSR/8YBpdyae7xd2aZKX3BJsh48JDayIthUixdDDqmjVvZmrfBrI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434818052715.098632927953; Fri, 3 Feb 2023 06:33:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx5R-0008Bf-VO; Fri, 03 Feb 2023 09:30:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4f-0006pb-Q0 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:57 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4b-00054B-Hg for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:57 -0500 Received: by mail-wm1-x330.google.com with SMTP id d4-20020a05600c3ac400b003db1de2aef0so4003066wms.2 for ; Fri, 03 Feb 2023 06:29:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4Uw8/DYeISr8umhjp5MVaOTabiUrIqChl/nqNJJfyJA=; b=P3viyOItoCoLJM2S5ed6Ra84YjFop4hdoiD8mnJ3Ur6juFTUsRFcf1Q11Lduz2XltS Wz9shPrOvQ4YYO221fPRYT5KcmCEbuuK4/uwqxbznd3ev0HtUOqsccHLYTMDo4hlKi75 UpWfpcxpiLKlVVTbPkL2Ix3BCmScWVh1T9Ur4tiN9fiuXc3gJi6Z5c4EP5RkGW4dd+ti T90TuB+XXJnkipvVVlNhCvIzHf3qUOarzMQyttT7PGCz7IfsAVFcYWP1B833b9p6cO7q NkMqV5ScAVN4N0oKM9cX7SBBQcJj5B/87eauF1o/RCOIrsBJksEpnOq/AlRENH8uwjNy sISA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4Uw8/DYeISr8umhjp5MVaOTabiUrIqChl/nqNJJfyJA=; b=Zxl/Ml/C/LzAx73NM5A2P6PTAU8EcaXWoM1Q10jXexHrV/kwZG0IUzKR0BHMqH7OrS fEIKYtLPC113LvkOLou1HyKkLNuB+s8hZqreliCFF1ClWT+1u647UXd4jVfcNCd/W7ce XS1n8o+6dekWAuXN9h8kIWAuUvyU4zXpdXEPZUPJZI5zHWA09tNU2yqmGtnfZKyjGbBo XFDSHIo07NiSEQSZ7zHYtDDkT40JCCvKeS+Wv42Ok4MskL0I/uilbY1zR5qmpMbmHT8X c6f8jCF6W4b2mfQQPdrpAeW69cfF5Darw/MJiSoTCvNwN6KSz563Ojap0RZKXWfDZqED RvQg== X-Gm-Message-State: AO0yUKWXJsKB8ZPYkkYnNq27RN2mE3yMk91M9IEAsGRFIbPoQ406bafF CJpwIMWYqE25dwJ1zLdMHPu40Xji/Qsa2pDa X-Google-Smtp-Source: AK7set9EInWuvDSNrTgH+CGZILslFwcH4XwsVdLS/OwVwSk1z7mrT7v7JhYCIPcxOcjgmksRTAE/YA== X-Received: by 2002:a05:600c:154a:b0:3dc:3398:cf87 with SMTP id f10-20020a05600c154a00b003dc3398cf87mr10207759wmg.11.1675434592847; Fri, 03 Feb 2023 06:29:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47 Date: Fri, 3 Feb 2023 14:29:22 +0000 Message-Id: <20230203142927.834793-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434819855100001 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 18..47. These bits cover TLBI TLB maintenance instructions. (If we implemented FEAT_XS we would need to trap some of the instructions added by that feature using these bits; but we don't yet, so will need to add the .fgt markup when we do.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-19-peter.maydell@linaro.org Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org --- target/arm/cpregs.h | 30 ++++++++++++++++++++++++++++++ target/arm/helper.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1f74308ef5d..2e5ac6b4f98 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -666,6 +666,36 @@ typedef enum FGTBit { DO_BIT(HFGITR, ATS1E0W), DO_BIT(HFGITR, ATS1E1RP), DO_BIT(HFGITR, ATS1E1WP), + DO_BIT(HFGITR, TLBIVMALLE1OS), + DO_BIT(HFGITR, TLBIVAE1OS), + DO_BIT(HFGITR, TLBIASIDE1OS), + DO_BIT(HFGITR, TLBIVAAE1OS), + DO_BIT(HFGITR, TLBIVALE1OS), + DO_BIT(HFGITR, TLBIVAALE1OS), + DO_BIT(HFGITR, TLBIRVAE1OS), + DO_BIT(HFGITR, TLBIRVAAE1OS), + DO_BIT(HFGITR, TLBIRVALE1OS), + DO_BIT(HFGITR, TLBIRVAALE1OS), + DO_BIT(HFGITR, TLBIVMALLE1IS), + DO_BIT(HFGITR, TLBIVAE1IS), + DO_BIT(HFGITR, TLBIASIDE1IS), + DO_BIT(HFGITR, TLBIVAAE1IS), + DO_BIT(HFGITR, TLBIVALE1IS), + DO_BIT(HFGITR, TLBIVAALE1IS), + DO_BIT(HFGITR, TLBIRVAE1IS), + DO_BIT(HFGITR, TLBIRVAAE1IS), + DO_BIT(HFGITR, TLBIRVALE1IS), + DO_BIT(HFGITR, TLBIRVAALE1IS), + DO_BIT(HFGITR, TLBIRVAE1), + DO_BIT(HFGITR, TLBIRVAAE1), + DO_BIT(HFGITR, TLBIRVALE1), + DO_BIT(HFGITR, TLBIRVAALE1), + DO_BIT(HFGITR, TLBIVMALLE1), + DO_BIT(HFGITR, TLBIVAE1), + DO_BIT(HFGITR, TLBIASIDE1), + DO_BIT(HFGITR, TLBIVAAE1), + DO_BIT(HFGITR, TLBIVALE1), + DO_BIT(HFGITR, TLBIVAALE1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b9c7fcc3a4..5b9cc087e28 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5318,50 +5318,62 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVMALLE1IS, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAE1IS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIASIDE1IS, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAAE1IS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVALE1IS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAALE1IS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVMALLE1, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVAE1, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIASIDE1, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVAAE1, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVALE1, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIVAALE1, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, @@ -7175,50 +7187,62 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAE1IS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAAE1IS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVALE1IS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAALE1IS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAE1OS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAAE1OS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVALE1OS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIRVAALE1OS, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIRVAE1, .writefn =3D tlbi_aa64_rvae1_write }, { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIRVAAE1, .writefn =3D tlbi_aa64_rvae1_write }, { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIRVALE1, .writefn =3D tlbi_aa64_rvae1_write }, { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .fgt =3D FGT_TLBIRVAALE1, .writefn =3D tlbi_aa64_rvae1_write }, { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, @@ -7290,26 +7314,32 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVMALLE1OS, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, + .fgt =3D FGT_TLBIVAE1OS, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIASIDE1OS, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAAE1OS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVALE1OS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAALE1OS, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434661; cv=none; d=zohomail.com; s=zohoarc; b=BQZKKR5AGpZzHNoY8FHYzDkwk+QgvW12L5S1rCf2Ge0lttyRxJuwDxLYQ9DbTU62HI7+QjSX9WEbM2/yezrTRLNz8BfuFeBpldJ1a0LzNu0nMuuGfy0gH57rhB0SD68FB+G/Mz06mE80hUVEtEHZJ1N0qE14WZT8XQtFqq0/XTo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434661; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=K2xxnob3/roFGLD087p6MyGRfXODxkAp5LJkBKCgYJQ=; b=PisbtmTPlprY7uJgKO9dr130HwaV6I0k/581DvL/Ur1rRt1o9kX0WtKcKRfLAiO9dB uz+lDZtKar+gY/3EI8nmSVEg/mTvcOWTS0My/OMBsOhV5wwA2gKHsUBdPuwbLPqBwV1T mOybnQZwg+ZKNLK3pDud/yJHjw5WAiVBVvU4+NpyZBXEA/GHKM7bU/7JmlQcDhXr1Dsp 9pdS/fjYfr/9wxyAwBAVLu4ppPSPluAK8KJvgHtJg6M72j5+jQNpAZqj85bJzw6Na1Ua uSzodVHKnEMqfNWKiuK/TTTtFgX+NcrlH8YuXTpJswZiSIRB82FdYTqvOKo2UgJIzcTT o6Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K2xxnob3/roFGLD087p6MyGRfXODxkAp5LJkBKCgYJQ=; b=qsvlPlzjAL/BJKFwnJjsWqRdpUW1ZiVYSHZYXUIeA2YbSdmq+Xcc2jNL7W0+eQxDWY 1OWB3TqMAdf+ejY6+H39rGQTTvvzqGc09tIj8khfy6PpLBM4i0rC7jxoL1T7r19TGbpD 2KqPaCDeA3oMAXuaK1/Dpzyweo78na3swYlPWfqEm9R38GKxoxyfRIoT52Jul3bQmP2m Lr+dqfAAFs0CTFkQa03uDXIoE3WcYEKqnfYSZFRsk4eadQisdO1lt8PyaG+je1nG8OyN 6Q0xTQtnYUGMVN+71fPBq/OUpJrf4Xn5jSYsTgnCXOtmUfszuz4FtxkgioBXVSiAC9Sg kCGA== X-Gm-Message-State: AO0yUKWDbkEQHv7h7bL4eMMJOKAFGTqPeQPf3/8QjhDBJ0NnkT82L5AL sLk3BCjwahOUIN7N2KDN3L0Gn3vQt5tuOgos X-Google-Smtp-Source: AK7set92dXak9YmbUOnuQWb/BW6qCoI8EiiyKUADxChCEG7IVrqI9cv8JZCj88GO3ZLW18MOWTLydA== X-Received: by 2002:a05:600c:4e4e:b0:3dd:e621:d328 with SMTP id e14-20020a05600c4e4e00b003dde621d328mr12317510wmq.8.1675434593694; Fri, 03 Feb 2023 06:29:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63 Date: Fri, 3 Feb 2023 14:29:23 +0000 Message-Id: <20230203142927.834793-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434662592100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 48..63. Some of these bits are for trapping instructions which are not in the system instruction encoding (i.e. which are not handled by the ARMCPRegInfo mechanism): * ERET, ERETAA, ERETAB * SVC We will have to handle those separately and manually. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-20-peter.maydell@linaro.org Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org --- target/arm/cpregs.h | 4 ++++ target/arm/helper.c | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2e5ac6b4f98..efcf9181b97 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -696,6 +696,10 @@ typedef enum FGTBit { DO_BIT(HFGITR, TLBIVAAE1), DO_BIT(HFGITR, TLBIVALE1), DO_BIT(HFGITR, TLBIVAALE1), + DO_BIT(HFGITR, CFPRCTX), + DO_BIT(HFGITR, DVPRCTX), + DO_BIT(HFGITR, CPPRCTX), + DO_BIT(HFGITR, DCCVAC), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 5b9cc087e28..c0403aadae2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5295,6 +5295,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, @@ -7588,10 +7589,12 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[]= =3D { { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, @@ -7747,24 +7750,30 @@ static CPAccessResult access_predinv(CPUARMState *e= nv, const ARMCPRegInfo *ri, static const ARMCPRegInfo predinv_reginfo[] =3D { { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .fgt =3D FGT_CFPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .fgt =3D FGT_DVPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .fgt =3D FGT_CPPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, /* * Note the AArch32 opcodes have a different OPC1. */ { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .fgt =3D FGT_CFPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .fgt =3D FGT_DVPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .fgt =3D FGT_CPPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UAP+fyEZ6YJZ2unHEOswKIVrra1c/Fd0zQr/S3C4us4=; b=aKil9Sh1GkE65ytO0w6SNI8F27YJZstpRQKd1TZf4cGLTdNirsw3U2xIILuyFdwCId v1bGk9bRdv43eiuBpn8qEscGHTqGRy6Ry2RkJMZam9D+0ei7QT+mvTdM1QtT+acxjGrD vzdrttUy1YuMiAocC+WdQ82ww4AR4lmQu0iDYDQwNj5OmwHlVOdy+Mj9879KfF4B/p8r u+FN4ViqvclnCQRoYZ8Bu2yeGTfn7dvOygOo8mIw1/kSADZsIgXK+fHmlNs9fsyZ3opl YIwQHE8BrG9JcLKYIN9MomGE0/UN+VTpYaOHVO1A/miBxOg43Vm/xUgOJ6+ihzGcmoH0 JIzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UAP+fyEZ6YJZ2unHEOswKIVrra1c/Fd0zQr/S3C4us4=; b=XX8rE8FeBrQU8uvBZfgDxcwvFUk8/FsnynZYHrf/bjeJeovydUbqFv1MOjpf8T2q1E HMibXbLcfl8kWQGMHYjoOB01HN6Eo9R9keOhVeWGX273Bbkzh+/V4RxmM1nRlY19waw7 393bPYrPiqb3gPiKbfqRhy2bxWWmPosIy9TTDwJ9VJDkGPXDXg09f+Wt0SNK+PKVCgyU ed3PRBVFNAMD+ZrVZkfk+Bn7j91qbkz+9HzrHGExFPcYkrUBHCkmHjgfiMF5OjUN220+ rZeuYfaCYP/qR0ZpobmuQmSc9hLoBeaWK9ZXy82EZG82QSYOg1kHDO3F5NmUtkL5h5VA 2mLQ== X-Gm-Message-State: AO0yUKX4S1yTXLJLrb+kFn/iErbzVtBBMFlDsqZAkZFOQOL4pJ81XBPK 3vU2Wa331O0H4VJSWLWUqQL89g68IdbuN5kY X-Google-Smtp-Source: AK7set+yK4ipRJPauiQsEi7ZWIwD4rlKT7BHwwCqa9Mmgmv52UlUB2PiLmhnVAcbDn0L08WDyeiqdw== X-Received: by 2002:a05:600c:a0d:b0:3dc:4f2c:c856 with SMTP id z13-20020a05600c0a0d00b003dc4f2cc856mr10468469wmp.32.1675434594556; Fri, 03 Feb 2023 06:29:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap Date: Fri, 3 Feb 2023 14:29:24 +0000 Message-Id: <20230203142927.834793-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434940926100001 Content-Type: text/plain; charset="utf-8" Implement the HFGITR_EL2.ERET fine-grained trap. This traps execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is reported with a syndrome value of 0x1a. The trap must take precedence over a possible pointer-authentication trap for ERETAA and ERETAB. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org --- target/arm/cpu.h | 1 + target/arm/syndrome.h | 10 ++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 3 +++ target/arm/translate-a64.c | 10 ++++++++++ 5 files changed, 26 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5cc81bec9bf..ec2a7716ce7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3245,6 +3245,7 @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) FIELD(TBFLAG_A64, SVL, 24, 4) /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. = */ FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) +FIELD(TBFLAG_A64, FGT_ERET, 29, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 73df5e37938..d27d1bc31f0 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -48,6 +48,7 @@ enum arm_exception_class { EC_AA64_SMC =3D 0x17, EC_SYSTEMREGISTERTRAP =3D 0x18, EC_SVEACCESSTRAP =3D 0x19, + EC_ERETTRAP =3D 0x1a, EC_SMETRAP =3D 0x1d, EC_INSNABORT =3D 0x20, EC_INSNABORT_SAME_EL =3D 0x21, @@ -215,6 +216,15 @@ static inline uint32_t syn_sve_access_trap(void) return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; } =20 +/* + * eret_op is bits [1:0] of the ERET instruction, so: + * 0 for ERET, 2 for ERETAA, 3 for ERETAB. + */ +static inline uint32_t syn_erettrap(int eret_op) +{ + return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; +} + static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) { return (EC_SMETRAP << ARM_EL_EC_SHIFT) diff --git a/target/arm/translate.h b/target/arm/translate.h index 599902016dc..62a7706eabd 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -132,6 +132,8 @@ typedef struct DisasContext { bool mve_no_pred; /* True if fine-grained traps are active */ bool fgt_active; + /* True if fine-grained trap on ERET is enabled */ + bool fgt_eret; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index c0403aadae2..6151c775053 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12065,6 +12065,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, =20 if (arm_fgt_active(env, el)) { DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET= )) { + DP_TBFLAG_A64(flags, FGT_ERET, 1); + } } =20 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a47dab4f1dd..11bfa3f717a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2385,6 +2385,10 @@ static void disas_uncond_b_reg(DisasContext *s, uint= 32_t insn) if (op4 !=3D 0) { goto do_unallocated; } + if (s->fgt_eret) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), = 2); + return; + } dst =3D tcg_temp_new_i64(); tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUARMState, elr_el[s->current_el])); @@ -2398,6 +2402,11 @@ static void disas_uncond_b_reg(DisasContext *s, uint= 32_t insn) if (rn !=3D 0x1f || op4 !=3D 0x1f) { goto do_unallocated; } + /* The FGT trap takes precedence over an auth trap. */ + if (s->fgt_eret) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), = 2); + return; + } dst =3D tcg_temp_new_i64(); tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUARMState, elr_el[s->current_el])); @@ -14742,6 +14751,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); + dc->fgt_eret =3D EX_TBFLAG_A64(tb_flags, FGT_ERET); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl =3D (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434814; cv=none; d=zohomail.com; s=zohoarc; b=E40wHMIFb7xC9u40VPErJY8KAQkuvo+EbEkE4xT6DRY0Kw4V12g2MgUfaXY+q4ErgQSqaQwCLXHpQu/ZHXZeae5SuuvGaB4H8TsgL81hRilEeqHLHMvyhs9RhXZuSTLW6dompmctD37qg6daUQAso9ZWSpEc/9fE0q/46YCdknU= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=l0u5UibgcI5qnW9GrxT+wU1ixlLChLWV7gMBX8MNisg=; b=NIX3HPCcyhL1s/JRKSFZatiTI0/FkQsTH2xtnHnUeHI8zm3XsdmP0J7eKWy9oiWEHM WvF4YlY188KyBd+3IASUswUQeIMWa2jIHQrPJBif/yI0bkv+a8OslDr/U4S8mTlEgi78 3a1oZ8Hhc6dmli6LF2I9qaX8vxVdBcg7KbMis+VVxf68ZG4XuikXxQjn2aJzO2bkLE95 xJ6Gf+HZVgH/3NVZPKhhrfm84//WsX/7o2njAETOnTUav+3CxPgFWUCaWZttcMWJYbCB /4uvdd42uGJQRB0fCoev7xt63iq1mzHuamChsja7a3VBZ4eLUG0addZS5avmtGrznfq/ rCDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l0u5UibgcI5qnW9GrxT+wU1ixlLChLWV7gMBX8MNisg=; b=fttKeYRZ4qlDvimXDWIwMnlE7/0C+9LpD9wLeZrNjARmxUQDohNen6WrAzLAT9GMlm hhbbPQA9d3/PUp044SrXGi+DLTuuN/HMLPk0kQ2bDcQl2006hgaC6sEuUjZZMq9Yio65 BRHP4p9M5lAqgRcvxE5zLZ6vNWRzjILV7qA1/NDyxuN/w6jPiiYbgj7eJd+JNPspPkB3 rl8WtTTzhIqS7AGlRHR45wf6mzyQ0G+MwsKncF1BwqeiG4kqkQSfHTiiageHODM7xGKo 0dqNEqDFFn4Hgzs6sPxgciCRoUYi0Nbo4uXpljMKgMHe7d+GemGTkUccEL2l7IV6CPkr A/FA== X-Gm-Message-State: AO0yUKVSgEUsq1OIA3kcG1GsDOSOjDYnDK1GhOPbJBUJqL4n7R3Yob66 OmsDadJI9UpIOJmB47slNw/K0Npp8NgulJWO X-Google-Smtp-Source: AK7set/t0G7d2VvGLlXGyQTQHvFxJ2sd7olfu7ekECLS4zcVXekf8LmSbtasnMsRt4jRmv56WAx9TA== X-Received: by 2002:a05:600c:a297:b0:3dc:42e7:f626 with SMTP id hu23-20020a05600ca29700b003dc42e7f626mr9618890wmb.26.1675434595402; Fri, 03 Feb 2023 06:29:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps Date: Fri, 3 Feb 2023 14:29:25 +0000 Message-Id: <20230203142927.834793-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434815714100005 Content-Type: text/plain; charset="utf-8" Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps. These trap execution of the SVC instruction from AArch32 and AArch64. (As usual, AArch32 can only trap from EL0, as fine grained traps are disabled with an AArch32 EL1.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org --- target/arm/cpu.h | 1 + target/arm/translate.h | 2 ++ target/arm/helper.c | 20 ++++++++++++++++++++ target/arm/translate-a64.c | 9 ++++++++- target/arm/translate.c | 12 +++++++++--- 5 files changed, 40 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec2a7716ce7..7bc97fece97 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3171,6 +3171,7 @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) +FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index 62a7706eabd..3717824b754 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -134,6 +134,8 @@ typedef struct DisasContext { bool fgt_active; /* True if fine-grained trap on ERET is enabled */ bool fgt_eret; + /* True if fine-grained trap on SVC is enabled */ + bool fgt_svc; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 6151c775053..c62ed05c122 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11842,6 +11842,20 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 +static inline bool fgt_svc(CPUARMState *env, int el) +{ + /* + * Assuming fine-grained-traps are active, return true if we + * should be trapping on SVC instructions. Only AArch64 can + * trap on an SVC at EL1, but we don't need to special-case this + * because if this is AArch32 EL1 then arm_fgt_active() is false. + * We also know el is 0 or 1. + */ + return el =3D=3D 0 ? + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0)= : + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -11927,6 +11941,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState= *env, int fp_el, =20 if (arm_fgt_active(env, el)) { DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } } =20 if (env->uncached_cpsr & CPSR_IL) { @@ -12068,6 +12085,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET= )) { DP_TBFLAG_A64(flags, FGT_ERET, 1); } + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } } =20 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 11bfa3f717a..bbfadb7c2e8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2179,6 +2179,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) int opc =3D extract32(insn, 21, 3); int op2_ll =3D extract32(insn, 0, 5); int imm16 =3D extract32(insn, 5, 16); + uint32_t syndrome; =20 switch (opc) { case 0: @@ -2189,8 +2190,13 @@ static void disas_exc(DisasContext *s, uint32_t insn) */ switch (op2_ll) { case 1: /* SVC= */ + syndrome =3D syn_aa64_svc(imm16); + if (s->fgt_svc) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + break; + } gen_ss_advance(s); - gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16)); + gen_exception_insn(s, 4, EXCP_SWI, syndrome); break; case 2: /* HVC= */ if (s->current_el =3D=3D 0) { @@ -14751,6 +14757,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); + dc->fgt_svc =3D EX_TBFLAG_ANY(tb_flags, FGT_SVC); dc->fgt_eret =3D EX_TBFLAG_A64(tb_flags, FGT_ERET); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); diff --git a/target/arm/translate.c b/target/arm/translate.c index 3f51dc6a6bf..c23a3462bfc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8834,9 +8834,14 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) (a->imm =3D=3D semihost_imm)) { gen_exception_internal_insn(s, EXCP_SEMIHOST); } else { - gen_update_pc(s, curr_insn_len(s)); - s->svc_imm =3D a->imm; - s->base.is_jmp =3D DISAS_SWI; + if (s->fgt_svc) { + uint32_t syndrome =3D syn_aa32_svc(a->imm, s->thumb); + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + } else { + gen_update_pc(s, curr_insn_len(s)); + s->svc_imm =3D a->imm; + s->base.is_jmp =3D DISAS_SWI; + } } return true; } @@ -9417,6 +9422,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active =3D EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); + dc->fgt_svc =3D EX_TBFLAG_ANY(tb_flags, FGT_SVC); =20 if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled =3D 1; --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434790; cv=none; d=zohomail.com; s=zohoarc; b=g6MMFw5kSwU5sjPvUt0d5Qe+T9BFbr0p4Xnhz4SedvhxpxmahN0ttH1sD6+WRii35WgQ3laQ1JEDtbVAHMVK0z4Yl3tFskvr0B7zK5yaFVzVlL5XKzcTJ2m4aOm4RT3h/dC4YweeZKtbjmgZkOvJguHzPpJ3w0EKVrizNfxbvS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434790; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xTqYZJo21mR+70Kxpz8qplBoPvCqRYvqTyvegNRGHKw=; b=gwQqcCxwetDInQbd7fkMf567FsmZBD+fV5+OXeFc72CekDCvPo1vPHUGyfjkEygtqb /NLS6pRoSv3mTzXCIDcC7plXRIPKKLKaiBl1BuM9heL1/ZDf9PjIJ2KC6H2SarVGkvle FIGd+Pa9v9e61HWHnPQNoG5y+gFBVpjlOf7R/Wb+gPEFlRri4aXypinELPvaGoRGqB+d a88wJDKLnp9WKfSxn1LxxKCn19gygvdnwxep2sNTWGbOlNx0g3rDnnWUOsYY6RmWZrjO 76/J6iX2ptifSewiv1qQMi2TIXWCc1etjhudCkeHP1plSgdSICowKqHSEEyFeoSrM5yh xuWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xTqYZJo21mR+70Kxpz8qplBoPvCqRYvqTyvegNRGHKw=; b=ubF8mpsPkMk64LlbFOBp6pkIeIz/jPvrY6dYnw6A813eeJ+xEe6/sulRmVd2ra8v+V HLBWDQUTZAqUQSlcqILwCnOu4GoGNqB3AfgQv2eew1QfcDYPTiEltyU5brtO40kVBPXW iQhZlQ0r1VfH2SXYHOqphoiGerlF4gYWXOftA9fhWlD2KYIJvxTvoZ30C9xyn9ptIHqZ vjIrJSAmK0xv5Z+VjHKsjpeThyIGAjUEFzW0a9+KDCuUK3ae8su1yzL+dO96CDnJapJM MSzFY0gM/CYZ7LcASseehg1DuUYfNIFZVhpLOJ9daNyd4zPVXLvKFSpwRuzHk9Wwx3pB TFpQ== X-Gm-Message-State: AO0yUKWiJQFTrekhd1wCINzTHEybgbQ7xnCAgAS5Sse5ZzuQqDnwZtXn Bu4QgTrNS1/FdWE/HQ5+ng14D+N3SnS5+lbZ X-Google-Smtp-Source: AK7set+IxgoN6eWdxdwnkf0Uj01kIXXKyfvCNAXc8SFUS3/sxoTjR8Nl+jnNplsTQyObXAJ3XsX/LA== X-Received: by 2002:a05:600c:210a:b0:3df:12db:2779 with SMTP id u10-20020a05600c210a00b003df12db2779mr8940780wml.3.1675434596198; Fri, 03 Feb 2023 06:29:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps Date: Fri, 3 Feb 2023 14:29:26 +0000 Message-Id: <20230203142927.834793-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434791566100001 Content-Type: text/plain; charset="utf-8" FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0, MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their AArch32 equivalents). This trapping is independent of whether fine-grained traps are enabled or not. Implement these extra traps. (We don't implement DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org --- target/arm/debug_helper.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b106746b0e1..3c671c88c1a 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -599,6 +599,33 @@ static CPAccessResult access_tda(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* + * Check for traps to Debug Comms Channel registers. If FEAT_FGT + * is implemented then these are controlled by MDCR_EL2.TDCC for + * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by + * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA. + */ +static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || + (arm_hcr_el2_eff(env) & HCR_TGE); + bool mdcr_el2_tdcc =3D cpu_isar_feature(aa64_fgt, env_archcpu(env)) && + (mdcr_el2 & MDCR_TDCC); + bool mdcr_el3_tdcc =3D cpu_isar_feature(aa64_fgt, env_archcpu(env)) && + (env->cp15.mdcr_el3 & MDCR_TDCC); + + if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -681,7 +708,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { */ { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, + .access =3D PL0_R, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_E= L0. @@ -689,11 +716,11 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { */ { .name =3D "OSDTRRX_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, + .access =3D PL1_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "OSDTRTX_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, + .access =3D PL1_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * OSECCR_EL1 provides a mechanism for an operating system @@ -757,7 +784,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { */ { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, + .access =3D PL1_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_NOP }, /* * Dummy DBGCLAIM registers. --=20 2.34.1 From nobody Thu Apr 25 16:49:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675435031; cv=none; d=zohomail.com; s=zohoarc; b=h87UoxV4WOQnfQuatysg4E59Y8GEQuEUVkCJizAvLgCIqnbeRdMjlIKv71NJRvjZ4Y25g4iu7v/s15BVam0WpCgLtMyXTg9H2HrC0c0dZNCWuBH2cMSXFkbr/frs8LNwR2UpfUo8736cmfpPeZQDOFKyi4imNcYbVGhzyqBEb3s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675435031; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L2nnqzPfORcCpUIAV2HyeXVRQVeoYBVIUoJ05tbUvrM=; b=i7xScj2N4CS/x7cR4AGK0dxk7GAPf+ACYCYatxOg5BvzZCi61kIA3NrDXZuQ/Ooym8Fa+sYsnJW8wtfX/rViTZmoFvL8ih+/yY/Wx6ODA0KRefC5+okTzYi9XOxvY7S+oGAZLNH//K1cW7KiPCYo9U+n2pHaIpMwYwUO7X3+xkI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167543503101795.30313227434635; Fri, 3 Feb 2023 06:37:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx5X-0000Sq-BO; Fri, 03 Feb 2023 09:30:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4i-0006tr-Lc for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:30:00 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4f-00053Z-R0 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:30:00 -0500 Received: by mail-wm1-x334.google.com with SMTP id hn2-20020a05600ca38200b003dc5cb96d46so6125856wmb.4 for ; Fri, 03 Feb 2023 06:29:57 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=L2nnqzPfORcCpUIAV2HyeXVRQVeoYBVIUoJ05tbUvrM=; b=NT96SRFcdwVoomEJAZrxvJiJs9Ol0Sf83+iAGijF5aoM9Au4TEMvoZoh54e/JyuBOq wpIWezoU9k1i2/yATyrVbzM9BbZgD4djza81vYFcLtkf1gxrHufQDAh1bBpzSJ46hHri 1qihFAtHD+pvYOChTwkl0JlLxij4ZyHEOT1VhzMYaFaV5mbG4CAIdPirfcivFct7tFF7 WDG58J1Fxw68TmUzU46rbIW7umaINpwgZ82Q1bA6bprZYl55gm5tpe7y6X7hdv+kbot9 K0qsWyyhsTD91TIhknOVHSsa1A7DmkFX0r33qLjqHIoMkOcNqsqBxvapUhHon77lXnCh 7FRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L2nnqzPfORcCpUIAV2HyeXVRQVeoYBVIUoJ05tbUvrM=; b=AESzYs+4zxjwPzPT4cnjbw/d0Y/9AHeCzvFWxhF+u978CYc3Ua62Arh7iTNfM4yBve ibzq/x70M8dxMA+7aoJmkPgy3SDAIhYSFRemG9spC3nXPUM4TGxaIo2p0Zlu6gxpKXk7 79elt5gs9RtYjB+yV0SqM3eKhkC4d+eygHlu3qUwbX79blkan6gQxUZ9G6aFuXAhr+WH dTyVi0R7CPVpXsrWJtp6L18weivV6Cp8VP2sZ+P1a5mj4y9MdsIxaYNBJjI6XF3rJIBF 7F614J5jeHG28fInzvWusN2AVPL4sGGgM1lcFRJtp0g1arl3ffgbi96xLWxCffP7+uNe cR8w== X-Gm-Message-State: AO0yUKVUtczpQBMo4UW1mCtZGEA/RwaBMjHGN54MXO//UYGQaKY/qPbE Z+MG8KKkUTo8mQ2jgnaDN/KjC+nedi8MgDof X-Google-Smtp-Source: AK7set9aTC8lEUcCUUr/efS2rL3vyLbw4/36ePYPxjI2LWWXktZxzN/+MCmPHlZND2jJVdxtExmBlA== X-Received: by 2002:a7b:cd17:0:b0:3dc:4f65:553e with SMTP id f23-20020a7bcd17000000b003dc4f65553emr10745119wmj.3.1675434597097; Fri, 03 Feb 2023 06:29:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max' Date: Fri, 3 Feb 2023 14:29:27 +0000 Message-Id: <20230203142927.834793-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675435032356100001 Content-Type: text/plain; charset="utf-8" Update the ID registers for TCG's '-cpu max' to report the presence of FEAT_FGT Fine-Grained Traps support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b87e064d9dc..2062d712610 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -30,6 +30,7 @@ the following architecture extensions: - FEAT_ETS (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) - FEAT_FCMA (Floating-point complex number instructions) +- FEAT_FGT (Fine-Grained Traps) - FEAT_FHM (Floating-point half-precision multiplication instructions) - FEAT_FP16 (Half-precision floating-point data processing) - FEAT_FRINTTS (Floating-point to integer instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0e021960fb5..4066950da15 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1224,6 +1224,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; --=20 2.34.1