From nobody Tue May 13 15:54:36 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1675434870; cv=none; d=zohomail.com; s=zohoarc; b=GZd4BzrkBYIC/IsJFAZnKsewRAXy5tYQsYAN9a5NMbcYAkNw6317FOGy7GywNvL2HmRf+bEGzns13mPP/X9iq4UzXHeO8tPtAXIRVVBs7LXwoq9Ay7eULNqFz7RcLJGp2VxxLjLLvY0KcW9ar3BES5pDK9sB3hEf2nk8lUh9QX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675434870; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yQxmFDzxxFrhEVqQzCA0FWZTs2ofEI2+0Euyqm2fY1E=; b=A2Xg8B8n95vGThs9yy9CnqYTG8fHFyhdm0VmRkNJ+TUcehfvzaZPRamremVNhtWkndELCg2UVQSpmwr1HSY9lR6g1PTrT67bGSVsB5K4cveiYKhSMj9z6agpVL6wYYWmP5b10Zi6SKAuJv3FnJfiMFr9B6FI7Op14cuNxAcnYPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675434870848248.715927662519; Fri, 3 Feb 2023 06:34:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNx4h-0006tW-OB; Fri, 03 Feb 2023 09:29:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNx4a-0006i6-Ht for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:53 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNx4X-000572-2d for qemu-devel@nongnu.org; Fri, 03 Feb 2023 09:29:51 -0500 Received: by mail-wm1-x334.google.com with SMTP id j32-20020a05600c1c2000b003dc4fd6e61dso6130144wms.5 for ; Fri, 03 Feb 2023 06:29:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yQxmFDzxxFrhEVqQzCA0FWZTs2ofEI2+0Euyqm2fY1E=; b=vn3ejJCBVKvfaKNXNgXAMDtPSngk3iqzBj1CwoqAauUWhW0GtxbxP/PuZlskIK1Dec 1WsmgsjFv68IFr1dSUDpMEmrC2QM60frjnLCKBnODw7clEyych1B3dKwbDz+GNDIo0rB T12tEg/HPGIvLv20CnSgbIoGpWSB6sGfazwGw9yzSrHgJA2zxyfFh4RtIhIUcut/EWJq 86yQ4NzvOPWlAENtGU1BkQBI7ltLlDNQTtjJecncdn9caLSAbWIaPIx2+JRPppwVXhTq XMA29uaOtIYP/yfPa9N1/UAP+jd6YFKXSdiWpq/2PrxaogTF80heGDxjqdn8i0q1ok2D Mp6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yQxmFDzxxFrhEVqQzCA0FWZTs2ofEI2+0Euyqm2fY1E=; b=LIEPqlE9Ivb7En7tTnSgiIvUAebxVz86sChjJk8h+xbHDU+aqNGhky4URxQiu8m3qu GE1lE+y3Wx9r07VzX6E/HjLHCIegMhtG7irqCqVvcVYXC3FYGU2KuCR6Q9f2kqpp6/lW VmrsS5k5+f4X9sg2MSenU3tDuOTVRZxetXigODVpsePa7q9HOQGKviDCEDIj/5MAVjYx IYJ17dlE5PynB58r0LCNScWKna9GecF8MxFsgs4W9j4CtiIKzUl9Ti+7LfP6KlZSBVWX hbNACdLoh4WP0rS/0fxaYcyhDr5UO24J67zrPr8trA3TxkzHNKRzFeQkHlUI5D+6t5XU tnig== X-Gm-Message-State: AO0yUKVbKE12ii0PlyJ50dh1s3hytYs2eYqOCri1/wwHiIwgM066drjl fyqS8p8ld0ELYjPTP3/2455cIYd9x7nmSuLe X-Google-Smtp-Source: AK7set+tdBRj2q+iONCgcqrAFkvTexPqGqoH+dVqNefECuXzuzh4DB8PyOfnJQqAteyiGCG7aW5f/w== X-Received: by 2002:a05:600c:3c9b:b0:3dc:46e8:982 with SMTP id bg27-20020a05600c3c9b00b003dc46e80982mr9496370wmb.19.1675434586066; Fri, 03 Feb 2023 06:29:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11 Date: Fri, 3 Feb 2023 14:29:14 +0000 Message-Id: <20230203142927.834793-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434872273100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 0..11. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org --- target/arm/cpregs.h | 14 ++++++++++++++ target/arm/helper.c | 17 +++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 8cc12045af6..82f2cefff0a 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -577,6 +577,20 @@ typedef enum FGTBit { FGT_HDFGRTR =3D FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), FGT_HDFGWTR =3D FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), FGT_HFGITR =3D FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), + + /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ + DO_BIT(HFGRTR, AFSR0_EL1), + DO_BIT(HFGRTR, AFSR1_EL1), + DO_BIT(HFGRTR, AIDR_EL1), + DO_BIT(HFGRTR, AMAIR_EL1), + DO_BIT(HFGRTR, APDAKEY), + DO_BIT(HFGRTR, APDBKEY), + DO_BIT(HFGRTR, APGAKEY), + DO_BIT(HFGRTR, APIAKEY), + DO_BIT(HFGRTR, APIBKEY), + DO_BIT(HFGRTR, CCSIDR_EL1), + DO_BIT(HFGRTR, CLIDR_EL1), + DO_BIT(HFGRTR, CONTEXTIDR_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 2389e41bd07..30e54455ac7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -633,6 +633,7 @@ static const ARMCPRegInfo cp_reginfo[] =3D { { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_CONTEXTIDR_EL1, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, @@ -2163,6 +2164,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, .access =3D PL1_R, .accessfn =3D access_tid4, + .fgt =3D FGT_CCSIDR_EL1, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW }, { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, @@ -2179,6 +2181,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid1, + .fgt =3D FGT_AIDR_EL1, .resetvalue =3D 0 }, /* * Auxiliary fault status registers: these also are IMPDEF, and we @@ -2187,10 +2190,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AFSR0_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AFSR1_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * MAIR can just read-as-written because we don't implement caches @@ -4392,6 +4397,7 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_AMAIR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, @@ -7041,42 +7047,52 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { { .name =3D "APDAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apda.lo) }, { .name =3D "APDAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apda.hi) }, { .name =3D "APDBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apdb.lo) }, { .name =3D "APDBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APDBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apdb.hi) }, { .name =3D "APGAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APGAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apga.lo) }, { .name =3D "APGAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APGAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apga.hi) }, { .name =3D "APIAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apia.lo) }, { .name =3D "APIAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIAKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apia.hi) }, { .name =3D "APIBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apib.lo) }, { .name =3D "APIBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, + .fgt =3D FGT_APIBKEY, .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, }; =20 @@ -7940,6 +7956,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_tid4, + .fgt =3D FGT_CLIDR_EL1, .resetvalue =3D cpu->clidr }; define_one_arm_cp_reg(cpu, &clidr); --=20 2.34.1