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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=p6ebWUhLxy1Vko9RKec4Spu2hlMYvJ/5ZZfi2NMMhLY=; b=m3o7g7LhK5q8cqpL4j091RrVmUQyFzUloPWMHfgS+aNbhLD14RDz9TMgnliR1aokHH 9qysRQNs0JHAsuijtYaouh4EUL8WTTmbd+rR5JLoO912pPfHcjx3CeCReigSecuvOCqW NNrb8JQvVbP5bj5KPq+YLd69xjtH14gv4kqUvI1qg/Z/hNF8xmYbxb4CP1dDeqCOyiyt KAPjS5jL8cC2GV3n3Jt6xV4ISU4vygfL/+srEAR7hQJkMz5faAUtB3fdFbqKJ0ssRccf Ho1WQlj64n9Qk39LgN7fSmeehOvsAxAfYVfuX7qFOSSoDHd8KlMDK7PUCv1cYB6IAVzY eOdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p6ebWUhLxy1Vko9RKec4Spu2hlMYvJ/5ZZfi2NMMhLY=; b=Me2y9esak2Rjo55hWDAachaL/aCNBGKseebG1yipo90fBBEPZJsWZRWYXUfRrvehhw tKjgUh5gqzBJYUSjAgfk+wa0DhyjJkn7VYk2iqAdWye9bFu4pfaFSAVLUqdeoirQW5ag XtOIPUcu7Z8PsVpE9yacDNgvNEBvb87DVlEcVpjV5SHsPOQ8eupdbJoliOVM/75jWey3 b5N4TGqCedJEmH9VVLHygtO4xail3QNSrlSkvgx0+r/6rvp5bq0dctE49DedCJVzMLge HmiuDh9Hapig+7GBrYfCKGoIB4Sh5ng0XrOThxKuv36wIKFM4M1uJfw2w8t/XpLAJlgV zS8A== X-Gm-Message-State: AO0yUKUayy8Kv3lyCY40NjasDNJt6gleZ8z7yh2V2g47nfRYhzVk7cPb KgDLcxNcd43A+4zJHgrRKYcZhhrujBNgAYxL X-Google-Smtp-Source: AK7set8KuWmlOkW4EOxa54HPMyi426+Rm56hT7BXKaOl4StLiVo8iQ3Yps6CbTWqhOnSxKYAEz0vqA== X-Received: by 2002:a05:600c:1d83:b0:3cf:68d3:3047 with SMTP id p3-20020a05600c1d8300b003cf68d33047mr9499897wms.41.1675434586946; Fri, 03 Feb 2023 06:29:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23 Date: Fri, 3 Feb 2023 14:29:15 +0000 Message-Id: <20230203142927.834793-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434799600100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 12..23. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/helper.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 82f2cefff0a..67d87ae8bf5 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -591,6 +591,18 @@ typedef enum FGTBit { DO_BIT(HFGRTR, CCSIDR_EL1), DO_BIT(HFGRTR, CLIDR_EL1), DO_BIT(HFGRTR, CONTEXTIDR_EL1), + DO_BIT(HFGRTR, CPACR_EL1), + DO_BIT(HFGRTR, CSSELR_EL1), + DO_BIT(HFGRTR, CTR_EL0), + DO_BIT(HFGRTR, DCZID_EL0), + DO_BIT(HFGRTR, ESR_EL1), + DO_BIT(HFGRTR, FAR_EL1), + DO_BIT(HFGRTR, ISR_EL1), + DO_BIT(HFGRTR, LORC_EL1), + DO_BIT(HFGRTR, LOREA_EL1), + DO_BIT(HFGRTR, LORID_EL1), + DO_BIT(HFGRTR, LORN_EL1), + DO_BIT(HFGRTR, LORSA_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 30e54455ac7..c059935d0e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -869,6 +869,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, + .fgt =3D FGT_CPACR_EL1, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, }; @@ -2170,6 +2171,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tid4, + .fgt =3D FGT_CSSELR_EL1, .writefn =3D csselr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, @@ -2233,6 +2235,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, { .name =3D "ISR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, + .fgt =3D FGT_ISR_EL1, .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, /* 32 bit ITLB invalidates */ { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, @@ -4135,6 +4138,7 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_FAR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, }; @@ -4143,6 +4147,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fgt =3D FGT_ESR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, @@ -5215,6 +5220,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, + .fgt =3D FGT_DCZID_EL0, .readfn =3D aa64_dczid_read }, { .name =3D "DC_ZVA", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 1, @@ -7005,22 +7011,27 @@ static const ARMCPRegInfo lor_reginfo[] =3D { { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORSA_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LOREA_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORN_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_lor_other, + .fgt =3D FGT_LORC_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, .access =3D PL1_R, .accessfn =3D access_lor_ns, + .fgt =3D FGT_LORID_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 @@ -8619,6 +8630,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "CTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 0, .crm =3D = 0, .access =3D PL0_R, .accessfn =3D ctr_el0_access, + .fgt =3D FGT_CTR_EL0, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ { .name =3D "TCMTR", --=20 2.34.1