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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BhearbGMg07ixmxcVta7913JfgZva0wWKZfBDKaes20=; b=p7NvEgSosXD4LYrwXJ4g74fQ+yZQPaezsBGjT2jGQNfO2d35npqIJ5Uu8KKwRSpXIC fsSedcPm4NT0bdd+h9OaXUoHGRN3gS4mLNvwawhpHHy2yVMEL88NKbEZs5EZi5dF/l6L /403ZexQ4/gZ9FssTW+djsXO2PdWsrAcj/92eoCCNqvPXWihyRG+m4CMDY3zQSiEulaE 42EDysb4MGQBjsqIZE7/zWWx4Gklb52iZyYOwtIjQRi6uIxfiqs73fEfyzF4lNKBR/na DN+z7ue5zmhNGqjH1vGhQHQmCQDFSXmI7lnYau1hFVpTB5lBCmvMO9mql5wxQtvkdVaT zAJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BhearbGMg07ixmxcVta7913JfgZva0wWKZfBDKaes20=; b=KFldb80Tu3kEsrjY8kS/07sBlWu6IsryeSuz3X4zG17vk6G1SpKJAv7gA20LvjbPkm wuOsNeNfyR0oSxYLoq9pkWQaG7ZGaU1xxzJN+StUX3WccTjfof/5JobgZZFCQoJbSk4M IXUXVNc2qGunCMhsiGNSDN8P18QePDckyDoxsc5WUKUxX3O42L69klwKVKF6nOCk7D9o rRzf1E9ShzATRO/CRGOpxAjyaXsqaYbRv8NNmUTse0AHzC2XzufJVoENVzULYWA6EnZw sOa7v5BybaayLN/JvtCqmv3rpm4/79UFqIlh7U0iJnXmkFlwawCVlJqWmvAzq266NTyt E/fg== X-Gm-Message-State: AO0yUKU+YknsSD77SFviGn/OY02603hao1172937ifj2LVyqNIaCDkFj TF2wAMGa8XMYM/AksIssRGSMhQ/Z24DszORE X-Google-Smtp-Source: AK7set+nBXMGKj/0n3AcB56hzkZm1rib3k9E4TUBvYBJYSFujlFj1MK77V9fhlWTS190TfyOPk1lPw== X-Received: by 2002:a05:600c:1c81:b0:3dc:5987:fe9 with SMTP id k1-20020a05600c1c8100b003dc59870fe9mr10183749wms.2.1675434589544; Fri, 03 Feb 2023 06:29:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11 Date: Fri, 3 Feb 2023 14:29:18 +0000 Message-Id: <20230203142927.834793-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434739279100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitons for the registers trapped by HDFGRTR/HDFGWTR bits 0..11. These cover various debug related registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-15-peter.maydell@linaro.org Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/debug_helper.c | 11 +++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index fef8ad08acc..7c4d07ed9c6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -622,6 +622,18 @@ typedef enum FGTBit { DO_BIT(HFGRTR, ERRIDR_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), + + /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ + DO_BIT(HDFGRTR, DBGBCRN_EL1), + DO_BIT(HDFGRTR, DBGBVRN_EL1), + DO_BIT(HDFGRTR, DBGWCRN_EL1), + DO_BIT(HDFGRTR, DBGWVRN_EL1), + DO_BIT(HDFGRTR, MDSCR_EL1), + DO_BIT(HDFGRTR, DBGCLAIM), + DO_BIT(HDFGWTR, OSLAR_EL1), + DO_BIT(HDFGRTR, OSLSR_EL1), + DO_BIT(HDFGRTR, OSECCR_EL1), + DO_BIT(HDFGRTR, OSDLR_EL1), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cced3f168d0..b106746b0e1 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -672,6 +672,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_MDSCR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), .resetvalue =3D 0 }, /* @@ -702,6 +703,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "OSECCR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_OSECCR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as @@ -717,16 +719,19 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSLAR_EL1, .writefn =3D oslar_write }, { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, .access =3D PL1_R, .resetvalue =3D 10, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSLSR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, /* Dummy OSDLR_EL1: 32-bit Linux will read this */ { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, .access =3D PL1_RW, .accessfn =3D access_tdosa, + .fgt =3D FGT_OSDLR_EL1, .writefn =3D osdlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.osdlr_el1) }, /* @@ -763,10 +768,12 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 = =3D 6, .type =3D ARM_CP_ALIAS, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGCLAIM, .writefn =3D dbgclaimset_write, .readfn =3D dbgclaimset_read }, { .name =3D "DBGCLAIMCLR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 = =3D 6, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGCLAIM, .writefn =3D dbgclaimclr_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgclaim) }, }; @@ -1127,12 +1134,14 @@ void define_debug_regs(ARMCPU *cpu) { .name =3D dbgbvr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGBVRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write }, { .name =3D dbgbcr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGBCRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write }, @@ -1149,12 +1158,14 @@ void define_debug_regs(ARMCPU *cpu) { .name =3D dbgwvr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGWVRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write }, { .name =3D dbgwcr_el1_name, .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, .access =3D PL1_RW, .accessfn =3D access_tda, + .fgt =3D FGT_DBGWCRN_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write }, --=20 2.34.1