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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wbeG3RqWepmqfpgsVO1uBd1T8UYDoP87EdSf0MfbsLw=; b=JiSPmtpu0/QbG5yWmnQfYg7R8CCCGCSB8HEV/ZT+51UvNinajG9Sv25mZWyCeiG2wN r59lpdTGpqLuqDW1BvUbZXiOfF1kpryUZcdYc2xzXuLq0XG/0UwhbPyDz4dK0NUqnTnu IKbkNz81fjks5sA8Heuc2iOQkloHHE7F/45qBZhBq1Fv+QwyoUsqM/DM0IlHxsY67qpk 2AKuu/iLzqRfJDxJYdLqBWjMmHBYkZ7a0GKEaCRMblxaMjDwwCyv9AFwHa0IqLRocEmV 8nmlZjV3OjN1J9sVvc91RCWChsioxjFJZisHcfvPkf+wnImDlC7JUvWp8tyzZlkZmwhP lyzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wbeG3RqWepmqfpgsVO1uBd1T8UYDoP87EdSf0MfbsLw=; b=kD2BJiIEPWYq6yAM1ITFZzN8BQ45bd/32v27CGsDMszUPwizoEFlihhmeYw4O87iN8 x56fMkfaLlRBTuFRbB8pE2+Uz+sfd0x/RTMLmctlHgDK2vaQPHRokfjQ9fJslnOpLk14 KqIVRWfP8O2fSPL+czn+2DSPc0f77OvLj2LfINEhmnId5FjMzOKfg2tHmvjuQgusIGhI RRLoXFP4u6nqcDqVA7YxAl02urqdvwFdqNxaIsGlXM2/fkf0srE5HKGuMiXE3XBR1Z7E xdk4H0dDjczK0eEoCtOIgXpGgnrc1Qbjz1wmBeES1q730MAO5DNOSN5W3x3q40puiud+ h2Lw== X-Gm-Message-State: AO0yUKV7XnHVnBbwHmIBj2dPemIV+sqtfhAG9x8717tfjTSB/PovcfiX ANYqYgl169m57TBTpCI36WRY0WHsdEIrj0QG X-Google-Smtp-Source: AK7set+E6CB1wWGMYvVjoLXu0IlvF1SRcMSHlXIr8CpeuQMV4UBHnjtriOeGfpwcLGqih0O3Jj/+kA== X-Received: by 2002:a05:6000:1007:b0:2c1:15b8:9eb7 with SMTP id a7-20020a056000100700b002c115b89eb7mr8348968wrx.59.1675434590353; Fri, 03 Feb 2023 06:29:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63 Date: Fri, 3 Feb 2023 14:29:19 +0000 Message-Id: <20230203142927.834793-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434654654100005 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the registers trapped by HDFGRTR/HDFGWTR bits 12..x. Bits 12..22 and bit 58 are for PMU registers. The remaining bits in HDFGRTR/HDFGWTR are for traps on registers that are part of features we don't implement: Bits 23..32 and 63 : FEAT_SPE Bits 33..48 : FEAT_ETE Bits 50..56 : FEAT_TRBE Bits 59..61 : FEAT_BRBE Bit 62 : FEAT_SPEv1p2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-16-peter.maydell@linaro.org Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org --- target/arm/cpregs.h | 12 ++++++++++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7c4d07ed9c6..c37e013b8f3 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -634,6 +634,18 @@ typedef enum FGTBit { DO_BIT(HDFGRTR, OSLSR_EL1), DO_BIT(HDFGRTR, OSECCR_EL1), DO_BIT(HDFGRTR, OSDLR_EL1), + DO_BIT(HDFGRTR, PMEVCNTRN_EL0), + DO_BIT(HDFGRTR, PMEVTYPERN_EL0), + DO_BIT(HDFGRTR, PMCCFILTR_EL0), + DO_BIT(HDFGRTR, PMCCNTR_EL0), + DO_BIT(HDFGRTR, PMCNTEN), + DO_BIT(HDFGRTR, PMINTEN), + DO_BIT(HDFGRTR, PMOVS), + DO_BIT(HDFGRTR, PMSELR_EL0), + DO_BIT(HDFGWTR, PMSWINC_EL0), + DO_BIT(HDFGWTR, PMCR_EL0), + DO_BIT(HDFGRTR, PMMIR_EL1), + DO_BIT(HDFGRTR, PMCEIDN_EL0), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index a48b022def6..2e494b8f924 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2035,21 +2035,25 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenset_write, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .raw_writefn =3D raw_write }, { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, .type =3D = ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL0_RW, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .writefn =3D pmcntenclr_write, .type =3D ARM_CP_ALIAS | ARM_CP_IO }, { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, @@ -2057,41 +2061,49 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .fgt =3D FGT_PMSWINC_EL0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .writefn =3D pmswinc_write }, { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .fgt =3D FGT_PMSWINC_EL0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .writefn =3D pmswinc_write }, { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fgt =3D FGT_PMSELR_EL0, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), .accessfn =3D pmreg_access_selr, .writefn =3D pmselr_write, .raw_writefn =3D raw_write}, { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, .access =3D PL0_RW, .accessfn =3D pmreg_access_selr, + .fgt =3D FGT_PMSELR_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, + .fgt =3D FGT_PMCCNTR_EL0, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, .accessfn =3D pmreg_access_ccntr }, { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, + .fgt =3D FGT_PMCCNTR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, @@ -2099,32 +2111,38 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCCFILTR_EL0, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .resetvalue =3D 0, }, { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCCFILTR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), .resetvalue =3D 0, }, { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMEVTYPERN_EL0, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMEVTYPERN_EL0, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access_xevcntr, + .fgt =3D FGT_PMEVCNTRN_EL0, .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .accessfn =3D pmreg_access_xevcntr, + .fgt =3D FGT_PMEVCNTRN_EL0, .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, @@ -2139,6 +2157,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), .resetvalue =3D 0, @@ -2146,18 +2165,21 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, .resetvalue =3D 0x0 }, { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenclr_write, }, { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenclr_write }, @@ -2293,6 +2315,7 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { /* PMOVSSET is not implemented in v7 before v7ve */ { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, @@ -2300,6 +2323,7 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, @@ -6884,6 +6908,7 @@ static void define_pmu_regs(ARMCPU *cpu) ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_RW, + .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), .accessfn =3D pmreg_access, .writefn =3D pmcr_write, @@ -6893,6 +6918,7 @@ static void define_pmu_regs(ARMCPU *cpu) .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), .resetvalue =3D cpu->isar.reset_pmcr_el0, @@ -6910,23 +6936,27 @@ static void define_pmu_regs(ARMCPU *cpu) { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fgt =3D FGT_PMEVCNTRN_EL0, .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, .accessfn =3D pmreg_access_xevcntr }, { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess_xevcntr, .type =3D ARM_CP_IO, + .fgt =3D FGT_PMEVCNTRN_EL0, .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, .raw_readfn =3D pmevcntr_rawread, .raw_writefn =3D pmevcntr_rawwrite }, { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fgt =3D FGT_PMEVTYPERN_EL0, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .accessfn =3D pmreg_access }, { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .fgt =3D FGT_PMEVTYPERN_EL0, .type =3D ARM_CP_IO, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .raw_writefn =3D pmevtyper_rawwrite }, @@ -6942,10 +6972,12 @@ static void define_pmu_regs(ARMCPU *cpu) { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, }; define_arm_cp_regs(cpu, v81_pmu_regs); @@ -6955,6 +6987,7 @@ static void define_pmu_regs(ARMCPU *cpu) .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, + .fgt =3D FGT_PMMIR_EL1, .resetvalue =3D 0 }; define_one_arm_cp_reg(cpu, &v84_pmmir); @@ -8251,18 +8284,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D cpu->pmceid0 }, { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D cpu->pmceid1 }, }; #ifdef CONFIG_USER_ONLY --=20 2.34.1