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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=K2xxnob3/roFGLD087p6MyGRfXODxkAp5LJkBKCgYJQ=; b=PisbtmTPlprY7uJgKO9dr130HwaV6I0k/581DvL/Ur1rRt1o9kX0WtKcKRfLAiO9dB uz+lDZtKar+gY/3EI8nmSVEg/mTvcOWTS0My/OMBsOhV5wwA2gKHsUBdPuwbLPqBwV1T mOybnQZwg+ZKNLK3pDud/yJHjw5WAiVBVvU4+NpyZBXEA/GHKM7bU/7JmlQcDhXr1Dsp 9pdS/fjYfr/9wxyAwBAVLu4ppPSPluAK8KJvgHtJg6M72j5+jQNpAZqj85bJzw6Na1Ua uSzodVHKnEMqfNWKiuK/TTTtFgX+NcrlH8YuXTpJswZiSIRB82FdYTqvOKo2UgJIzcTT o6Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K2xxnob3/roFGLD087p6MyGRfXODxkAp5LJkBKCgYJQ=; b=qsvlPlzjAL/BJKFwnJjsWqRdpUW1ZiVYSHZYXUIeA2YbSdmq+Xcc2jNL7W0+eQxDWY 1OWB3TqMAdf+ejY6+H39rGQTTvvzqGc09tIj8khfy6PpLBM4i0rC7jxoL1T7r19TGbpD 2KqPaCDeA3oMAXuaK1/Dpzyweo78na3swYlPWfqEm9R38GKxoxyfRIoT52Jul3bQmP2m Lr+dqfAAFs0CTFkQa03uDXIoE3WcYEKqnfYSZFRsk4eadQisdO1lt8PyaG+je1nG8OyN 6Q0xTQtnYUGMVN+71fPBq/OUpJrf4Xn5jSYsTgnCXOtmUfszuz4FtxkgioBXVSiAC9Sg kCGA== X-Gm-Message-State: AO0yUKWDbkEQHv7h7bL4eMMJOKAFGTqPeQPf3/8QjhDBJ0NnkT82L5AL sLk3BCjwahOUIN7N2KDN3L0Gn3vQt5tuOgos X-Google-Smtp-Source: AK7set92dXak9YmbUOnuQWb/BW6qCoI8EiiyKUADxChCEG7IVrqI9cv8JZCj88GO3ZLW18MOWTLydA== X-Received: by 2002:a05:600c:4e4e:b0:3dd:e621:d328 with SMTP id e14-20020a05600c4e4e00b003dde621d328mr12317510wmq.8.1675434593694; Fri, 03 Feb 2023 06:29:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63 Date: Fri, 3 Feb 2023 14:29:23 +0000 Message-Id: <20230203142927.834793-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434662592100003 Content-Type: text/plain; charset="utf-8" Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 48..63. Some of these bits are for trapping instructions which are not in the system instruction encoding (i.e. which are not handled by the ARMCPRegInfo mechanism): * ERET, ERETAA, ERETAB * SVC We will have to handle those separately and manually. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Fuad Tabba Message-id: 20230130182459.3309057-20-peter.maydell@linaro.org Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org --- target/arm/cpregs.h | 4 ++++ target/arm/helper.c | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2e5ac6b4f98..efcf9181b97 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -696,6 +696,10 @@ typedef enum FGTBit { DO_BIT(HFGITR, TLBIVAAE1), DO_BIT(HFGITR, TLBIVALE1), DO_BIT(HFGITR, TLBIVAALE1), + DO_BIT(HFGITR, CFPRCTX), + DO_BIT(HFGITR, DVPRCTX), + DO_BIT(HFGITR, CPPRCTX), + DO_BIT(HFGITR, DCCVAC), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/helper.c b/target/arm/helper.c index 5b9cc087e28..c0403aadae2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5295,6 +5295,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, @@ -7588,10 +7589,12 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[]= =3D { { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, + .fgt =3D FGT_DCCVAC, .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, @@ -7747,24 +7750,30 @@ static CPAccessResult access_predinv(CPUARMState *e= nv, const ARMCPRegInfo *ri, static const ARMCPRegInfo predinv_reginfo[] =3D { { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .fgt =3D FGT_CFPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .fgt =3D FGT_DVPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .fgt =3D FGT_CPPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, /* * Note the AArch32 opcodes have a different OPC1. */ { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .fgt =3D FGT_CFPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .fgt =3D FGT_DVPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .fgt =3D FGT_CPPRCTX, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, }; =20 --=20 2.34.1