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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c130e00b003df241f52e8sm2578492wmf.42.2023.02.03.06.29.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 06:29:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vPVJCWB3C3sZSgsGNanDCbKT7SX6LCAO601kW+euxik=; b=FpBIaM3XdddGB2IqZS6R6yqeKLqK6EJv9gHWvP6NcL8r8e3HrOK+f7xwhPDegBBZxE 7bgdmGRo5q/qvcuhZq4lcYYVDUSbovpuFFy2DEsT3qDQBVx1lpXRosPD1dFpJqpzJSIQ gGWEccvvUpTR+0lBRLh1+pMGRrpDe0WmR9BQgosv0saE9wwejkuAS/6MhYeNhngRw2aR ZQxPayLjM9eu0jvGBoXR3fOASwhJTDaiaX7VIWbsCbskpBMAMHQGn+9cK0BMRIl0HPYj 0oVrGK9zam2EVoxb5lgtrqdrsNpLPPlikgMjjHYGcRi5sO/slugTCQUlB1n/1V3HZZLw fA/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vPVJCWB3C3sZSgsGNanDCbKT7SX6LCAO601kW+euxik=; b=QwuKdKfgEVT8uCpSMmlaqZVHRgUC/Lo2rd+Kme9EIYpH35Qfuzb6IKvnP9bqQifEr+ FReG7KDhqlo77llb5VZ9ffY9m2FPaqCdpePtrAREIvp3op6yuQRlwxmcsfExxfJOq41Y aCewqYiHMRneWSNO6RgX4X0ow2Jcp8b+xn+YXWA4pS+K+2QX+X3kQftRtWXjm0j2wPsE o1uW5uo7H1iEaq2lGRHCDlgbb6FersYviu8sxQFziTqYpT/Wx52nI4n2S2rUKMG8bvBF pKEhiS8thuh6C9dz/8eaTUa1PxQUnjqOx6wmuEGQ38RngUuION0m46Ne5RsC7WeqcD2e NpqA== X-Gm-Message-State: AO0yUKXAOGvhNZpQ2Qwa7r/wJBZNXnTs+qYnZe38Wmo+C+xVvVb7bpHg SULdkvon6l291Pnr7ufYTxg/ciF6cIzFWpTQ X-Google-Smtp-Source: AK7set8JjjZnBojYAoZb036LVdh5Ta9k6ZTCZqi4fP63my9/p4AadujjH6zMH5cnZS1RKX2JWnBABQ== X-Received: by 2002:a5d:5092:0:b0:2bf:9468:340 with SMTP id a18-20020a5d5092000000b002bf94680340mr7874118wrt.19.1675434574257; Fri, 03 Feb 2023 06:29:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset Date: Fri, 3 Feb 2023 14:29:00 +0000 Message-Id: <20230203142927.834793-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org> References: <20230203142927.834793-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675434703056100003 Content-Type: text/plain; charset="utf-8" From: Evgeny Iakovlev Current FIFO handling code does not reset RXFE/RXFF flags when guest resets FIFO by writing to UARTLCR register, although internal FIFO state is reset to 0 read count. Actual guest-visible flag update will happen only on next data read or write attempt. As a result of that any guest that expects RXFE flag to be set (and RXFF to be cleared) after resetting FIFO will never see that happen. Signed-off-by: Evgeny Iakovlev Reviewed-by: Peter Maydell Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell --- hw/char/pl011.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index ca7537d8ed2..c15cb7af20b 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -92,6 +92,16 @@ static inline unsigned pl011_get_fifo_depth(PL011State *= s) return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; } =20 +static inline void pl011_reset_fifo(PL011State *s) +{ + s->read_count =3D 0; + s->read_pos =3D 0; + + /* Reset FIFO flags */ + s->flags &=3D ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF); + s->flags |=3D PL011_FLAG_RXFE | PL011_FLAG_TXFE; +} + static uint64_t pl011_read(void *opaque, hwaddr offset, unsigned size) { @@ -239,8 +249,7 @@ static void pl011_write(void *opaque, hwaddr offset, case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & 0x10) { - s->read_count =3D 0; - s->read_pos =3D 0; + pl011_reset_fifo(s); } if ((s->lcr ^ value) & 0x1) { int break_enable =3D value & 0x1; @@ -450,12 +459,11 @@ static void pl011_reset(DeviceState *dev) s->ilpr =3D 0; s->ibrd =3D 0; s->fbrd =3D 0; - s->read_pos =3D 0; - s->read_count =3D 0; s->read_trigger =3D 1; s->ifl =3D 0x12; s->cr =3D 0x300; - s->flags =3D 0x90; + s->flags =3D 0; + pl011_reset_fifo(s); } =20 static void pl011_class_init(ObjectClass *oc, void *data) --=20 2.34.1