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bh=H87psRagJYTdzx3tENLQCPSm9o01fzQsLmOMat36+r4=; b=KsK62vldtwTS1i3JJNpxOeQ39dZ40BreGACxkWhvq5ZMLyGZdidkIj0LaKT8PgJ2LsdWoI c4Ie2gZC2P/AtKua0fSs4klfoia2x6CzGJ0ZErtYCmnUTBqRdD7IJr9T8kny62l3Xv6+Sa oF1AmAZOqHUxQ/tsqJWS893mi/M8+1c= X-MC-Unique: PVumxtSrMxurjDg8s3hAdg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, richard.henderson@linaro.org, peter.maydell@linaro.org, pbonzini@redhat.com, qemu-devel@nongnu.org Subject: [PATCH] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Date: Fri, 3 Feb 2023 18:16:57 +0100 Message-Id: <20230203171657.2867598-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1675444661525100003 Content-Type: text/plain; charset="utf-8" Many registers whose 'cooked' writefns induce TLB maintenance do not have raw_writefn ops defined. If only the writefn ops is set (ie. no raw_writefn is provided), it is assumed the cooked also work as the raw one. For those registers it is not obvious the tlb_flush works on KVM mode so better/safer setting the raw write. Signed-off-by: Eric Auger Suggested-by: Peter Maydell --- I'am not familiar with those callbacks. I have tested in kvm accelerated mode including migration but I fail to test with TCG. It SIGSEVs for me even without my additions. I am not sure whether the .raw_writefn must be set only for registers only doing some TLB maintenance or shall be set safely on other registers doing TLB maintenance + other state settings. --- target/arm/helper.c | 242 +++++++++++++++++++++++--------------------- 1 file changed, 128 insertions(+), 114 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 72b37b7cf1..cf92812aa3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -718,16 +718,20 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. */ { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, .writefn =3D tlbia= ll_write, + .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, + .writefn =3D tlbiall_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "TLBIMVA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, .writefn =3D tlbim= va_write, + .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, + .writefn =3D tlbimva_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "TLBIASID", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, .writefn =3D tlbia= sid_write, + .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, + .writefn =3D tlbiasid_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "TLBIMVAA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim= vaa_write, + .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, + .writefn =3D tlbimvaa_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, @@ -2229,52 +2233,52 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* 32 bit ITLB invalidates */ { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiall_write }, + .writefn =3D tlbiall_write, .raw_writefn =3D raw_write }, { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, + .writefn =3D tlbimva_write, .raw_writefn =3D raw_write }, { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 5, .opc2 =3D 2, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiasid_write }, + .writefn =3D tlbiasid_write, .raw_writefn =3D raw_write }, /* 32 bit DTLB invalidates */ { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiall_write }, + .writefn =3D tlbiall_write, .raw_writefn =3D raw_write }, { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, + .writefn =3D tlbimva_write, .raw_writefn =3D raw_write }, { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 6, .opc2 =3D 2, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiasid_write }, + .writefn =3D tlbiasid_write, .raw_writefn =3D raw_write }, /* 32 bit TLB invalidates */ { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 0, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiall_write }, + .writefn =3D tlbiall_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, + .writefn =3D tlbimva_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 2, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiasid_write }, + .writefn =3D tlbiasid_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimvaa_write }, + .writefn =3D tlbimvaa_write, .raw_writefn =3D raw_write }, }; =20 static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { /* 32 bit TLB invalidates, Inner Shareable */ { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbiall_is_write }, + .writefn =3D tlbiall_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbimva_is_write }, + .writefn =3D tlbimva_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbiasid_is_write }, + .writefn =3D tlbiasid_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbimvaa_is_write }, + .writefn =3D tlbimvaa_is_write, .raw_writefn =3D raw_write }, }; =20 static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { @@ -3912,12 +3916,12 @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D access_tvm_trvm, - .readfn =3D prbar_read, .writefn =3D prbar_write }, + .readfn =3D prbar_read, .writefn =3D prbar_write, .raw_writefn =3D r= aw_write }, { .name =3D "PRLAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D access_tvm_trvm, - .readfn =3D prlar_read, .writefn =3D prlar_write }, + .readfn =3D prlar_read, .writefn =3D prlar_write, .raw_writefn =3D r= aw_write }, { .name =3D "PRSELR", .resetvalue =3D 0, .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, @@ -3926,11 +3930,13 @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] =3D { { .name =3D "HPRBAR", .resetvalue =3D 0, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, - .readfn =3D hprbar_read, .writefn =3D hprbar_write }, + .readfn =3D hprbar_read, + .writefn =3D hprbar_write, .raw_writefn =3D raw_write }, { .name =3D "HPRLAR", .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, - .readfn =3D hprlar_read, .writefn =3D hprlar_write }, + .readfn =3D hprlar_read, + .writefn =3D hprlar_write, .raw_writefn =3D raw_write }, { .name =3D "HPRSELR", .resetvalue =3D 0, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, .access =3D PL2_RW, @@ -3939,7 +3945,8 @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] =3D { { .name =3D "HPRENR", .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 1, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, - .readfn =3D hprenr_read, .writefn =3D hprenr_write }, + .readfn =3D hprenr_read, + .writefn =3D hprenr_write, .raw_writefn =3D raw_write }, }; =20 static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { @@ -3951,17 +3958,17 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { { .name =3D "DRBAR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.drbar), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .raw_writefn =3D= raw_write, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "DRSR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, .= opc2 =3D 2, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.drsr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .raw_writefn =3D= raw_write, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "DRACR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 4, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.dracr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .raw_writefn =3D= raw_write, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, .access =3D PL1_RW, @@ -4139,13 +4146,13 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -4403,13 +4410,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_write, .raw_writefn =3D raw_write }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_write, .raw_writefn =3D raw_write }, }; =20 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5260,83 +5267,83 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vmalle1is_write }, + .writefn =3D tlbi_aa64_vmalle1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, + .writefn =3D tlbi_aa64_vae1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vmalle1is_write }, + .writefn =3D tlbi_aa64_vmalle1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, + .writefn =3D tlbi_aa64_vae1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, + .writefn =3D tlbi_aa64_vae1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, + .writefn =3D tlbi_aa64_vae1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vmalle1_write }, + .writefn =3D tlbi_aa64_vmalle1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1_write }, + .writefn =3D tlbi_aa64_vae1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vmalle1_write }, + .writefn =3D tlbi_aa64_vmalle1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1_write }, + .writefn =3D tlbi_aa64_vae1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1_write }, + .writefn =3D tlbi_aa64_vae1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1_write }, + .writefn =3D tlbi_aa64_vae1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1is_write }, + .writefn =3D tlbi_aa64_ipas2e1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1is_write }, + .writefn =3D tlbi_aa64_ipas2e1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, + .writefn =3D tlbi_aa64_alle1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, + .writefn =3D tlbi_aa64_alle1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1_write }, + .writefn =3D tlbi_aa64_ipas2e1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1_write }, + .writefn =3D tlbi_aa64_ipas2e1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1_write }, + .writefn =3D tlbi_aa64_alle1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, + .writefn =3D tlbi_aa64_alle1is_write, .raw_writefn =3D raw_write }, #ifndef CONFIG_USER_ONLY /* 64 bit address translation operations */ { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, @@ -5390,39 +5397,39 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* TLB invalidate last level of translation table walk */ { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbimva_is_write }, + .writefn =3D tlbimva_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbimvaa_is_write }, + .writefn =3D tlbimvaa_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, + .writefn =3D tlbimva_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimvaa_write }, + .writefn =3D tlbimvaa_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_write }, + .writefn =3D tlbimva_hyp_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVALHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_is_write }, + .writefn =3D tlbimva_hyp_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIIPAS2", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_hyp_write }, + .writefn =3D tlbiipas2_hyp_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIIPAS2IS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2is_hyp_write }, + .writefn =3D tlbiipas2is_hyp_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIIPAS2L", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_hyp_write }, + .writefn =3D tlbiipas2_hyp_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIIPAS2LIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2is_hyp_write }, + .writefn =3D tlbiipas2is_hyp_write, .raw_writefn =3D raw_write }, /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_ticab = }, @@ -5823,12 +5830,12 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_write }, + .writefn =3D hcr_write, .raw_writefn =3D raw_write }, { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_writelow }, + .writefn =3D hcr_writelow, .raw_writefn =3D raw_write }, { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -5895,6 +5902,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, + .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, @@ -5911,10 +5919,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2), - .writefn =3D vttbr_write }, + .writefn =3D vttbr_write, .raw_writefn =3D raw_write }, { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .writefn =3D vttbr_write, + .access =3D PL2_RW, .writefn =3D vttbr_write, .raw_writefn =3D raw_w= rite, .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2) }, { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, @@ -5926,7 +5934,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el= 2_write, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D vmsa_tcr_ttbr_el2_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, @@ -5934,47 +5943,47 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "TLBIALLNSNH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_nsnh_write }, + .writefn =3D tlbiall_nsnh_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIALLNSNHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_nsnh_is_write }, + .writefn =3D tlbiall_nsnh_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIALLH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_hyp_write }, + .writefn =3D tlbiall_hyp_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIALLHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_hyp_is_write }, + .writefn =3D tlbiall_hyp_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVAH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_write }, + .writefn =3D tlbimva_hyp_write, .raw_writefn =3D raw_write }, { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_is_write }, + .writefn =3D tlbimva_hyp_is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_alle2_write }, + .writefn =3D tlbi_aa64_alle2_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2_write }, + .writefn =3D tlbi_aa64_vae2_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2_write }, + .writefn =3D tlbi_aa64_vae2_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_alle2is_write }, + .writefn =3D tlbi_aa64_alle2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, + .writefn =3D tlbi_aa64_vae2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, + .writefn =3D tlbi_aa64_vae2is_write, .raw_writefn =3D raw_write }, #ifndef CONFIG_USER_ONLY /* * Unlike the other EL2-related AT operations, these must @@ -6063,7 +6072,7 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_RW, .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), - .writefn =3D hcr_writehigh }, + .writefn =3D hcr_writehigh, .raw_writefn =3D raw_write }, }; =20 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6113,12 +6122,12 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), - .resetfn =3D scr_reset, .writefn =3D scr_write }, + .resetfn =3D scr_reset, .writefn =3D scr_write, .raw_writefn =3D raw= _write }, { .name =3D "SCR", .type =3D ARM_CP_ALIAS | ARM_CP_NEWEL, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.scr_el3), - .writefn =3D scr_write }, + .writefn =3D scr_write, .raw_writefn =3D raw_write }, { .name =3D "SDER32_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, .access =3D PL3_RW, .resetvalue =3D 0, @@ -6185,27 +6194,27 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "TLBI_ALLE3IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3is_write }, + .writefn =3D tlbi_aa64_alle3is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE3IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, + .writefn =3D tlbi_aa64_vae3is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE3IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, + .writefn =3D tlbi_aa64_vae3is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ALLE3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3_write }, + .writefn =3D tlbi_aa64_alle3_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3_write }, + .writefn =3D tlbi_aa64_vae3_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3_write }, + .writefn =3D tlbi_aa64_vae3_write, .raw_writefn =3D raw_write }, }; =20 #ifndef CONFIG_USER_ONLY @@ -7113,19 +7122,19 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_rvae1_write }, + .writefn =3D tlbi_aa64_rvae1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_rvae1_write }, + .writefn =3D tlbi_aa64_rvae1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_rvae1_write }, + .writefn =3D tlbi_aa64_rvae1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_rvae1_write }, + .writefn =3D tlbi_aa64_rvae1_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, @@ -7137,11 +7146,11 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, + .writefn =3D tlbi_aa64_rvae2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, + .writefn =3D tlbi_aa64_rvae2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, @@ -7153,19 +7162,19 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, + .writefn =3D tlbi_aa64_rvae2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, + .writefn =3D tlbi_aa64_rvae2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2_write }, + .writefn =3D tlbi_aa64_rvae2_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2_write }, + .writefn =3D tlbi_aa64_rvae2_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, @@ -7196,47 +7205,47 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vmalle1is_write }, + .writefn =3D tlbi_aa64_vmalle1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, + .writefn =3D tlbi_aa64_vae1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vmalle1is_write }, + .writefn =3D tlbi_aa64_vmalle1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, + .writefn =3D tlbi_aa64_vae1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, + .writefn =3D tlbi_aa64_vae1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, + .writefn =3D tlbi_aa64_vae1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_alle2is_write }, + .writefn =3D tlbi_aa64_alle2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, + .writefn =3D tlbi_aa64_vae2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, + .writefn =3D tlbi_aa64_alle1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, + .writefn =3D tlbi_aa64_vae2is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, + .writefn =3D tlbi_aa64_alle1is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, .access =3D PL2_W, .type =3D ARM_CP_NOP }, @@ -7252,15 +7261,15 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3is_write }, + .writefn =3D tlbi_aa64_alle3is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VAE3OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, + .writefn =3D tlbi_aa64_vae3is_write, .raw_writefn =3D raw_write }, { .name =3D "TLBI_VALE3OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, + .writefn =3D tlbi_aa64_vae3is_write, .raw_writefn =3D raw_write }, }; =20 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) @@ -7676,6 +7685,7 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, #ifndef CONFIG_USER_ONLY { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, @@ -8664,7 +8674,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, .access =3D PL1_RW, .resetvalue =3D 0, .accessfn =3D access_tvm_trvm, - .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read, + .raw_writefn =3D raw_write }; define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); g_free(tmp_string); @@ -8676,7 +8687,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, .access =3D PL1_RW, .resetvalue =3D 0, .accessfn =3D access_tvm_trvm, - .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read, + .raw_writefn =3D raw_write }; define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); g_free(tmp_string); @@ -8694,7 +8706,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .type =3D ARM_CP_NO_RAW, .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, .access =3D PL2_RW, .resetvalue =3D 0, - .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read, + .raw_writefn =3D raw_write }; define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); g_free(tmp_string); @@ -8706,7 +8719,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .type =3D ARM_CP_NO_RAW, .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, .access =3D PL2_RW, .resetvalue =3D 0, - .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read, + .raw_writefn =3D raw_write }; define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); g_free(tmp_string); --=20 2.37.3