From nobody Tue Feb 10 10:01:06 2026 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676280954; cv=none; d=zohomail.com; s=zohoarc; b=L1mrIQ8H9VGaMA8pdeg87kPUEt3WrwCYyYQ8irvWLYLqK5D0Pe1LG0OaRA5gMbsGZ89dMx/8Z1ItQIjyqdelI2VjaDXmyFIfDqp1kmRvFNVNT56OmddtfrvV4CIEQ9w48R8BBrJFgr/d9ul7f1JYsI9+btfbLWnUgY588CW4Ksg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676280954; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vgm/Dq3ZPQUPRkKHeR3odmAmYxRNnhKXbHnKrFtc1eg=; b=UzCLU2zO1hdKvAS0EtHpjOAHoUaAahca6CBDYZi6SlxsuJDnyWzuxs2iIE8JLZb8NFH4zD+FIJak90QHljqTUxNYNH/wgosPuWOV1f86Ls9EYBwRkR5bcy8Q5BD0a/kAIX9OYg7dS6rRaU/aJwx7uBy/kngSUFqFPx0o7eQxcrM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1676280954756501.3817613343009; Mon, 13 Feb 2023 01:35:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRVAK-0006rW-Ib; Mon, 13 Feb 2023 04:30:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRV9y-0006KE-3u for qemu-devel@nongnu.org; Mon, 13 Feb 2023 04:30:06 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRV9v-0006TH-54 for qemu-devel@nongnu.org; Mon, 13 Feb 2023 04:30:05 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2023 01:30:00 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by orsmga004.jf.intel.com with ESMTP; 13 Feb 2023 01:29:55 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676280603; x=1707816603; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wy/HB9PCBo5jKGh1Soirwp+UxznN/hgvoS723fwEbJU=; b=bnrWbUMhWf6fCzBR1fXqzXELTrLWTVLOSxQN/x4j09RvJjIO4hsc5UGq qTmNQuFDbkI8PRIcHnLEP8BHWUkJeTYbEj7XI/d2S8DleNopP4cOFm1T/ OjqVckpaR6Wqub2f04LAmhlKf+lkX4bqYxCqbSjDT1AKASjbzUnGKrcBX 41I+LAOkqS7I2pHfSYc6yTmLTA7yKMKIMHRhCdnCWk/Zb+HqCpRguE6VV Vi61Ij1eZdN7RwlkxN3wQ6/fLqdEICIfwCF0veUigd246368gW4vUzagG H1ZnC9muDQAzLrZgmsjNUa3PCjrI7EE/mv1HdZnQPr95KlRoY4m0AQz2Z A==; X-IronPort-AV: E=McAfee;i="6500,9779,10619"; a="318875826" X-IronPort-AV: E=Sophos;i="5.97,293,1669104000"; d="scan'208";a="318875826" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10619"; a="792660341" X-IronPort-AV: E=Sophos;i="5.97,293,1669104000"; d="scan'208";a="792660341" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster Cc: qemu-devel@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhuocheng Ding , Robert Hoo , Xiaoyao Li , Like Xu , Zhao Liu Subject: [PATCH RESEND 15/18] i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14] Date: Mon, 13 Feb 2023 17:36:22 +0800 Message-Id: <20230213093625.158170-16-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230213093625.158170-1-zhao1.liu@linux.intel.com> References: <20230213093625.158170-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1676280956021100006 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[4].EAX[bits 25:14] is used to represent the cache topology for intel CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[4].EAX[bits 25:14]. Additionally, since maximum_processor_id (original "num_apic_ids") is parsed based on cpu topology levels, which are verified when parsing smp, it's no need to check this value by "assert(num_apic_ids > 0)" again, so remove this assert. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 55 +++++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 19 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 364534e84b1b..96ef96860604 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -231,22 +231,50 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache) ((t) =3D=3D UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 0 /* Invalid value */) =20 +static uint32_t max_processor_ids_for_cache(CPUCacheInfo *cache, + X86CPUTopoInfo *topo_info) +{ + uint32_t num_ids =3D 0; + + switch (cache->share_level) { + case CORE: + num_ids =3D 1 << apicid_core_offset(topo_info); + break; + case DIE: + num_ids =3D 1 << apicid_die_offset(topo_info); + break; + default: + /* + * Currently there is no use case for SMT, MODULE and PACKAGE, so = use + * assert directly to facilitate debugging. + */ + g_assert_not_reached(); + } + + return num_ids - 1; +} + +static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) +{ + uint32_t num_cores =3D 1 << (apicid_pkg_offset(topo_info) - + apicid_core_offset(topo_info)); + return num_cores - 1; +} =20 /* Encode cache info for CPUID[4] */ static void encode_cache_cpuid4(CPUCacheInfo *cache, - int num_apic_ids, int num_cores, + X86CPUTopoInfo *topo_info, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 - assert(num_apic_ids > 0); *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | - ((num_cores - 1) << 26) | - ((num_apic_ids - 1) << 14); + (max_core_ids_in_package(topo_info) << 26) | + (max_processor_ids_for_cache(cache, topo_info) << 14); =20 assert(cache->line_size > 0); assert(cache->partitions > 0); @@ -5335,38 +5363,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; - int addressable_cores_offset =3D apicid_pkg_offset(&topo_info)= - - apicid_core_offset(&topo_info); - int core_offset, die_offset; =20 switch (count) { case 0: /* L1 dcache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; } --=20 2.34.1