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Tsirkin" , Yan Vugenfirer , Yuri Benditovich , Sriram Yagnaraman , Alexander Bulekov , Akihiko Odaki Subject: [PATCH v6 07/34] e1000e: Mask registers when writing Date: Thu, 23 Feb 2023 19:19:51 +0900 Message-Id: <20230223102018.141748-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223102018.141748-1-akihiko.odaki@daynix.com> References: <20230223102018.141748-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::632; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1677147780270100006 Content-Type: text/plain; charset="utf-8" When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 76 +++++++++++++++++++------------------------- 1 file changed, 32 insertions(+), 44 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 1cafc38f50..e6fc85ea51 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -2447,7 +2447,11 @@ e1000e_set_fcrtl(E1000ECore *core, int index, uint32= _t val) core->mac[index] =3D val & (BIT(num) - 1); \ } =20 +E1000E_LOW_BITS_SET_FUNC(4) +E1000E_LOW_BITS_SET_FUNC(6) +E1000E_LOW_BITS_SET_FUNC(11) E1000E_LOW_BITS_SET_FUNC(12) +E1000E_LOW_BITS_SET_FUNC(13) E1000E_LOW_BITS_SET_FUNC(16) =20 static void @@ -2619,22 +2623,6 @@ e1000e_mac_ims_read(E1000ECore *core, int index) return core->mac[IMS]; } =20 -#define E1000E_LOW_BITS_READ_FUNC(num) \ - static uint32_t \ - e1000e_mac_low##num##_read(E1000ECore *core, int index) \ - { \ - return core->mac[index] & (BIT(num) - 1); \ - } \ - -#define E1000E_LOW_BITS_READ(num) \ - e1000e_mac_low##num##_read - -E1000E_LOW_BITS_READ_FUNC(4); -E1000E_LOW_BITS_READ_FUNC(6); -E1000E_LOW_BITS_READ_FUNC(11); -E1000E_LOW_BITS_READ_FUNC(13); -E1000E_LOW_BITS_READ_FUNC(16); - static uint32_t e1000e_mac_swsm_read(E1000ECore *core, int index) { @@ -2928,7 +2916,19 @@ static const readops e1000e_macreg_readops[] =3D { e1000e_getreg(LATECOL), e1000e_getreg(SEQEC), e1000e_getreg(XONTXC), + e1000e_getreg(AIT), + e1000e_getreg(TDFH), + e1000e_getreg(TDFT), + e1000e_getreg(TDFHS), + e1000e_getreg(TDFTS), + e1000e_getreg(TDFPC), e1000e_getreg(WUS), + e1000e_getreg(PBS), + e1000e_getreg(RDFH), + e1000e_getreg(RDFT), + e1000e_getreg(RDFHS), + e1000e_getreg(RDFTS), + e1000e_getreg(RDFPC), e1000e_getreg(GORCL), e1000e_getreg(MGTPRC), e1000e_getreg(EERD), @@ -3064,16 +3064,9 @@ static const readops e1000e_macreg_readops[] =3D { [MPTC] =3D e1000e_mac_read_clr4, [IAC] =3D e1000e_mac_read_clr4, [ICR] =3D e1000e_mac_icr_read, - [RDFH] =3D E1000E_LOW_BITS_READ(13), - [RDFHS] =3D E1000E_LOW_BITS_READ(13), - [RDFPC] =3D E1000E_LOW_BITS_READ(13), - [TDFH] =3D E1000E_LOW_BITS_READ(13), - [TDFHS] =3D E1000E_LOW_BITS_READ(13), [STATUS] =3D e1000e_get_status, [TARC0] =3D e1000e_get_tarc, - [PBS] =3D E1000E_LOW_BITS_READ(6), [ICS] =3D e1000e_mac_ics_read, - [AIT] =3D E1000E_LOW_BITS_READ(16), [TORH] =3D e1000e_mac_read_clr8, [GORCH] =3D e1000e_mac_read_clr8, [PRC127] =3D e1000e_mac_read_clr4, @@ -3089,11 +3082,6 @@ static const readops e1000e_macreg_readops[] =3D { [BPTC] =3D e1000e_mac_read_clr4, [TSCTC] =3D e1000e_mac_read_clr4, [ITR] =3D e1000e_mac_itr_read, - [RDFT] =3D E1000E_LOW_BITS_READ(13), - [RDFTS] =3D E1000E_LOW_BITS_READ(13), - [TDFPC] =3D E1000E_LOW_BITS_READ(13), - [TDFT] =3D E1000E_LOW_BITS_READ(13), - [TDFTS] =3D E1000E_LOW_BITS_READ(13), [CTRL] =3D e1000e_get_ctrl, [TARC1] =3D e1000e_get_tarc, [SWSM] =3D e1000e_mac_swsm_read, @@ -3106,10 +3094,10 @@ static const readops e1000e_macreg_readops[] =3D { [WUPM ... WUPM + 31] =3D e1000e_mac_readreg, [MTA ... MTA + 127] =3D e1000e_mac_readreg, [VFTA ... VFTA + 127] =3D e1000e_mac_readreg, - [FFMT ... FFMT + 254] =3D E1000E_LOW_BITS_READ(4), + [FFMT ... FFMT + 254] =3D e1000e_mac_readreg, [FFVT ... FFVT + 254] =3D e1000e_mac_readreg, [MDEF ... MDEF + 7] =3D e1000e_mac_readreg, - [FFLT ... FFLT + 10] =3D E1000E_LOW_BITS_READ(11), + [FFLT ... FFLT + 10] =3D e1000e_mac_readreg, [FTFT ... FTFT + 254] =3D e1000e_mac_readreg, [PBM ... PBM + 10239] =3D e1000e_mac_readreg, [RETA ... RETA + 31] =3D e1000e_mac_readreg, @@ -3132,19 +3120,8 @@ static const writeops e1000e_macreg_writeops[] =3D { e1000e_putreg(LEDCTL), e1000e_putreg(FCAL), e1000e_putreg(FCRUC), - e1000e_putreg(AIT), - e1000e_putreg(TDFH), - e1000e_putreg(TDFT), - e1000e_putreg(TDFHS), - e1000e_putreg(TDFTS), - e1000e_putreg(TDFPC), e1000e_putreg(WUC), e1000e_putreg(WUS), - e1000e_putreg(RDFH), - e1000e_putreg(RDFT), - e1000e_putreg(RDFHS), - e1000e_putreg(RDFTS), - e1000e_putreg(RDFPC), e1000e_putreg(IPAV), e1000e_putreg(TDBAH1), e1000e_putreg(TIMINCA), @@ -3155,7 +3132,6 @@ static const writeops e1000e_macreg_writeops[] =3D { e1000e_putreg(TARC1), e1000e_putreg(FLSWDATA), e1000e_putreg(POEMB), - e1000e_putreg(PBS), e1000e_putreg(MFUTP01), e1000e_putreg(MFUTP23), e1000e_putreg(MANC), @@ -3220,6 +3196,18 @@ static const writeops e1000e_macreg_writeops[] =3D { [TADV] =3D e1000e_set_16bit, [ITR] =3D e1000e_set_itr, [EERD] =3D e1000e_set_eerd, + [AIT] =3D e1000e_set_16bit, + [TDFH] =3D e1000e_set_13bit, + [TDFT] =3D e1000e_set_13bit, + [TDFHS] =3D e1000e_set_13bit, + [TDFTS] =3D e1000e_set_13bit, + [TDFPC] =3D e1000e_set_13bit, + [RDFH] =3D e1000e_set_13bit, + [RDFHS] =3D e1000e_set_13bit, + [RDFT] =3D e1000e_set_13bit, + [RDFTS] =3D e1000e_set_13bit, + [RDFPC] =3D e1000e_set_13bit, + [PBS] =3D e1000e_set_6bit, [GCR] =3D e1000e_set_gcr, [PSRCTL] =3D e1000e_set_psrctl, [RXCSUM] =3D e1000e_set_rxcsum, @@ -3259,11 +3247,11 @@ static const writeops e1000e_macreg_writeops[] =3D { [WUPM ... WUPM + 31] =3D e1000e_mac_writereg, [MTA ... MTA + 127] =3D e1000e_mac_writereg, [VFTA ... VFTA + 127] =3D e1000e_mac_writereg, - [FFMT ... FFMT + 254] =3D e1000e_mac_writereg, + [FFMT ... FFMT + 254] =3D e1000e_set_4bit, [FFVT ... FFVT + 254] =3D e1000e_mac_writereg, [PBM ... PBM + 10239] =3D e1000e_mac_writereg, [MDEF ... MDEF + 7] =3D e1000e_mac_writereg, - [FFLT ... FFLT + 10] =3D e1000e_mac_writereg, + [FFLT ... FFLT + 10] =3D e1000e_set_11bit, [FTFT ... FTFT + 254] =3D e1000e_mac_writereg, [RETA ... RETA + 31] =3D e1000e_mac_writereg, [RSSRK ... RSSRK + 31] =3D e1000e_mac_writereg, --=20 2.39.1