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[217.237.116.51]) by smtp.gmail.com with ESMTPSA id jj1-20020a170907984100b008d606b1bbb1sm5200917ejc.9.2023.02.23.12.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:23:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=URC4QULn1s6Vm1JS2+nnjxOu3AuTbC5LZ+8A63obzbk=; b=Ud2cFpNPmcI0ZMmV13Y2JgvJBl5uo+ugE6ro05qlmV1OtCAilKNBEoQSYlJGJ3BZMl uxBmCEnppdaFo1RfeFbAG8XmC05Muy1dXYYugVXuN8WXKHj07g8qGJrsnSPzBXzVgLEn 9rLtliqnnFBKo60jn4Ggfp55NmKVXhXasonokNoctq5iLwuKFGoQDngDLIGQZM/F/LPo JPZkovIDprU+L6S3BMWrx57/UlPQHyijaZnp43Kc2dI+5naaVZsngZrhDV6oGgqbHiEk I8dCCf9kL7RSOA3krUFY5ScpedZn2T+oKNyCfslOgmm6XBNLAJHYoB0etGXcKHHEixlq LBEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=URC4QULn1s6Vm1JS2+nnjxOu3AuTbC5LZ+8A63obzbk=; b=J6C6fYhcJ5dngFULYJkT5rT7Pi1mKTNJGDa7s0rwLUW5hOWENLVLGFiepFZtF4GBt/ gK2OOJvZAjBvsup7Hj7es6TtSU9ANubS9CQVHv8T7U/Qkjks/v7HSOyKGvieoZfEm0dW o8oyNfsdPzDxbXZkDrZlrNnjuc9AlfI7Sm/1dnbFb+c2kr7zMtEFne0ZN0mN+dcSkwQb BX8C36DCbgpth2akhTquXq8O/HfHk4YidBtGmcJDTDQXKbuKziVIzS/6rrT/S1q+yWrP B6hmk07ygrGwzI2Ajhrk4svomHjV0Uh6Mos51QkX/wTrGotXksDT86/onX0pfM868LGx U9jw== X-Gm-Message-State: AO0yUKV4Y14k59NtcmpJ8dZ81rLrSWADER81U/Cc19uIzbAAo2vwoF3L fOG4P1ZF8MC4JddLEz8O552swSBAlpY= X-Google-Smtp-Source: AK7set+V6EmoQRLSALSepupWkjPI/pJ9jCrRb64D3/rEeC2rtzhOBeaKgXbrAEl/T1XFZbLvJ2kvpQ== X-Received: by 2002:a17:907:7b97:b0:8db:4c66:59cf with SMTP id ne23-20020a1709077b9700b008db4c6659cfmr16788511ejc.42.1677183794547; Thu, 23 Feb 2023 12:23:14 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , qemu-ppc@nongnu.org, Gerd Hoffmann , Jiaxun Yang , BALATON Zoltan , Bernhard Beschow Subject: [PATCH 2/5] hw/isa/vt82c686: Implement PCI IRQ routing Date: Thu, 23 Feb 2023 21:20:50 +0100 Message-Id: <20230223202053.117050-3-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230223202053.117050-1-shentey@gmail.com> References: <20230223202053.117050-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677183874311100007 Content-Type: text/plain; charset="utf-8" The real VIA south bridges implement a PCI IRQ router which is configured by the BIOS or the OS. In order to respect these configurations, QEMU needs to implement it as well. Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 3f9bd0c04d..f24e387d63 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -604,6 +604,48 @@ static void via_isa_request_i8259_irq(void *opaque, in= t irq, int level) qemu_set_irq(s->cpu_intr, level); } =20 +static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num) +{ + switch (irq_num) { + case 0: + return s->dev.config[0x55] >> 4; + + case 1: + return s->dev.config[0x56] & 0xf; + + case 2: + return s->dev.config[0x56] >> 4; + + case 3: + return s->dev.config[0x57] >> 4; + } + + return 0; +} + +static void via_isa_set_pci_irq(void *opaque, int irq_num, int level) +{ + ViaISAState *s =3D opaque; + PCIBus *bus =3D pci_get_bus(&s->dev); + int pic_irq; + + /* now we change the pic irq level according to the via irq mappings */ + /* XXX: optimize */ + pic_irq =3D via_isa_get_pci_irq(s, irq_num); + if (pic_irq < ISA_NUM_IRQS) { + int i, pic_level; + + /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ + pic_level =3D 0; + for (i =3D 0; i < PCI_NUM_PINS; i++) { + if (pic_irq =3D=3D via_isa_get_pci_irq(s, i)) { + pic_level |=3D pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(s->isa_irqs[pic_irq], pic_level); + } +} + static void via_isa_realize(PCIDevice *d, Error **errp) { ViaISAState *s =3D VIA_ISA(d); @@ -676,6 +718,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp) if (!qdev_realize(DEVICE(&s->mc97), BUS(pci_bus), errp)) { return; } + + pci_bus_irqs(pci_bus, via_isa_set_pci_irq, s, PCI_NUM_PINS); } =20 /* TYPE_VT82C686B_ISA */ --=20 2.39.2