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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:44:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4VpqcMOXVlrjqv2u2QyFnc/vNdrKfYNKBg4oxbaB+0Q=; b=AeF+e/q1u6JXtK32KfD1tGeD3rTzWOTE9LnYz4oGELCJM5mBGEI71BjB61EQKWLjTu GhaWy0x0Bugy1WnUIv7T7ixAT/3e4biWSymK2/bkfvPn2SbIa0rFcYKOtFv9JJTHUr6j 4MkdEkLBrZwLlEnxyV3aWx0WvofrodjuGgb8JnP8snXqf5XM9I5r2gynqw4NIOzOzj56 T/KZ5oeLtK+0r6hSe9uuZfBGKPsYOp5GQ5W1RXKHSP1aJMOkJgBxcjm71pvgClGFihXp opjHUO/9Hi5x5lCDOTqXJuOCGHw0ygw3uBVr7b5/vlnpLwxhoc+eXzsugl2sMwDsn/Sx Efkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4VpqcMOXVlrjqv2u2QyFnc/vNdrKfYNKBg4oxbaB+0Q=; b=wQ0tbFYeZ7BWoWv6I/8ZxbBTZTsVClw165P0X0LPvB1ALY4IbBfPvFoM1Q5kA767Ec KWsqNaBmzDtKk6Pqe9qI7tt+RO1zA+fImbTX26lBBVq3iVMq2yWRUsxl0IEwTvkr2UuF 7qLCgv8+E+U5CjyXGq3fkO8L33+CYlAzrMP4gO/jBUEVpnJKFEC7X58XMRnPJkESl3pp TphBPkvVWAskwrJJYZlvHQPA2VkA/3KQpxFM1wzJ5JIiqtnptv6IP7iRkVFEkzVBKFQt GaOiMXno/vDJiaL3sw1TRbdrvZ2wOz6lGHJFq0u4yT7zXITynqQjkJisu3sD8EMCHoiV DisQ== X-Gm-Message-State: AO0yUKX882xrpSOVtkeE2ZmPH0qPxAfibivzxLtvwIcBjuggvThobHKd HrdWuac84hbtvLD+XVEylr53T5QZ6vBs4NIKgPOdrA== X-Google-Smtp-Source: AK7set/t/aBuZB9vcZH5dhDvSjapnVQaEZaY6pIrVjQI1paSN2L+LTZUToiXiD7ACBUEe8GZPp4c7w== X-Received: by 2002:a05:6a20:6530:b0:cc:59a7:65ae with SMTP id n48-20020a056a20653000b000cc59a765aemr625929pzg.24.1677185046622; Thu, 23 Feb 2023 12:44:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Idan Horowitz Subject: [PATCH 12/13] target/arm: Do memory type alignment check when translation disabled Date: Thu, 23 Feb 2023 10:43:41 -1000 Message-Id: <20230223204342.1093632-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677185089085100013 Content-Type: text/plain; charset="utf-8" If translation is disabled, the default memory type is Device, which requires alignment checking. This is more optimially done early via the MemOp given to the TCG memory operation. Reported-by: Idan Horowitz Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 07d4100365..b1b664e0ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11867,6 +11867,37 @@ static inline bool fgt_svc(CPUARMState *env, int e= l) FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); } =20 +/* + * Return true if memory alignment should be enforced. + */ +static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t = sctlr) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + /* Check the alignment enable bit. */ + if (sctlr & SCTLR_A) { + return true; + } + + /* + * If translation is disabled, then the default memory type is + * Device(-nGnRnE) instead of Normal, which requires that alignment + * be enforced. Since this affects all ram, it is most efficient + * to handle this during translation. + */ + if (sctlr & SCTLR_M) { + /* Translation enabled: memory type in PTE via MAIR_ELx. */ + return false; + } + if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { + /* Stage 2 translation enabled: memory type in PTE. */ + return false; + } + return true; +#endif +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -11936,8 +11967,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState= *env, int fp_el, { CPUARMTBFlags flags =3D {}; int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); =20 - if (arm_sctlr(env, el) & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } =20 @@ -12037,7 +12069,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, =20 sctlr =3D regime_sctlr(env, stage1); =20 - if (sctlr & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } =20 --=20 2.34.1