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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N9ofc0CdkfvI0sj5X3EW+klo2rQGa2mDhM3KZBvNWdU=; b=XREkinomMTHs6e/RJS+hFiMGgHgCOY6P8r/0KdxfluDzmmjrIn2HavVQWuPvA6dTCR JLMbr28+LDdZXfnZQHo2TNPcs7JEeHxU1loMf31d9OzJ2TDtRSPVppWx9j85VXViEAQd s9jbsTAY3n+wyYlodeYYiIqy/piwWCZP508evi4RGOQeQeO5R4nABiDL3iuYO+L+LRoX 1mM5mXIjtZ6FwDgdplFyXCxC7A76rFQQc/gwhLvcNwh0zWux1bkav7sMBDHRC3EHuijB 2qGWi4BYQiYITKwxMsj2Rd0Pd6i2e6uh3/vfZSk9Qk2EdgqfpRqwzdF9QbCdW9hvh3T/ 9gEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N9ofc0CdkfvI0sj5X3EW+klo2rQGa2mDhM3KZBvNWdU=; b=r8lJ1U10hoqFijFe7AR6j8dxcrCXjtQbeIH23Qh7EBDuBhndlAxnleWMJPhqMxD9ov FARJxI02BHjvUTsrD8dj3hmXT7ugJNNQcGPyKcs+ksTzng1KyWxddrgRE4x9WO5Bfife /wFGBKNG4Mv5+OUfS8viZqIPG6ep+FCijbOvpm1tqVy3a49zuMxIC/xKbulZVy9xInm0 UTt9huJqrZR+v188C+Ny3Ch01qhdcumbfOw0diFUzeFPr0rrn2YdcTjSSwiScWRe+nTi 6M4N8XCbd9a8OwIQ+lpt1jc6iQd77oO0KCcZXzYKbqP1a71omtCsSQ0A23tNXz+GpaQd NpeA== X-Gm-Message-State: AO0yUKUnznWyqnTZUpX4W17u953q157a05a0STWxmajEcSRDOSJKYNgC bS0cQUbOF/oBhIeiULw9vUlOG10T56UrEcv2Dq8= X-Google-Smtp-Source: AK7set8vy3cvHeo/xltwXsCVEJwMwvX0NoDiQGmoZ6lWiGId8C+Ona66epA4MdqoRD2VJ8gyc0DobA== X-Received: by 2002:a05:6a20:12d0:b0:cb:9afd:8ad0 with SMTP id v16-20020a056a2012d000b000cb9afd8ad0mr11952950pzg.19.1677185029392; Thu, 23 Feb 2023 12:43:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 01/13] target/sparc: Use tlb_set_page_full Date: Thu, 23 Feb 2023 10:43:30 -1000 Message-Id: <20230223204342.1093632-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677185117594100006 Content-Type: text/plain; charset="utf-8" Pass CPUTLBEntryFull to get_physical_address instead of a collection of pointers. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Mark Cave-Ayland Cc: Artyom Tarasenko --- target/sparc/mmu_helper.c | 121 +++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 67 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 158ec2ae8f..a98dd0abd4 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -64,10 +64,9 @@ static const int perm_table[2][8] =3D { } }; =20 -static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, MemTxAttrs *= attrs, - target_ulong address, int rw, int mmu_idx, - target_ulong *page_size) +static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full, + int *access_index, target_ulong address, + int rw, int mmu_idx) { int access_perms =3D 0; hwaddr pde_ptr; @@ -80,20 +79,20 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, is_user =3D mmu_idx =3D=3D MMU_USER_IDX; =20 if (mmu_idx =3D=3D MMU_PHYS_IDX) { - *page_size =3D TARGET_PAGE_SIZE; + full->lg_page_size =3D TARGET_PAGE_BITS; /* Boot mode: instruction fetches are taken from PROM */ if (rw =3D=3D 2 && (env->mmuregs[0] & env->def.mmu_bm)) { - *physical =3D env->prom_addr | (address & 0x7ffffULL); - *prot =3D PAGE_READ | PAGE_EXEC; + full->phys_addr =3D env->prom_addr | (address & 0x7ffffULL); + full->prot =3D PAGE_READ | PAGE_EXEC; return 0; } - *physical =3D address; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + full->phys_addr =3D address; + full->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return 0; } =20 *access_index =3D ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1); - *physical =3D 0xffffffffffff0000ULL; + full->phys_addr =3D 0xffffffffffff0000ULL; =20 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */ /* Context base + context number */ @@ -157,16 +156,17 @@ static int get_physical_address(CPUSPARCState *env, h= waddr *physical, case 2: /* L3 PTE */ page_offset =3D 0; } - *page_size =3D TARGET_PAGE_SIZE; + full->lg_page_size =3D TARGET_PAGE_BITS; break; case 2: /* L2 PTE */ page_offset =3D address & 0x3f000; - *page_size =3D 0x40000; + full->lg_page_size =3D 18; } break; case 2: /* L1 PTE */ page_offset =3D address & 0xfff000; - *page_size =3D 0x1000000; + full->lg_page_size =3D 24; + break; } } =20 @@ -188,16 +188,16 @@ static int get_physical_address(CPUSPARCState *env, h= waddr *physical, } =20 /* the page can be put in the TLB */ - *prot =3D perm_table[is_user][access_perms]; + full->prot =3D perm_table[is_user][access_perms]; if (!(pde & PG_MODIFIED_MASK)) { /* only set write access if already dirty... otherwise wait for dirty access */ - *prot &=3D ~PAGE_WRITE; + full->prot &=3D ~PAGE_WRITE; } =20 /* Even if large ptes, we map only one 4KB page in the cache to avoid filling it too fast */ - *physical =3D ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset; + full->phys_addr =3D ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset; return error_code; } =20 @@ -208,11 +208,9 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; - hwaddr paddr; + CPUTLBEntryFull full =3D {}; target_ulong vaddr; - target_ulong page_size; - int error_code =3D 0, prot, access_index; - MemTxAttrs attrs =3D {}; + int error_code =3D 0, access_index; =20 /* * TODO: If we ever need tlb_vaddr_to_host for this target, @@ -223,16 +221,15 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, assert(!probe); =20 address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, - address, access_type, - mmu_idx, &page_size); + error_code =3D get_physical_address(env, &full, &access_index, + address, access_type, mmu_idx); vaddr =3D address; if (likely(error_code =3D=3D 0)) { qemu_log_mask(CPU_LOG_MMU, "Translate at %" VADDR_PRIx " -> " HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n", - address, paddr, vaddr); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + address, full.phys_addr, vaddr); + tlb_set_page_full(cs, mmu_idx, vaddr, &full); return true; } =20 @@ -247,8 +244,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, permissions. If no mapping is available, redirect accesses to neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ - prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); + full.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + tlb_set_page_full(cs, mmu_idx, vaddr, &full); return true; } else { if (access_type =3D=3D MMU_INST_FETCH) { @@ -545,8 +542,7 @@ static uint64_t build_sfsr(CPUSPARCState *env, int mmu_= idx, int rw) return sfsr; } =20 -static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, - int *prot, MemTxAttrs *attrs, +static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *= full, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); @@ -579,11 +575,12 @@ static int get_physical_address_data(CPUSPARCState *e= nv, hwaddr *physical, =20 for (i =3D 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ - if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { + if (ultrasparc_tag_match(&env->dtlb[i], address, context, + &full->phys_addr)) { int do_fault =3D 0; =20 if (TTE_IS_IE(env->dtlb[i].tte)) { - attrs->byte_swap =3D true; + full->attrs.byte_swap =3D true; } =20 /* access ok? */ @@ -616,9 +613,9 @@ static int get_physical_address_data(CPUSPARCState *env= , hwaddr *physical, } =20 if (!do_fault) { - *prot =3D PAGE_READ; + full->prot =3D PAGE_READ; if (TTE_IS_W_OK(env->dtlb[i].tte)) { - *prot |=3D PAGE_WRITE; + full->prot |=3D PAGE_WRITE; } =20 TTE_SET_USED(env->dtlb[i].tte); @@ -645,8 +642,7 @@ static int get_physical_address_data(CPUSPARCState *env= , hwaddr *physical, return 1; } =20 -static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, - int *prot, MemTxAttrs *attrs, +static int get_physical_address_code(CPUSPARCState *env, CPUTLBEntryFull *= full, target_ulong address, int mmu_idx) { CPUState *cs =3D env_cpu(env); @@ -681,7 +677,7 @@ static int get_physical_address_code(CPUSPARCState *env= , hwaddr *physical, for (i =3D 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->itlb[i], - address, context, physical)) { + address, context, &full->phys_addr)) { /* access ok? */ if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) { /* Fault status register */ @@ -708,7 +704,7 @@ static int get_physical_address_code(CPUSPARCState *env= , hwaddr *physical, =20 return 1; } - *prot =3D PAGE_EXEC; + full->prot =3D PAGE_EXEC; TTE_SET_USED(env->itlb[i].tte); return 0; } @@ -722,14 +718,13 @@ static int get_physical_address_code(CPUSPARCState *e= nv, hwaddr *physical, return 1; } =20 -static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, MemTxAttrs *= attrs, - target_ulong address, int rw, int mmu_idx, - target_ulong *page_size) +static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full, + int *access_index, target_ulong address, + int rw, int mmu_idx) { /* ??? We treat everything as a small page, then explicitly flush everything when an entry is evicted. */ - *page_size =3D TARGET_PAGE_SIZE; + full->lg_page_size =3D TARGET_PAGE_BITS; =20 /* safety net to catch wrong softmmu index use from dynamic code */ if (env->tl > 0 && mmu_idx !=3D MMU_NUCLEUS_IDX) { @@ -747,17 +742,15 @@ static int get_physical_address(CPUSPARCState *env, h= waddr *physical, } =20 if (mmu_idx =3D=3D MMU_PHYS_IDX) { - *physical =3D ultrasparc_truncate_physical(address); - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + full->phys_addr =3D ultrasparc_truncate_physical(address); + full->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return 0; } =20 if (rw =3D=3D 2) { - return get_physical_address_code(env, physical, prot, attrs, addre= ss, - mmu_idx); + return get_physical_address_code(env, full, address, mmu_idx); } else { - return get_physical_address_data(env, physical, prot, attrs, addre= ss, - rw, mmu_idx); + return get_physical_address_data(env, full, address, rw, mmu_idx); } } =20 @@ -768,25 +761,17 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; - target_ulong vaddr; - hwaddr paddr; - target_ulong page_size; - MemTxAttrs attrs =3D {}; - int error_code =3D 0, prot, access_index; + CPUTLBEntryFull full =3D {}; + int error_code =3D 0, access_index; =20 address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, - address, access_type, - mmu_idx, &page_size); + error_code =3D get_physical_address(env, &full, &access_index, + address, access_type, mmu_idx); if (likely(error_code =3D=3D 0)) { - vaddr =3D address; - - trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, + trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->= tl, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - - tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, - page_size); + tlb_set_page_full(cs, mmu_idx, address, &full); return true; } if (probe) { @@ -888,12 +873,14 @@ void dump_mmu(CPUSPARCState *env) static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys, target_ulong addr, int rw, int mmu_idx) { - target_ulong page_size; - int prot, access_index; - MemTxAttrs attrs =3D {}; + CPUTLBEntryFull full =3D {}; + int access_index, ret; =20 - return get_physical_address(env, phys, &prot, &access_index, &attrs, a= ddr, - rw, mmu_idx, &page_size); + ret =3D get_physical_address(env, &full, &access_index, addr, rw, mmu_= idx); + if (ret =3D=3D 0) { + *phys =3D full.phys_addr; + } + return ret; } =20 #if defined(TARGET_SPARC64) --=20 2.34.1