From nobody Wed May 14 10:46:45 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1677195939; cv=none; d=zohomail.com; s=zohoarc; b=QDvlh1lQeLWCtL5/6WAtBT5Iesw5tTI36fOp0o1zU8vnDdZwkeI3UCJ/B18IrSbkfecflbM9ZkKGgS1FuJxnfnhNrKvU9olnusnAHkMOeHzSgC1Tn9V4b4tkJQMPkkRdEMxgsfuPD88g3LI2GB2elthki9EjlQhyQVRGqxaWVjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677195939; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=niOll0s/PDcnOMdRIUOVBVVgsiBEkn8iEUg3l/2iVTQ=; b=K2Yxhn0dbloo1/I/PPvxa/k7LMfxK3lsKEVmBolPf8cmLB0TJquLe8yUfMhBbLucngRQOAootyrX+OkFiDNNMxNlIc1UUmrwzjtdZRYrRBsTrcgUJl4xS1ZfdNlGts1a/VGB0auxAaHE/kOWDDnBWOT2QHbxCw+fZlg/sRfSJ94= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677195939739415.84836839969296; Thu, 23 Feb 2023 15:45:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pVLGa-0002nT-J6; Thu, 23 Feb 2023 18:44:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pVLGS-0002kC-3q for qemu-devel@nongnu.org; Thu, 23 Feb 2023 18:44:41 -0500 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pVLGQ-00017p-5Y for qemu-devel@nongnu.org; Thu, 23 Feb 2023 18:44:39 -0500 Received: by mail-oi1-x230.google.com with SMTP id bg11so14380583oib.5 for ; Thu, 23 Feb 2023 15:44:37 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([189.110.112.117]) by smtp.gmail.com with ESMTPSA id v6-20020acaac06000000b0037facb2c5fasm2415037oie.1.2023.02.23.15.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 15:44:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=niOll0s/PDcnOMdRIUOVBVVgsiBEkn8iEUg3l/2iVTQ=; b=hHmeCJSocilNvFU/5MelF/wzn7O7Ubjo4kJhAyw5Xy4o3Li2GmyDsC5igGPONTYcv0 eEo/NNp6omt8IOQs1L8NRTquwV5aL+TAJnFfYTxZ5xSj4UKmkXirtfHAriGHPR6rQvEG B9xzJ2SbqWEA7syI8XJU9BcjIgP1LAOnm7m6h83NzqHjoA5DOx6JFsm4vYp9tNKi1FKk qrptQ9CbsODhxq3yEnbo2szlhaaRIJSqKEnnTNA/YXIxKW5iyLPaHy/s15eUc5mGZ40P Twmx5sXrOrAeSCbtZ3I1X2oC2zNqzr0JqanBBzmyo24OoWtyjq+C3dBDebAbMnRyatLq c2Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=niOll0s/PDcnOMdRIUOVBVVgsiBEkn8iEUg3l/2iVTQ=; b=PutIoR+9czVmvSFFHnzLBLkFHfkHtwHMowgGbxRzdOeyoZVjd0sqeAoo5ls4A48fF/ UoAZ85533jGKY1KuF2FbiSOKZ+8GLPZdZWDdetvqAtA04PeQRMPIkhg7G9o84F7Vs94j fiFKwYF5zd2hIOyt5MMRbNtfwcTrXfPRrzB2H3sIyqanBvxELIu5RBaiWjVEeHhnfev5 KHlSpp9VY9haU0IrzSksPB7ZMxyM8+I2Q1Z7Sx8fAkAaWVeZy8v9t3mVwnk0tYn4XR8N VLeE6+QmX7dCVUr4Ct749uAyH4SSuhqhD55BnuoDdynkslBIAg1tydK2veaR7hKX7mML dN4w== X-Gm-Message-State: AO0yUKU9SkXjiNKT4U9nQ1/+Hovduw8QB2Gy3sqA+7ZX0aOozIBZhWC3 jF0dxPb0cepIR4dg2chB1ZmbfjfDsJ++xBad X-Google-Smtp-Source: AK7set/WdUygpuMPTB7z2o5ctXaknf6NLEB28UZ7C6eSclTAUD70Tu0FF2+yuf+elkR0Zn0Zk5FT4Q== X-Received: by 2002:a05:6808:8ea:b0:37e:aa97:4660 with SMTP id d10-20020a05680808ea00b0037eaa974660mr5878983oic.16.1677195877080; Thu, 23 Feb 2023 15:44:37 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH v7 1/4] tcg: add 'size' param to probe_access_flags() Date: Thu, 23 Feb 2023 20:44:24 -0300 Message-Id: <20230223234427.521114-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230223234427.521114-1-dbarboza@ventanamicro.com> References: <20230223234427.521114-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1677195942199100006 Content-Type: text/plain; charset="utf-8" probe_access_flags() as it is today uses probe_access_full(), which in turn uses probe_access_internal() with size =3D 0. probe_access_internal() then uses the size to call the tlb_fill() callback for the given CPU. This size param ('fault_size' as probe_access_internal() calls it) is ignored by most existing .tlb_fill callback implementations, e.g. arm_cpu_tlb_fill(), ppc_cpu_tlb_fill(), x86_cpu_tlb_fill() and mips_cpu_tlb_fill() to name a few. But RISC-V riscv_cpu_tlb_fill() actually uses it. The 'size' parameter is used to check for PMP (Physical Memory Protection) access. This is necessary because PMP does not make any guarantees about all the bytes of the same page having the same permissions, i.e. the same page can have different PMP properties, so we're forced to make sub-page range checks. To allow RISC-V emulation to do a probe_acess_flags() that covers PMP, we need to either add a 'size' param to the existing probe_acess_flags() or create a new interface (e.g. probe_access_range_flags). There are quite a few probe_* APIs already, so let's add a 'size' param to probe_access_flags() and re-use this API. This is done by open coding what probe_access_full() does inside probe_acess_flags() and passing the 'size' param to probe_acess_internal(). Existing probe_access_flags() callers use size =3D 0 to not change their current API usage. 'size' is asserted to enforce single page access like probe_access() already does. No behavioral changes intended. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson --- accel/stubs/tcg-stub.c | 2 +- accel/tcg/cputlb.c | 17 ++++++++++++++--- accel/tcg/user-exec.c | 5 +++-- include/exec/exec-all.h | 3 ++- semihosting/uaccess.c | 2 +- target/arm/ptw.c | 2 +- target/arm/sve_helper.c | 2 +- target/s390x/tcg/mem_helper.c | 6 +++--- 8 files changed, 26 insertions(+), 13 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index c1b05767c0..96af23dc5d 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -25,7 +25,7 @@ void tcg_flush_jmp_cache(CPUState *cpu) { } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, +int probe_access_flags(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) { diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4812d83961..fc27e34457 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1606,14 +1606,25 @@ int probe_access_full(CPUArchState *env, target_ulo= ng addr, return flags; } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, +int probe_access_flags(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) { CPUTLBEntryFull *full; + int flags; + + g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); + + flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, + nonfault, phost, &full, retaddr); =20 - return probe_access_full(env, addr, access_type, mmu_idx, - nonfault, phost, &full, retaddr); + /* Handle clean RAM pages. */ + if (unlikely(flags & TLB_NOTDIRTY)) { + notdirty_write(env_cpu(env), addr, 1, full, retaddr); + flags &=3D ~TLB_NOTDIRTY; + } + + return flags; } =20 void *probe_access(CPUArchState *env, target_ulong addr, int size, diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index ae67d84638..7b37fd229e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -761,13 +761,14 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra); } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, +int probe_access_flags(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { int flags; =20 - flags =3D probe_access_internal(env, addr, 0, access_type, nonfault, r= a); + g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); + flags =3D probe_access_internal(env, addr, size, access_type, nonfault= , ra); *phost =3D flags ? NULL : g2h(env_cpu(env), addr); return flags; } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 54585a9954..b0d4916573 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -446,6 +446,7 @@ static inline void *probe_read(CPUArchState *env, targe= t_ulong addr, int size, * probe_access_flags: * @env: CPUArchState * @addr: guest virtual address to look up + * @size: size of the access * @access_type: read, write or execute permission * @mmu_idx: MMU index to use for lookup * @nonfault: suppress the fault @@ -460,7 +461,7 @@ static inline void *probe_read(CPUArchState *env, targe= t_ulong addr, int size, * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. */ -int probe_access_flags(CPUArchState *env, target_ulong addr, +int probe_access_flags(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); =20 diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index 8018828069..7505eb6d1b 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -37,7 +37,7 @@ ssize_t softmmu_strlen_user(CPUArchState *env, target_ulo= ng addr) /* Find the number of bytes remaining in the page. */ left_in_page =3D TARGET_PAGE_SIZE - (addr & ~TARGET_PAGE_MASK); =20 - flags =3D probe_access_flags(env, addr, MMU_DATA_LOAD, + flags =3D probe_access_flags(env, addr, 0, MMU_DATA_LOAD, mmu_idx, true, &h, 0); if (flags & TLB_INVALID_MASK) { return -1; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2b125fff44..1ecefb2027 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -407,7 +407,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t= old_val, void *discard; =20 env->tlb_fi =3D fi; - flags =3D probe_access_flags(env, ptw->out_virt, MMU_DATA_STORE, + flags =3D probe_access_flags(env, ptw->out_virt, 0, MMU_DATA_STORE, arm_to_core_mmu_idx(ptw->in_ptw_idx), true, &discard, 0); env->tlb_fi =3D NULL; diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 521fc9b969..51909c44ac 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5352,7 +5352,7 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, = CPUARMState *env, addr =3D useronly_clean_ptr(addr); =20 #ifdef CONFIG_USER_ONLY - flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nofault, + flags =3D probe_access_flags(env, addr, 0, access_type, mmu_idx, nofau= lt, &info->host, retaddr); #else CPUTLBEntryFull *full; diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index d6725fd18c..c9fd4142f1 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -143,14 +143,14 @@ static int s390_probe_access(CPUArchState *env, targe= t_ulong addr, int size, bool nonfault, void **phost, uintptr_t ra) { #if defined(CONFIG_USER_ONLY) - return probe_access_flags(env, addr, access_type, mmu_idx, + return probe_access_flags(env, addr, 0, access_type, mmu_idx, nonfault, phost, ra); #else int flags; =20 env->tlb_fill_exc =3D 0; - flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nonfault= , phost, - ra); + flags =3D probe_access_flags(env, addr, 0, access_type, mmu_idx, + nonfault, phost, ra); if (env->tlb_fill_exc) { return env->tlb_fill_exc; } --=20 2.39.2