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([189.110.112.117]) by smtp.gmail.com with ESMTPSA id zf48-20020a0568716ab000b001722c5625e2sm3604123oab.7.2023.02.24.09.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:45:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1gVj1M/nMMH0BmloQmU2g5NSrvMNYo6IEPm887UKzGc=; b=eJY3xBwolzpInIB7rOU3kyaPTbjJB7++DPwsY5CttIs8rZHnrboU1mlhl2nCvDUyK0 cKaHd/v4xZEDBWcVg7z8TS81nkIPlKw91abwdbkPUY3P279JuhIluxjSPHxV1V5/YwKZ 3DXEv+ICnvsyKvvExFUYqTwD69ZRYyDRCrlAzDg9DOnvs8j0+09EZaRYI1qinSEpzMls YiIQnwOLBK5ZMS2jFyRLhkpUjOxeW0fCtA42r6LA54FzcAOO9geVMEEUMrL2pibFoLS8 hvxSPwGBbIGO77Nf+26pUfm17bPqg8N24bzaq25gbSwSF0mFC0Rnt1Zt1Zf7xPDGXQRg H22A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1gVj1M/nMMH0BmloQmU2g5NSrvMNYo6IEPm887UKzGc=; b=oN346kFZv4RlS4Almf2jyDksXxGVE/BgOBFXRWR/3K6JW40s+Xt/DRYsUvYkGVYU++ v6xw2qIxQ2K7gZZqUaI0goq7bPakkDy/Bv5VE3UAvFDO7gWJj3U+DhnH8ohi/aAK3jJ9 dxg9+ekvqweU47HHfAbp1/QCMRlWX9b0+WlKGbzJ5wHpaDA2rypJQqxqsuvjImmy+Bjv aL19xDG4HZEaJpGLEdf3KdbsRhvn9UlQ1jiLs3ReCSnhTMmMSIpZQTREKBojSMdVucEl W2PBSdfFisToMcb5XjX8GT4xTHUoLqeonOOir1ooflg20Qf938AY9oXIIfiNZ2NTWl9r 6Kqw== X-Gm-Message-State: AO0yUKU+TwlWSE49phxqfLtzTojTJV0iWdt9uhfBhVRq+XQjTlQkiknh N/E0zFYbUI1hMWjRKhvt5mWTfXkFGRbl2B7A X-Google-Smtp-Source: AK7set/D0pwYYZjL58HKINwGMyDbioDkqwpNFsyhI6j89o0s7cP/Wcp7sTu1cc0nEfHqmoD9JaSDDA== X-Received: by 2002:a05:6870:8a2b:b0:163:51eb:b577 with SMTP id p43-20020a0568708a2b00b0016351ebb577mr13495298oaq.46.1677260732497; Fri, 24 Feb 2023 09:45:32 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH 2/4] target/riscv/csr.c: simplify mctr() Date: Fri, 24 Feb 2023 14:45:18 -0300 Message-Id: <20230224174520.92490-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224174520.92490-1-dbarboza@ventanamicro.com> References: <20230224174520.92490-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1677260830020100005 Content-Type: text/plain; charset="utf-8" Use riscv_cpu_cfg() to retrieve pmu_num. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/csr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3692617d13..0f4aa22a0f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -165,8 +165,7 @@ static RISCVException ctr32(CPURISCVState *env, int csr= no) #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); + int pmu_num =3D riscv_cpu_cfg(env)->pmu_num; int ctr_index; int base_csrno =3D CSR_MHPMCOUNTER3; =20 @@ -175,7 +174,7 @@ static RISCVException mctr(CPURISCVState *env, int csrn= o) base_csrno +=3D 0x80; } ctr_index =3D csrno - base_csrno; - if (!cpu->cfg.pmu_num || ctr_index >=3D cpu->cfg.pmu_num) { + if (!pmu_num || ctr_index >=3D pmu_num) { /* The PMU is not enabled or counter is out of range*/ return RISCV_EXCP_ILLEGAL_INST; } --=20 2.39.2