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([189.110.112.117]) by smtp.gmail.com with ESMTPSA id zf48-20020a0568716ab000b001722c5625e2sm3604123oab.7.2023.02.24.09.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:45:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yq+sgSEsm/UWUCBr+CXkx2Nf6xLVC+0m9hNthdUCKgc=; b=gduwjqQgB+5YL816A9MujgjLziGFVDHxtHX86mxk9XyU/4UajWq2LpeagHwZFTwAhf aYAhLnlnDa6y12gV8z59tufLVu3cg8jRgC8Gl/Vo+EHLr46s2rF+/UR2kWgVSJM26p7c r+IpRA8JECGajYpoZqsJXCPp1V6OIIFRgjUgsHLwck6LdHfgO/mVtfgObseDjgTMDefg y8Ntv+BInBi/mIYjYw6NCeXntennVpOcMek+2myy/WwpV1kTVOWQJykeYGgvlzwy0Kmb Elkf5viQVSlMXJOPfa9pQnBJpiF7PzsWpTt+tf2L27zNRMF36Dj4Oi4Bf2u7h8XUBI9d WNsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yq+sgSEsm/UWUCBr+CXkx2Nf6xLVC+0m9hNthdUCKgc=; b=ddT0Hy5lFS4DaXrVqxmGrTQQbiXZ+yF8NC7bJY+phipKuOrM2b1kth3pfPaMLL2TWC OmwktIaNtN21uUa/tqrTmNqDSnCN+/y6EqvA4I9yyp3J0Wy9LPNemm7t9tpi/7hW1coP 7zjCFD2iAweZYYSfAL3d+yyUSpbCC+1VTc69nVrPG9T30KYZ4Hi/syS4c7TmdIlVrbQi Tagy6kD6mzTb3JnZkQ8PVKgp9g5GAwxQS9HKgKQ4KswSStBQIfWPHE4oYGUGqz5t7rYq RdUl29EqNUeJtV6u/O57mHcHizaVhu1EzAcm0mKr29ZgGh+BYdA6yGwfayBBDzj/R0vU WGNA== X-Gm-Message-State: AO0yUKXs3kY1227YB7Pf4UBYzES05tr489PWgdrUFbTXZLs/tveJd1rW vH6AFVfNzObA1Rhm0moVvgPhypDRVHQZvPcw X-Google-Smtp-Source: AK7set8IFvZ63XpGJ7g6fy4whTMRjmESPSvOE8tw2yjHTm4m3VdOeqw/WOVC4L9EDwPTKL51/XxnPA== X-Received: by 2002:a05:6871:b2a:b0:16e:29f3:df8f with SMTP id fq42-20020a0568710b2a00b0016e29f3df8fmr14674771oab.29.1677260735257; Fri, 24 Feb 2023 09:45:35 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH 3/4] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers Date: Fri, 24 Feb 2023 14:45:19 -0300 Message-Id: <20230224174520.92490-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224174520.92490-1-dbarboza@ventanamicro.com> References: <20230224174520.92490-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1677260819948100001 Content-Type: text/plain; charset="utf-8" A common trend in this file is to retrieve a RISCVCPU pointer by first retrieving a CPUState pointer via env_cpu(). The CPU pointer is used only to access the RISCVCPUConfig object and nothing else. Let's use riscv_cpu_cfg() to access what we need directly without these 2 pointers. Suggested-by: LIU Zhiwei Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/csr.c | 50 +++++++++++----------------------------------- 1 file changed, 12 insertions(+), 38 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0f4aa22a0f..53f1a331f9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,10 +46,8 @@ static RISCVException smstateen_acc_ok(CPURISCVState *en= v, int index, uint64_t bit) { bool virt =3D riscv_cpu_virt_enabled(env); - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); =20 - if (env->priv =3D=3D PRV_M || !cpu->cfg.ext_smstateen) { + if (env->priv =3D=3D PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_NONE; } =20 @@ -81,7 +79,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env) && - !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + !riscv_cpu_cfg(env)->ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } #endif @@ -90,11 +88,9 @@ static RISCVException fs(CPURISCVState *env, int csrno) =20 static RISCVException vs(CPURISCVState *env, int csrno) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - if (env->misa_ext & RVV || - cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { + riscv_cpu_cfg(env)->ext_zve32f || + riscv_cpu_cfg(env)->ext_zve64f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; @@ -193,10 +189,7 @@ static RISCVException mctr32(CPURISCVState *env, int c= srno) =20 static RISCVException sscofpmf(CPURISCVState *env, int csrno) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - - if (!cpu->cfg.ext_sscofpmf) { + if (!riscv_cpu_cfg(env)->ext_sscofpmf) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -319,10 +312,7 @@ static RISCVException umode32(CPURISCVState *env, int = csrno) =20 static RISCVException mstateen(CPURISCVState *env, int csrno) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - - if (!cpu->cfg.ext_smstateen) { + if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -331,10 +321,7 @@ static RISCVException mstateen(CPURISCVState *env, int= csrno) =20 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int bas= e) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - - if (!cpu->cfg.ext_smstateen) { + if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -361,10 +348,8 @@ static RISCVException sstateen(CPURISCVState *env, int= csrno) { bool virt =3D riscv_cpu_virt_enabled(env); int index =3D csrno - CSR_SSTATEEN0; - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); =20 - if (!cpu->cfg.ext_smstateen) { + if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -916,11 +901,9 @@ static RISCVException read_timeh(CPURISCVState *env, i= nt csrno, =20 static RISCVException sstc(CPURISCVState *env, int csrno) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); bool hmode_check =3D false; =20 - if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { + if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -1150,30 +1133,21 @@ static RISCVException write_ignore(CPURISCVState *e= nv, int csrno, static RISCVException read_mvendorid(CPURISCVState *env, int csrno, target_ulong *val) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - - *val =3D cpu->cfg.mvendorid; + *val =3D riscv_cpu_cfg(env)->mvendorid; return RISCV_EXCP_NONE; } =20 static RISCVException read_marchid(CPURISCVState *env, int csrno, target_ulong *val) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - - *val =3D cpu->cfg.marchid; + *val =3D riscv_cpu_cfg(env)->marchid; return RISCV_EXCP_NONE; } =20 static RISCVException read_mimpid(CPURISCVState *env, int csrno, target_ulong *val) { - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - - *val =3D cpu->cfg.mimpid; + *val =3D riscv_cpu_cfg(env)->mimpid; return RISCV_EXCP_NONE; } =20 --=20 2.39.2