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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id 26-20020aa7921a000000b00592417157f2sm843114pfo.148.2023.02.25.01.19.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Feb 2023 01:19:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BOxM+Tb1bwmnIEw8dgEhWm1s4rF8ejPxKOa7NUQZfU4=; b=sT7RtYuPLKxOiqyYPM8KS1XQRDVfNkxBwcsoj+UawZfLC8X+/pOkaOX/pfgyX1TJem Prv2SsfWjbXm5mcVdBa8nvdljWULfbr6IYw7SXsPimS+9o498Nt0O/WthFa9EIWSBBIu HiojcBzJpNc4KppcplOeHoZRhuyaNCk1jgt0qIyiQb13cQQhYEE64j1IHsAGL/MYnk0E DprHq+Z1EC7mWP7PzmAkCiG/KbhYhZiBM8BQ7rMDBugGnKp6Z0i7D047hIyP5lUhQhKw 6uM9y87z8oHL60IPW5OLIj5uWEjt8XsS+ccoHC7Ylo4jj+wnFLPb15JeeCIApKN4+qZ+ 5Xdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BOxM+Tb1bwmnIEw8dgEhWm1s4rF8ejPxKOa7NUQZfU4=; b=nGoc0RYdXm7D52xWNKKCdM3GNg7xsCUWqxFNdmtYTxLvbC7tkG+W7gO2gnx1WW7ay7 skh9Bwg+G2jZ6rmoC4veJ4LLtutP4W1xpqoqP1sBKHkuGxGUTvUo5RZ8lWxDvdEdJzl2 In1FLJqoUdwSkhZyKubBUJTaR9M9YWHFKH9/ZMHoJ7It9pH55cd0r4MA7FUUQ7R8vwAx itvBAtbUmNGO3e+cYm3WKeaBshbU9UhcysYc9QtHbT6CGPaD4GAlMkLLfim2cv1d0fjS bcOHia59LCEtaQOE1zCNZ2wRZlVMLeTISqG0yHyP+7GorN0tCyyug4xPoWwspYEE4EJs aJyg== X-Gm-Message-State: AO0yUKU1mdXA2leuxunvieD4Cge5vgtUSue9U3wgdhkFEma1N3qkVDbu yC4cdO+ipN80lEzVYK5+Yd6ctHtSEMB+s0wskv+pjQ== X-Google-Smtp-Source: AK7set/SSsyArhDi2S8aTfTSwWUs4FZ9YEYfG4YE4VIyXrTFAznS30POs3rAsawmYk+WKmkLp5IylQ== X-Received: by 2002:a05:6a20:9148:b0:cc:dca8:cfdc with SMTP id x8-20020a056a20914800b000ccdca8cfdcmr517085pzc.2.1677316785918; Sat, 25 Feb 2023 01:19:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH 51/76] target/riscv: Drop ftemp_new Date: Fri, 24 Feb 2023 23:14:02 -1000 Message-Id: <20230225091427.1817156-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230225091427.1817156-1-richard.henderson@linaro.org> References: <20230225091427.1817156-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677317386536100008 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new_i64. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/translate.c | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f9d5d1097e..273e566d66 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -106,9 +106,6 @@ typedef struct DisasContext { TCGv zero; /* Space for 3 operands plus 1 extra for address computation. */ TCGv temp[4]; - /* Space for 4 operands(1 dest and <=3D3 src) for float point computat= ion */ - TCGv_i64 ftemp[4]; - uint8_t nftemp; /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; @@ -431,12 +428,6 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_= num, TCGv rl, TCGv rh) } } =20 -static TCGv_i64 ftemp_new(DisasContext *ctx) -{ - assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); - return ctx->ftemp[ctx->nftemp++] =3D tcg_temp_new_i64(); -} - static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) { if (!ctx->cfg_ptr->ext_zfinx) { @@ -450,7 +441,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_n= um) case MXL_RV32: #ifdef TARGET_RISCV32 { - TCGv_i64 t =3D ftemp_new(ctx); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); return t; } @@ -476,7 +467,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_nu= m) switch (get_xl(ctx)) { case MXL_RV32: { - TCGv_i64 t =3D ftemp_new(ctx); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); return t; } @@ -496,12 +487,12 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_n= um) } =20 if (reg_num =3D=3D 0) { - return ftemp_new(ctx); + return tcg_temp_new_i64(); } =20 switch (get_xl(ctx)) { case MXL_RV32: - return ftemp_new(ctx); + return tcg_temp_new_i64(); #ifdef TARGET_RISCV64 case MXL_RV64: return cpu_gpr[reg_num]; @@ -1207,8 +1198,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); - ctx->nftemp =3D 0; - memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); @@ -1244,11 +1233,6 @@ static void riscv_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) ctx->temp[i] =3D NULL; } ctx->ntemp =3D 0; - for (i =3D ctx->nftemp - 1; i >=3D 0; --i) { - tcg_temp_free_i64(ctx->ftemp[i]); - ctx->ftemp[i] =3D NULL; - } - ctx->nftemp =3D 0; =20 /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { --=20 2.34.1