From nobody Wed May 14 03:25:02 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1677345053; cv=none; d=zohomail.com; s=zohoarc; b=HrOh9u7El7xEj0qu4nCtvDeivZDfZchxQPjLA78w2aT5ec/4MKLBNgLFjuNpu0s4BKECzbN9io7AEShNq6aIwjmcAgp8SwuERholJjN9DQM8XWt/YZyIJOawT6CidvjIDKJPNB+x3g3YY/C1afzGkpvt52tJcpJaruTRrha2tVE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677345053; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=URC4QULn1s6Vm1JS2+nnjxOu3AuTbC5LZ+8A63obzbk=; b=U3AJ1p5r/wCO7E7DIym4UEQx7go7ONIejlOo6fcE3EfUeCrZeZeaBUiKIJ6FL2NZgxK3I9JD1sLni6B7NK5Hi+B1eHLKe5cUNZV2IF4hgwbTZUgiI7kFZe2J9SN4lcU4dm/6ox1ur1wQACqsGSh/FKkMQVvwxuxJvzPSS9LlRz0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677345053081168.6808612284318; Sat, 25 Feb 2023 09:10:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pVy2z-0001c3-Hr; Sat, 25 Feb 2023 12:09:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pVy2x-0001ab-Tf; Sat, 25 Feb 2023 12:09:19 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pVy2v-0005co-HO; Sat, 25 Feb 2023 12:09:19 -0500 Received: by mail-ed1-x52d.google.com with SMTP id cq23so9535368edb.1; Sat, 25 Feb 2023 09:09:16 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf06ee000578a61baa078133.dip0.t-ipconnect.de. [2003:fa:af06:ee00:578:a61b:aa07:8133]) by smtp.gmail.com with ESMTPSA id t6-20020a17090616c600b008d356cafaedsm989066ejd.40.2023.02.25.09.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Feb 2023 09:09:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=URC4QULn1s6Vm1JS2+nnjxOu3AuTbC5LZ+8A63obzbk=; b=dieEEyiDTvB7t7aoMeXFfM18WiGE9+IoqB7nDW1gfo85+2R/tvrv4BBuzU8dOeR1Pe Y1rN3PX/D2raoI7eEqPpNgg/6RJScEGgbVH6gHjs6TB+iny/6elfKGIj4rpnwXloGeWA Ud/3NH+5IgCbb0bbo+cSX9Ck9afioJHwserHD+vTsCxjEya6NiZ1QSugA6G8WbkjbMds iAkJS21S45uX31p57WP1CON80FnY8fgJXMQ37OxRBoo5N8M/k0moo4G3UNkhtReQzqPe 9GV8fOaeXaEca0Wl3H++VHaUNocHjmOEBAoRCVzJVi7LiVnYOlUI3hHVhM/76GEChKGr 3kkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=URC4QULn1s6Vm1JS2+nnjxOu3AuTbC5LZ+8A63obzbk=; b=QkRVzyTDAcZ2YoZvTMCKzvJwOqC4OORvOiQ32J28biRGfNI9Zjb9Jyfrc0YwkWTrLR eWT7xSbTAwSHmoD4GoyiNCbn+g7fewYdewtkPCanNuWx/lzEQWCxAggYXkMItqSBK9BC vnx9ghYlQJc80y1bv+WoDYdRtGCDL2GLa1TqyX028CgCYQrTWdJ8+wDIkq/ECduPcNRq l+o5o4tLfg4+P+rARKyP1m7AkcYUxPxao76hHTRD+Dd1JkJyikz9hVkbPMENAWARPaDG 3XweYVd8vdAAhTvnOlxclkMWtuNdSM6+nrt/1Q+jXO9a8OdxdI0Uo84BoNtyDdYj5bYX SXsA== X-Gm-Message-State: AO0yUKVMPV/lnwZnk/uSPPKpzMt2exDCbJYswH9fU5M67nqf3p949iC9 66gAbqRihNbxD13dFOQ16WgzgAz0l5dVAg== X-Google-Smtp-Source: AK7set8RudUZM7uL76kAOH5izV1ijB9Vkgt50kyP/gJH4t04XiPzpJtw5WK4HdAZ561wlNVeGHT6Xg== X-Received: by 2002:a17:906:2610:b0:8b1:2e7c:df49 with SMTP id h16-20020a170906261000b008b12e7cdf49mr26114898ejc.7.1677344955454; Sat, 25 Feb 2023 09:09:15 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Gerd Hoffmann , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, BALATON Zoltan , Bernhard Beschow Subject: [PATCH v2 2/3] hw/isa/vt82c686: Implement PCI IRQ routing Date: Sat, 25 Feb 2023 18:08:56 +0100 Message-Id: <20230225170857.15774-3-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230225170857.15774-1-shentey@gmail.com> References: <20230225170857.15774-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677345054903100003 Content-Type: text/plain; charset="utf-8" The real VIA south bridges implement a PCI IRQ router which is configured by the BIOS or the OS. In order to respect these configurations, QEMU needs to implement it as well. Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 3f9bd0c04d..f24e387d63 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -604,6 +604,48 @@ static void via_isa_request_i8259_irq(void *opaque, in= t irq, int level) qemu_set_irq(s->cpu_intr, level); } =20 +static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num) +{ + switch (irq_num) { + case 0: + return s->dev.config[0x55] >> 4; + + case 1: + return s->dev.config[0x56] & 0xf; + + case 2: + return s->dev.config[0x56] >> 4; + + case 3: + return s->dev.config[0x57] >> 4; + } + + return 0; +} + +static void via_isa_set_pci_irq(void *opaque, int irq_num, int level) +{ + ViaISAState *s =3D opaque; + PCIBus *bus =3D pci_get_bus(&s->dev); + int pic_irq; + + /* now we change the pic irq level according to the via irq mappings */ + /* XXX: optimize */ + pic_irq =3D via_isa_get_pci_irq(s, irq_num); + if (pic_irq < ISA_NUM_IRQS) { + int i, pic_level; + + /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ + pic_level =3D 0; + for (i =3D 0; i < PCI_NUM_PINS; i++) { + if (pic_irq =3D=3D via_isa_get_pci_irq(s, i)) { + pic_level |=3D pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(s->isa_irqs[pic_irq], pic_level); + } +} + static void via_isa_realize(PCIDevice *d, Error **errp) { ViaISAState *s =3D VIA_ISA(d); @@ -676,6 +718,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp) if (!qdev_realize(DEVICE(&s->mc97), BUS(pci_bus), errp)) { return; } + + pci_bus_irqs(pci_bus, via_isa_set_pci_irq, s, PCI_NUM_PINS); } =20 /* TYPE_VT82C686B_ISA */ --=20 2.39.2