Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added code to set the tail elements to 1 in
the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and
vext_ldff(). Aside from a env->vl versus an evl value being used in the
first loop, the code is being repeated 4 times.
Create a helper to avoid code repetition in all those functions.
Arguments that are used in the callers (nf, esz and max_elems) are
passed as arguments. All other values are being derived inside the
helper.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/vector_helper.c | 86 +++++++++++++-----------------------
1 file changed, 30 insertions(+), 56 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 00de879787..7d2e3978f1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -267,6 +267,28 @@ GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq)
+static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
+ void *vd, uint32_t desc, uint32_t nf,
+ uint32_t esz, uint32_t max_elems)
+{
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+ uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ uint32_t vta = vext_vta(desc);
+ uint32_t registers_used;
+ int k;
+
+ for (k = 0; k < nf; ++k) {
+ vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
+ (k * max_elems + max_elems) * esz);
+ }
+
+ if (nf * max_elems % total_elems != 0) {
+ registers_used = ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
+ vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
+ registers_used * vlenb);
+ }
+}
+
/*
*** stride: access vector element from strided memory
*/
@@ -281,8 +303,6 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t nf = vext_nf(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vta = vext_vta(desc);
uint32_t vma = vext_vma(desc);
for (i = env->vstart; i < env->vl; i++, env->vstart++) {
@@ -301,18 +321,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
}
env->vstart = 0;
- /* set tail elements to 1s */
- for (k = 0; k < nf; ++k) {
- vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
- (k * max_elems + max_elems) * esz);
- }
- if (nf * max_elems % total_elems != 0) {
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
- uint32_t registers_used =
- ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
+
+ vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \
@@ -359,8 +369,6 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
uint32_t nf = vext_nf(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vta = vext_vta(desc);
/* load bytes from guest memory */
for (i = env->vstart; i < evl; i++, env->vstart++) {
@@ -372,18 +380,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
}
}
env->vstart = 0;
- /* set tail elements to 1s */
- for (k = 0; k < nf; ++k) {
- vext_set_elems_1s(vd, vta, (k * max_elems + evl) * esz,
- (k * max_elems + max_elems) * esz);
- }
- if (nf * max_elems % total_elems != 0) {
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
- uint32_t registers_used =
- ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
+
+ vext_set_tail_elems_1s(env, evl, vd, desc, nf, esz, max_elems);
}
/*
@@ -484,8 +482,6 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t vm = vext_vm(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vta = vext_vta(desc);
uint32_t vma = vext_vma(desc);
/* load bytes from guest memory */
@@ -505,18 +501,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
}
env->vstart = 0;
- /* set tail elements to 1s */
- for (k = 0; k < nf; ++k) {
- vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
- (k * max_elems + max_elems) * esz);
- }
- if (nf * max_elems % total_elems != 0) {
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
- uint32_t registers_used =
- ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
+
+ vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \
@@ -585,8 +571,6 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t vm = vext_vm(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vta = vext_vta(desc);
uint32_t vma = vext_vma(desc);
target_ulong addr, offset, remain;
@@ -647,18 +631,8 @@ ProbeSuccess:
}
}
env->vstart = 0;
- /* set tail elements to 1s */
- for (k = 0; k < nf; ++k) {
- vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
- (k * max_elems + max_elems) * esz);
- }
- if (nf * max_elems % total_elems != 0) {
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
- uint32_t registers_used =
- ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
+
+ vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \
--
2.39.2On 26/2/23 18:05, Daniel Henrique Barboza wrote:
> Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
> load / store instructions") added code to set the tail elements to 1 in
> the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and
> vext_ldff(). Aside from a env->vl versus an evl value being used in the
> first loop, the code is being repeated 4 times.
>
> Create a helper to avoid code repetition in all those functions.
> Arguments that are used in the callers (nf, esz and max_elems) are
> passed as arguments. All other values are being derived inside the
> helper.
>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/vector_helper.c | 86 +++++++++++++-----------------------
> 1 file changed, 30 insertions(+), 56 deletions(-)
> +static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
> + void *vd, uint32_t desc, uint32_t nf,
> + uint32_t esz, uint32_t max_elems)
> +{
> + uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> + uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> + uint32_t vta = vext_vta(desc);
> + uint32_t registers_used;
> + int k;
> +
> + for (k = 0; k < nf; ++k) {
> + vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
> + (k * max_elems + max_elems) * esz);
> + }
> +
> + if (nf * max_elems % total_elems != 0) {
> + registers_used = ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
> + vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
> + registers_used * vlenb);
> + }
for (unsigned k = 0; k < nf; ++k) {
vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
(k * max_elems + max_elems) * esz);
}
if (nf * max_elems % total_elems != 0) {
uint32_t cnt = (nf * max_elems) * esz;
vext_set_elems_1s(vd, vta, cnt, QEMU_ALIGN_UP(cnt, vlenb));
}
I suspect ROUND_UP() could be used if vlenb is a power of 2.
On Sun, 26 Feb 2023 10:23:01 PST (-0800), philmd@linaro.org wrote:
> On 26/2/23 18:05, Daniel Henrique Barboza wrote:
>> Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
>> load / store instructions") added code to set the tail elements to 1 in
>> the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and
>> vext_ldff(). Aside from a env->vl versus an evl value being used in the
>> first loop, the code is being repeated 4 times.
>>
>> Create a helper to avoid code repetition in all those functions.
>> Arguments that are used in the callers (nf, esz and max_elems) are
>> passed as arguments. All other values are being derived inside the
>> helper.
>>
>> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Reviewed-by: Frank Chang <frank.chang@sifive.com>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/vector_helper.c | 86 +++++++++++++-----------------------
>> 1 file changed, 30 insertions(+), 56 deletions(-)
>
>
>> +static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
>> + void *vd, uint32_t desc, uint32_t nf,
>> + uint32_t esz, uint32_t max_elems)
>> +{
>> + uint32_t total_elems = vext_get_total_elems(env, desc, esz);
>> + uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
>> + uint32_t vta = vext_vta(desc);
>> + uint32_t registers_used;
>> + int k;
>> +
>> + for (k = 0; k < nf; ++k) {
>> + vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
>> + (k * max_elems + max_elems) * esz);
>> + }
>> +
>> + if (nf * max_elems % total_elems != 0) {
>> + registers_used = ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
>> + vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
>> + registers_used * vlenb);
>> + }
>
> for (unsigned k = 0; k < nf; ++k) {
> vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
> (k * max_elems + max_elems) * esz);
> }
>
> if (nf * max_elems % total_elems != 0) {
> uint32_t cnt = (nf * max_elems) * esz;
> vext_set_elems_1s(vd, vta, cnt, QEMU_ALIGN_UP(cnt, vlenb));
> }
>
> I suspect ROUND_UP() could be used if vlenb is a power of 2.
As far as I can tell there's nothing in the ISA that requires vlenb be a
power of two, it's just defined as
The XLEN-bit-wide read-only CSR vlenb holds the value VLEN/8, i.e.,
the vector register length in bytes.
I'm pretty surprised to see that's the case and I'd doubt anything
actually works with non-power-of-two vlenb. It's possible I'm just
missing something in the ISA so I opened a bug at
<https://github.com/riscv/riscv-v-spec/issues/864>.
© 2016 - 2026 Red Hat, Inc.